147 lines
3.5 KiB
C
147 lines
3.5 KiB
C
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/*
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* Device Tree support for Allwinner A1X SoCs
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clocksource.h>
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/sunxi-sid.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mcpm.h>
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#include "sunxi.h"
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static struct map_desc sunxi_io_desc[] __initdata = {
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{
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.virtual = (unsigned long) IO_ADDRESS(SUNXI_IO_PBASE),
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.pfn = __phys_to_pfn(SUNXI_IO_PBASE),
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.length = SUNXI_IO_SIZE,
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.type = MT_DEVICE,
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},
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#if defined CONFIG_ARCH_SUN8IW10P1 || defined CONFIG_ARCH_SUN8IW8P1
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{
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.virtual = (unsigned long)IO_ADDRESS(SUNXI_SRAM_A1_PBASE),
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.pfn = __phys_to_pfn(SUNXI_SRAM_A1_PBASE),
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.length = SUNXI_SRAM_A1_SIZE,
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.type = MT_MEMORY_ITCM,
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},
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{
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.virtual = (unsigned long)IO_ADDRESS(SUNXI_SRAM_C_PBASE),
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.pfn = __phys_to_pfn(SUNXI_SRAM_C_PBASE),
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.length = SUNXI_SRAM_C_SIZE,
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.type = MT_MEMORY_ITCM,
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},
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#endif
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#if defined(CONFIG_ARCH_SUN8IW11P1)
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{
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.virtual = (unsigned long)IO_ADDRESS(SUNXI_SRAM_A_PBASE),
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.pfn = __phys_to_pfn(SUNXI_SRAM_A_PBASE),
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.length = SUNXI_SRAM_A_SIZE,
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.type = MT_MEMORY_ITCM,
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},
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#endif
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#if defined(CONFIG_ARCH_SUN8IW17P1)
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{
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.virtual = (unsigned long)IO_ADDRESS(SUNXI_SRAM_A1_PBASE),
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.pfn = __phys_to_pfn(SUNXI_SRAM_A1_PBASE),
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.length = SUNXI_SRAM_A1_SIZE,
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.type = MT_MEMORY_ITCM,
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},
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{
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.virtual = (unsigned long)IO_ADDRESS(SUNXI_SRAM_C_PBASE),
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.pfn = __phys_to_pfn(SUNXI_SRAM_C_PBASE),
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.length = SUNXI_SRAM_C_SIZE,
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.type = MT_MEMORY_ITCM,
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},
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{
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.virtual = (unsigned long)IO_ADDRESS(SUNXI_SRAM_A2_PBASE),
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.pfn = __phys_to_pfn(SUNXI_SRAM_A2_PBASE),
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.length = SUNXI_SRAM_A2_SIZE,
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.type = MT_MEMORY_ITCM,
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},
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#endif
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#if defined(CONFIG_ARCH_SUN8IW5P1)
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{
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.virtual = (unsigned long)IO_ADDRESS(SUNXI_SRAM_A1_PBASE),
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.pfn = __phys_to_pfn(SUNXI_SRAM_A1_PBASE),
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.length = SUNXI_SRAM_A1_SIZE,
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.type = MT_MEMORY_ITCM,
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},
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{
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.virtual = (unsigned long)IO_ADDRESS(SUNXI_SRAM_A2_PBASE),
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.pfn = __phys_to_pfn(SUNXI_SRAM_A2_PBASE),
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.length = SUNXI_SRAM_A2_SIZE,
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.type = MT_DEVICE_NONSHARED,
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},
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#endif
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};
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void __init sunxi_map_io(void)
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{
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iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
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#ifdef CONFIG_SUNXI_TRUSTZONE
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sunxi_firmware_init();
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#endif
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}
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static void __init sunxi_timer_init(void)
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{
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of_clk_init(NULL);
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#ifdef CONFIG_COMMON_CLK_ENABLE_SYNCBOOT_EARLY
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clk_syncboot();
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#endif
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clocksource_of_init();
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}
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static const char * const sunxi_board_dt_compat[] = {
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"allwinner,sun4i-a10",
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"allwinner,sun5i-a13",
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"arm,sun8iw10p1",
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"arm,sun8iw11p1",
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"arm,sun8iw17p1",
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"arm,sun8iw8p1",
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"arm,sun8iw5p1",
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NULL,
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};
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#ifdef CONFIG_SMP
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static bool __init sun8i_smp_init_ops(void)
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{
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#ifdef CONFIG_MCPM
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/* the mcpm smp ops just use for MCPM platform */
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early_printk("------%s----%d-----\n", __func__, __LINE__);
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mcpm_smp_set_ops();
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return true;
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#else
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/* default use machine_desc->smp ops */
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return false;
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#endif
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}
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#endif
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DT_MACHINE_START(SUNXI_DT, CONFIG_SUNXI_SOC_NAME)
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#ifdef CONFIG_SMP
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.smp_init = smp_init_ops(sun8i_smp_init_ops),
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#ifndef CONFIG_MCPM
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.smp = smp_ops(sunxi_smp_ops),
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#endif
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#endif
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.map_io = sunxi_map_io,
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.init_time = sunxi_timer_init,
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.dt_compat = sunxi_board_dt_compat,
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MACHINE_END
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