69 lines
1.5 KiB
ArmAsm
69 lines
1.5 KiB
ArmAsm
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/*
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* arch/arm/include/asm/tc2_pm_setup.S
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*
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* Created by: Nicolas Pitre, October 2012
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( (based on dcscb_setup.S by Dave Martin)
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* Copyright: (C) 2012 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/mcpm.h>
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#define SPC_PHYS_BASE 0x7FFF0000
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#define SPC_WAKE_INT_STAT 0xb2c
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#define SNOOP_CTL_A15 0x404
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#define SNOOP_CTL_A7 0x504
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#define A15_SNOOP_MASK (0x3 << 7)
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#define A7_SNOOP_MASK (0x1 << 13)
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#define A15_BX_ADDR0 0xB68
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ENTRY(tc2_resume)
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mrc p15, 0, r0, c0, c0, 5
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ubfx r1, r0, #0, #4 @ r1 = cpu
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ubfx r2, r0, #8, #4 @ r2 = cluster
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add r1, r1, r2, lsl #2 @ r1 = index of CPU in WAKE_INT_STAT
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ldr r3, =SPC_PHYS_BASE + SPC_WAKE_INT_STAT
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ldr r3, [r3]
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lsr r3, r1
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tst r3, #1
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wfieq @ if no pending IRQ reenters wfi
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b mcpm_entry_point
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ENDPROC(tc2_resume)
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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* The ACTLR SMP bit does not need to be set here, because cpu_resume()
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* already restores that.
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*/
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ENTRY(tc2_pm_power_up_setup)
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cmp r0, #0
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beq 2f
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b cci_enable_port_for_self
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2: @ Clear the BX addr register
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ldr r3, =SPC_PHYS_BASE + A15_BX_ADDR0
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mrc p15, 0, r0, c0, c0, 5 @ MPIDR
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ubfx r1, r0, #8, #4 @ cluster
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ubfx r0, r0, #0, #4 @ cpu
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add r3, r3, r1, lsl #4
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mov r1, #0
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str r1, [r3, r0, lsl #2]
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dsb
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bx lr
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ENDPROC(tc2_pm_power_up_setup)
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