86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
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/*
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* Copyright (C) 2016 Allwinnertech, czy <chenzunyin@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable factor-based clock implementation
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*/
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#ifndef __MACH_SUNXI_CLK_SUN3IW1_H
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#define __MACH_SUNXI_CLK_SUN3IW1_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include "clk-factors.h"
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#define PLL_CPU 0x0000
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#define PLL_AUDIO 0x0008
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#define PLL_VIDEO 0x0010
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#define PLL_VE 0x0018
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#define PLL_DDR 0x0020
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#define PLL_PERIPH 0x0028
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#define CPU_CFG 0x0050
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#define AHB1_CFG 0x0054
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#define BUS_GATE0 0x0060
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#define BUS_GATE1 0x0064
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#define BUS_GATE2 0x0068
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#define SD0_CFG 0x0088
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#define SD1_CFG 0x008c
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#define AUDIO_CFG 0x00B0
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#define SPDIF_CFG 0x00B4
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#define CIR_CFG 0x00B8
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#define USB_CFG 0x00CC
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#define DRAM_GATE 0x0100
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#define BE_CFG 0x0104
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#define FE_CFG 0x010C
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#define TCON_CFG 0x0118
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#define DEINTERLACE_CFG 0x011C
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#define TVE_CFG 0x0120
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#define TVD_CFG 0x0124
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#define CSI_CFG 0x0134
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#define VE_CFG 0x013C
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#define CODEC_CFG 0x0140
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#define AVS_CFG 0x0144
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#define PLL_LOCK 0x0200
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#define CPU_LOCK 0x0204
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#define PLL_AUDIOPAT 0x0284
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#define PLL_VIDEOPAT 0x0288
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#define PLL_DDRPAT 0x0290
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#define BUS_RST0 0x02C0
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#define BUS_RST1 0x02C4
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#define BUS_RST2 0x02D0
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#define SUNXI_CLK_MAX_REG 0x02D0
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#define F_N8X7_M0X4(nv, mv) FACTOR_ALL(nv, 8, 7, 0, 0, 0, mv,\
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0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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#define F_N8X5_K4X2(nv, kv) FACTOR_ALL(nv, 8, 5, kv, 4, 2, 0,\
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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#define F_N8X7_M0X2(nv, mv) FACTOR_ALL(nv, 8, 7, 0, 0, 0, mv,\
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0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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#define F_N8X5_K4X2_M0X2(nv, kv, mv) FACTOR_ALL(nv, 8, 5, kv,\
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4, 2, mv, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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#define F_N8X5_K4X2_M0X2_P16x2(nv, kv, mv, pv) \
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FACTOR_ALL(nv, 8, 5, \
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kv, 4, 2, \
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mv, 0, 2, \
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pv, 16, 2,\
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0, 0, 0, 0, 0, 0)
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#define F_N8X7_N116X5_M0X2_M14x4(nv, kv, mv, pv) \
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FACTOR_ALL(nv, 8, 7, \
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kv, 16, 5, \
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mv, 0, 2, \
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pv, 4, 4, \
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0, 0, 0, 0, 0, 0)
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#define PLLCPU(n, k, m, p, freq) \
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{F_N8X5_K4X2_M0X2_P16x2(n, k, m, p), freq}
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#define PLLVIDEO(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLVE(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLDDR(n, k, m, freq) {F_N8X5_K4X2_M0X2(n, k, m), freq}
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#define PLLPERIPH(n, k, freq) {F_N8X5_K4X2(n, k), freq}
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#endif
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