107 lines
4.1 KiB
C
107 lines
4.1 KiB
C
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#ifndef _PM_CONFIG_SUN8IW6P1_H
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#define _PM_CONFIG_SUN8IW6P1_H
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/*
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* Copyright (c) 2011-2015 yanggq.young@allwinnertech.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include "pm_def_i.h"
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#include "mach/platform.h"
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#include "mach/memory.h"
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#include "asm-generic/sizes.h"
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/*#include <generated/autoconf.h>*/
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#include "mach/irqs.h"
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/*debug reg*/
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#if 1 /*for real ic */
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#define STANDBY_STATUS_REG_PA (SUNXI_R_PRCM_PBASE + 0x1f0)
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#define STANDBY_STATUS_REG IO_ADDRESS((STANDBY_STATUS_REG_PA))
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#else
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#define STANDBY_STATUS_REG_PA (0x40000000 + 0x1f0)
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#define STANDBY_STATUS_REG (0xc0000000 + 0x1f0)
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#endif
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#define STANDBY_STATUS_REG_NUM (4) /*reg1 - reg3 is available. */
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/*module base reg*/
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#define AW_LRADC01_BASE (0x0) /*notice: fake addr */
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#define AW_CCM_BASE (SUNXI_CCM_PBASE)
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#define AW_CCM_MOD_BASE (SUNXI_CCM_PBASE)
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#define AW_CCM_PIO_BUS_GATE_REG_OFFSET (0x68)
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#define AW_CCU_UART_PA (AW_CCM_BASE + 0x6C) /*uart0 gating: bit16, 0: mask, 1: pass */
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#define AW_CCU_UART_RESET_PA (AW_CCM_BASE + 0x2D8) /*uart0 reset: bit16, 0: reset, 1: de_assert */
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/*uart & jtag para*/
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#define AW_JTAG_PH_GPIO_PA (0x01c20800 + 0x24) /*jtag0: Pb0-Pb3, */
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#define AW_JTAG_PF_GPIO_PA (0x01c20800 + 0xB4) /*jtag0: PF0, PF1, PF3, PF5 bitmap: 0x40, 4044; */
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#define AW_UART_PH_GPIO_PA (0x01c20800 + 0x28) /*uart0: use pB */
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#define AW_UART_PF_GPIO_PA (0x01c20800 + 0xB4) /*uart0: PF2, PF4, bitmap: 0x04, 0400; */
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#define AW_JTAG_PH_CONFIG_VAL_MASK (0x0000ffff)
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#define AW_JTAG_PH_CONFIG_VAL (0x00003333)
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#define AW_JTAG_PF_CONFIG_VAL_MASK (0x00f0f0ff)
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#define AW_JTAG_PF_CONFIG_VAL (0x00303033)
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#define AW_UART_PH_CONFIG_VAL_MASK (0x00000FF0)
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#define AW_UART_PH_CONFIG_VAL (0x00000220)
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#define AW_UART_PF_CONFIG_VAL_MASK (0x000F0F00)
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#define AW_UART_PF_CONFIG_VAL (0x00030300)
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#define AW_JTAG_GPIO_PA (AW_JTAG_PF_GPIO_PA)
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#define AW_UART_GPIO_PA (AW_UART_PF_GPIO_PA)
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#define AW_JTAG_CONFIG_VAL_MASK AW_JTAG_PF_CONFIG_VAL_MASK
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#define AW_JTAG_CONFIG_VAL AW_JTAG_PF_CONFIG_VAL
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#define AW_SPINLOCK_BASE (SUNXI_SPINLOCK_PBASE)
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#define AW_RTC_BASE (AW_SRAM_A1_BASE) /*notice: fake addr. */
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#define AW_SRAMCTRL_BASE (SUNXI_SRAMCTRL_PBASE)
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#define GPIO_REG_LENGTH ((0x31c+0x4)>>2) /*0x24 - 0x31c */
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#define CPUS_GPIO_REG_LENGTH ((0x300+0x4)>>2) /**/
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#define SRAM_REG_LENGTH ((0xf0+0x4)>>2)
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#define CCU_REG_LENGTH ((0x2d8+0x4)>>2)
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#define CCU_MOD_CLK_AHB1_RESET_SPINLOCK (AW_CCM_MOD_BASE + 0x2c4) /*bit22, 1:de-assert, 0: assert. */
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#define CCU_CLK_NRESET (0x1<<22)
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#define CCU_MOD_CLK_AHB1_GATING_SPINLOCK (AW_CCM_MOD_BASE + 0x64) /*bit22, 1: pass; 0: mask */
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#define CCU_CLK_ON (0x1<<22)
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/*irq src no.*/
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#define AW_IRQ_TIMER1 (SUNXI_IRQ_TIMER1)
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#define AW_IRQ_TOUCHPANEL (0)
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#define AW_IRQ_LRADC (SUNXI_IRQ_LRADC)
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#define AW_IRQ_NMI (SUNXI_IRQ_NMI)
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#define AW_IRQ_MBOX (SUNXI_IRQ_MBOX)
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#define AW_IRQ_WLAN (0)
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#define AW_IRQ_ALARM (0)
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#define AW_IRQ_IR0 (0)
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#define AW_IRQ_IR1 (0)
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#define AW_IRQ_USBOTG (SUNXI_IRQ_USBOTG)
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#define AW_IRQ_USBEHCI0 (SUNXI_IRQ_USBEHCI0)
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#define AW_IRQ_USBEHCI1 (SUNXI_IRQ_USBEHCI1)
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#define AW_IRQ_USBOHCI0 (SUNXI_IRQ_USBOHCI0)
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#define AW_IRQ_USBOHCI1 (0)
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#define AW_IRQ_USBEHCI2 (0)
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#define AW_IRQ_USBOHCI2 (0)
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#define AW_IRQ_GPIOA (0)
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#define AW_IRQ_GPIOB (SUNXI_IRQ_EINTB)
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#define AW_IRQ_GPIOC (0)
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#define AW_IRQ_GPIOD (0)
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#define AW_IRQ_GPIOE (0)
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#define AW_IRQ_GPIOF (0)
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#define AW_IRQ_GPIOG (SUNXI_IRQ_EINTG)
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#define AW_IRQ_GPIOH (SUNXI_IRQ_EINTH)
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#define AW_IRQ_GPIOI (0)
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#define AW_IRQ_GPIOJ (0)
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/**---stack point address in sram-------------*/
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/*
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* notice: try not to use last 0xc bytes,
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* considering the ds-5 debugger will access (last + 0xc) bytes with unknown reason,
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* which will hangup the soc.
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**/
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#define SP_IN_SRAM 0xf0003ff0 /*end of 16k */
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#define SP_IN_SRAM_PA 0x00003ff0 /*end of 16k */
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#define SP_IN_SRAM_START (SRAM_FUNC_START_PA | 0x3c00) /*15k */
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#endif /*_PM_CONFIG_SUN8IW6P1_H*/
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