156 lines
5.3 KiB
C
156 lines
5.3 KiB
C
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#ifndef _PM_CONFIG_H
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#define _PM_CONFIG_H
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/*
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* Copyright (c) 2011-2015 yanggq.young@allwinnertech.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include "uapi/linux/const.h"
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#include "pm_def_i.h"
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#include "asm-generic/sizes.h"
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/*#include <generated/autoconf.h>*/
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#if defined(CONFIG_ARCH_SUN8IW1P1) || defined(CONFIG_ARCH_SUN8IW3P1) \
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|| defined(CONFIG_ARCH_SUN8IW5P1) || defined(CONFIG_ARCH_SUN8IW6P1) \
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|| defined(CONFIG_ARCH_SUN8IW8P1) || defined(CONFIG_ARCH_SUN8IW17P1) \
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|| defined(CONFIG_ARCH_SUN9IW1P1) || defined(CONFIG_ARCH_SUN50IW1P1) \
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|| defined(CONFIG_ARCH_SUN50IW2P1) || defined(CONFIG_ARCH_SUN50IW3P1) \
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|| defined(CONFIG_ARCH_SUN50IW6P1)
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#include "pm_config_common.h"
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#endif
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/*hardware resource description*/
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#ifdef CONFIG_ARCH_SUN8IW1P1
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#include "pm_config-sun8iw1p1.h"
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#elif defined CONFIG_ARCH_SUN8IW3P1
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#include "pm_config-sun8iw3p1.h"
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#elif defined CONFIG_ARCH_SUN8IW5P1
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#include "pm_config-sun8iw5p1.h"
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#elif defined CONFIG_ARCH_SUN8IW6P1
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#include "pm_config-sun8iw6p1.h"
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#elif defined CONFIG_ARCH_SUN8IW8P1
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#include "pm_config-sun8iw8p1.h"
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#elif defined CONFIG_ARCH_SUN8IW10P1
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#include "pm_config-sun8iw10p1.h"
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#elif defined CONFIG_ARCH_SUN8IW11P1
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#include "pm_config-sun8iw11p1.h"
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#elif defined CONFIG_ARCH_SUN8IW17P1
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#include "pm_config-sun8iw17p1.h"
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#elif defined CONFIG_ARCH_SUN9IW1P1
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#include "pm_config-sun9iw1p1.h"
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#elif defined CONFIG_ARCH_SUN50IW1P1
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#include "pm_config-sun50iw1p1.h"
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#elif defined CONFIG_ARCH_SUN50IW2P1
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#include "pm_config-sun50iw2p1.h"
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#elif defined CONFIG_ARCH_SUN50IW3P1
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#include "pm_config-sun50iw3p1.h"
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#elif defined CONFIG_ARCH_SUN50IW6P1
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#include "pm_config-sun50iw6p1.h"
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#endif
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/*#define CHECK_IC_VERSION*/
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/*#define RETURN_FROM_RESUME0_WITH_MMU //suspend: 0xf000, resume0: 0xc010, resume1: 0xf000*/
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/*#define RETURN_FROM_RESUME0_WITH_NOMMU // suspend: 0x0000, resume0: 0x4010, resume1: 0x0000*/
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/*#define DIRECT_RETURN_FROM_SUSPEND //not support yet*/
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#define ENTER_SUPER_STANDBY /*suspend: 0xf000, resume0: 0x4010, resume1: 0x0000 */
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/*#define ENTER_SUPER_STANDBY_WITH_NOMMU //not support yet, suspend: 0x0000, resume0: 0x4010, resume1: 0x0000*/
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/*#define WATCH_DOG_RESET*/
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/*NOTICE: only need one definiton*/
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#define RESUME_FROM_RESUME1
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#ifdef CONFIG_ARCH_SUN4I
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#define PERMANENT_REG (0xf1c20d20)
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#define PERMANENT_REG_PA (0x01c20d20)
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#define STANDBY_STATUS_REG (0xf1c20d20)
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#define STANDBY_STATUS_REG_PA (0x01c20d20)
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#elif defined(CONFIG_ARCH_SUN5I)
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#define PERMANENT_REG (0xF1c0123c)
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#define PERMANENT_REG_PA (0x01c0123c)
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#define STANDBY_STATUS_REG (0xf0000740)
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#define STANDBY_STATUS_REG_PA (0x00000740)
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/*notice: the address is located in the last word of (DRAM_BACKUP_BASE_ADDR + DRAM_BACKUP_SIZE) */
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#define SUN5I_STANDBY_STATUS_REG (DRAM_BACKUP_BASE_ADDR + (DRAM_BACKUP_SIZE<<2) - 0x4)
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#define SUN5I_STANDBY_STATUS_REG_PA (DRAM_BACKUP_BASE_ADDR_PA + (DRAM_BACKUP_SIZE<<2) - 0x4)
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#endif
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#if defined(CONFIG_ARCH_SUN8I) || defined(CONFIG_ARCH_SUN9IW1P1)
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#define CORTEX_A7
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#endif
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/**********************************************platform separator *****************************************/
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#if defined(CONFIG_ARCH_SUN8I) && !defined(CONFIG_ARCH_SUN8IW17)
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/**start address for function run in sram*/
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#define SRAM_FUNC_START (0xf0000000)
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#define SRAM_FUNC_START_PA (0x00000000)
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/*for mem mapping*/
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#define MEM_SW_VA_SRAM_BASE (0x00000000)
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#define MEM_SW_PA_SRAM_BASE (0x00000000)
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/*dram area*/
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#define DRAM_BASE_ADDR_PA (0x40000000)
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#define DRAM_TRANING_SIZE (16)
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#define CPU_CLK_REST_DEFAULT_VAL (0x00010000) /*SRC is HOSC. */
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#endif
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#ifdef CONFIG_ARCH_SUN4I
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#define INT_REG_LENGTH ((0x90+0x4)>>2)
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#define GPIO_REG_LENGTH ((0x218+0x4)>>2)
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#define SRAM_REG_LENGTH ((0x94+0x4)>>2)
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#elif defined CONFIG_ARCH_SUN5I
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#define INT_REG_LENGTH ((0x94+0x4)>>2)
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#define GPIO_REG_LENGTH ((0x218+0x4)>>2)
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#define SRAM_REG_LENGTH ((0x94+0x4)>>2)
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#endif
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/*interrupt src definition.*/
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#define AW_IRQ_TIMER0 (SUNXI_IRQ_TIMER0)
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/*platform independant src config.*/
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#define AW_SRAM_A1_BASE (SUNXI_SRAM_A1_PBASE)
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#define AW_SRAM_A2_BASE (SUNXI_SRAM_A2_PBASE)
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#define AW_SRAM_A3_BASE (SUNXI_SRAM_A3_PBASE)
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#define AW_SRAM_C_BASE (SUNXI_SRAM_C_PBASE)
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#define AW_PIO_BASE (SUNXI_PIO_PBASE)
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#ifdef CONFIG_ARCH_SUN8IW8P1
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#else
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#define AW_R_PRCM_BASE (SUNXI_R_PRCM_PBASE)
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#define AW_TWI2_BASE (SUNXI_TWI2_PBASE)
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#define AW_MSGBOX_BASE (SUNXI_MSGBOX_PBASE)
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#define AW_SPINLOCK_BASE (SUNXI_SPINLOCK_PBASE)
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#define AW_R_PIO_BASE (SUNXI_R_PIO_PBASE)
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#endif
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#define AW_R_CPUCFG_BASE (SUNXI_R_CPUCFG_PBASE)
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#define AW_UART0_BASE (SUNXI_UART0_PBASE)
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#define AW_TWI0_BASE (SUNXI_TWI0_PBASE)
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#define AW_TWI1_BASE (SUNXI_TWI1_PBASE)
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#define AW_CPUCFG_P_REG0 (SUNXI_CPUCFG_P_REG0)
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#define AW_CPUCFG_GENCTL (SUNXI_CPUCFG_GENCTL)
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#define AW_CPUX_PWR_CLAMP(x) (SUNXI_CPUX_PWR_CLAMP(x))
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#define AW_CPUX_PWR_CLAMP_STATUS(x) (SUNXI_CPUX_PWR_CLAMP_STATUS(x))
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#define AW_CPU_PWROFF_REG (SUNXI_CPU_PWROFF_REG)
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#define SRAM_CTRL_REG1_ADDR_PA 0x01c00004
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#define SRAM_CTRL_REG1_ADDR_VA IO_ADDRESS(SRAM_CTRL_REG1_ADDR_PA)
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#define RUNTIME_CONTEXT_SIZE (14) /*r0-r13 */
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#define DRAM_COMPARE_DATA_ADDR (0xc0100000) /*1Mbytes offset */
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#define DRAM_COMPARE_SIZE (0x10000) /*? */
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#define UL(x) _AC(x, UL)
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#define SUSPEND_FREQ (720000) /*720M */
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#define SUSPEND_DELAY_MS (10)
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#endif /*_PM_CONFIG_H*/
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