Initial commit
This commit is contained in:
Ole André Vadla Ravnås
commit
169c65d57e
51358 changed files with 23120455 additions and 0 deletions
364
arch/arm/mach-imx/mach-cpuimx51sd.c
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364
arch/arm/mach-imx/mach-cpuimx51sd.c
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/*
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*
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* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
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*
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* based on board-mx51_babbage.c which is
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* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/i2c/tsc2007.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/i2c-gpio.h>
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#include <linux/spi/spi.h>
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#include <linux/can/platform/mcp251x.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "common.h"
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#include "devices-imx51.h"
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#include "eukrea-baseboards.h"
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#include "hardware.h"
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#include "iomux-mx51.h"
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#define USBH1_RST IMX_GPIO_NR(2, 28)
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#define ETH_RST IMX_GPIO_NR(2, 31)
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#define TSC2007_IRQGPIO_REV2 IMX_GPIO_NR(3, 12)
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#define TSC2007_IRQGPIO_REV3 IMX_GPIO_NR(4, 0)
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#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
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#define CAN_RST IMX_GPIO_NR(4, 15)
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#define CAN_NCS IMX_GPIO_NR(4, 24)
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#define CAN_RXOBF_REV2 IMX_GPIO_NR(1, 4)
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#define CAN_RXOBF_REV3 IMX_GPIO_NR(3, 12)
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#define CAN_RX1BF IMX_GPIO_NR(1, 6)
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#define CAN_TXORTS IMX_GPIO_NR(1, 7)
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#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
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#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
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#define I2C_SCL IMX_GPIO_NR(4, 16)
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#define I2C_SDA IMX_GPIO_NR(4, 17)
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/* USB_CTRL_1 */
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#define MX51_USB_CTRL_1_OFFSET 0x10
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#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
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#define MX51_USB_PLLDIV_12_MHZ 0x00
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#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
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#define MX51_USB_PLL_DIV_24_MHZ 0x02
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static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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/* USB HOST1 */
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MX51_PAD_USBH1_CLK__USBH1_CLK,
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MX51_PAD_USBH1_DIR__USBH1_DIR,
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MX51_PAD_USBH1_NXT__USBH1_NXT,
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MX51_PAD_USBH1_DATA0__USBH1_DATA0,
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MX51_PAD_USBH1_DATA1__USBH1_DATA1,
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MX51_PAD_USBH1_DATA2__USBH1_DATA2,
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MX51_PAD_USBH1_DATA3__USBH1_DATA3,
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MX51_PAD_USBH1_DATA4__USBH1_DATA4,
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MX51_PAD_USBH1_DATA5__USBH1_DATA5,
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MX51_PAD_USBH1_DATA6__USBH1_DATA6,
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MX51_PAD_USBH1_DATA7__USBH1_DATA7,
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MX51_PAD_USBH1_STP__USBH1_STP,
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MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
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/* FEC */
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MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
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/* HSI2C */
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MX51_PAD_I2C1_CLK__GPIO4_16,
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MX51_PAD_I2C1_DAT__GPIO4_17,
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/* I2C1 */
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MX51_PAD_SD2_CMD__I2C1_SCL,
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MX51_PAD_SD2_CLK__I2C1_SDA,
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/* CAN */
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
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MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
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MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
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MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
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MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
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MX51_PAD_GPIO1_6__GPIO1_6,
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MX51_PAD_GPIO1_7__GPIO1_7,
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MX51_PAD_GPIO1_8__GPIO1_8,
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MX51_PAD_GPIO1_9__GPIO1_9,
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/* Touchscreen */
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/* IRQ */
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NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
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PAD_CTL_PKE | PAD_CTL_SRE_FAST |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
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NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
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PAD_CTL_PKE | PAD_CTL_SRE_FAST |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
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};
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static const struct imxuart_platform_data uart_pdata __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static int tsc2007_get_pendown_state(void)
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{
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if (mx51_revision() < IMX_CHIP_REVISION_3_0)
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return !gpio_get_value(TSC2007_IRQGPIO_REV2);
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else
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return !gpio_get_value(TSC2007_IRQGPIO_REV3);
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}
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static struct tsc2007_platform_data tsc2007_info = {
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.model = 2007,
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.x_plate_ohms = 180,
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.get_pendown_state = tsc2007_get_pendown_state,
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};
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static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
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{
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I2C_BOARD_INFO("pcf8563", 0x51),
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}, {
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I2C_BOARD_INFO("tsc2007", 0x49),
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.platform_data = &tsc2007_info,
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},
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};
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static const struct mxc_nand_platform_data
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eukrea_cpuimx51sd_nand_board_info __initconst = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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/* This function is board specific as the bit mask for the plldiv will also
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be different for other Freescale SoCs, thus a common bitmask is not
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possible and cannot get place in /plat-mxc/ehci.c.*/
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static int initialize_otg_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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void __iomem *usbother_base;
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usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
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if (!usb_base)
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return -ENOMEM;
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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/* Set the PHY clock to 19.2MHz */
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
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v |= MX51_USB_PLL_DIV_19_2_MHZ;
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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iounmap(usb_base);
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mdelay(10);
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return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
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}
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static int initialize_usbh1_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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void __iomem *usbother_base;
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usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
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if (!usb_base)
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return -ENOMEM;
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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/* The clock for the USBH1 ULPI port will come from the PHY. */
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v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
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__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
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usbother_base + MX51_USB_CTRL_1_OFFSET);
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iounmap(usb_base);
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mdelay(10);
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return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
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MXC_EHCI_ITC_NO_THRESHOLD);
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}
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static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
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.init = initialize_otg_port,
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.portsc = MXC_EHCI_UTMI_16BIT,
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};
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static const struct fsl_usb2_platform_data usb_pdata __initconst = {
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.operating_mode = FSL_USB2_DR_DEVICE,
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.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
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};
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static const struct mxc_usbh_platform_data usbh1_config __initconst = {
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.init = initialize_usbh1_port,
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.portsc = MXC_EHCI_MODE_ULPI,
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};
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static bool otg_mode_host __initdata;
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static int __init eukrea_cpuimx51sd_otg_mode(char *options)
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{
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if (!strcmp(options, "host"))
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otg_mode_host = true;
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else if (!strcmp(options, "device"))
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otg_mode_host = false;
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else
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pr_info("otg_mode neither \"host\" nor \"device\". "
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"Defaulting to device\n");
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return 1;
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}
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__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
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static struct i2c_gpio_platform_data pdata = {
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.sda_pin = I2C_SDA,
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.sda_is_open_drain = 0,
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.scl_pin = I2C_SCL,
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.scl_is_open_drain = 0,
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.udelay = 2,
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};
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static struct platform_device hsi2c_gpio_device = {
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.name = "i2c-gpio",
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.id = 0,
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.dev.platform_data = &pdata,
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};
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static struct mcp251x_platform_data mcp251x_info = {
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.oscillator_frequency = 24E6,
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};
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static struct spi_board_info cpuimx51sd_spi_device[] = {
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{
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.modalias = "mcp2515",
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.max_speed_hz = 10000000,
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.bus_num = 0,
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.mode = SPI_MODE_0,
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.chip_select = 0,
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.platform_data = &mcp251x_info,
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/* irq number is run-time assigned */
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},
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};
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static int cpuimx51sd_spi1_cs[] = {
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CAN_NCS,
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};
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static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
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.chipselect = cpuimx51sd_spi1_cs,
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.num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
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};
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static struct platform_device *rev2_platform_devices[] __initdata = {
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&hsi2c_gpio_device,
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};
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static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
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.bitrate = 100000,
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};
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static void __init eukrea_cpuimx51sd_init(void)
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{
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imx51_soc_init();
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mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
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ARRAY_SIZE(eukrea_cpuimx51sd_pads));
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imx51_add_imx_uart(0, &uart_pdata);
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imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
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imx51_add_imx2_wdt(0);
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gpio_request(ETH_RST, "eth_rst");
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gpio_set_value(ETH_RST, 1);
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imx51_add_fec(NULL);
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gpio_request(CAN_IRQGPIO, "can_irq");
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gpio_direction_input(CAN_IRQGPIO);
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gpio_free(CAN_IRQGPIO);
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gpio_request(CAN_NCS, "can_ncs");
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gpio_direction_output(CAN_NCS, 1);
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gpio_free(CAN_NCS);
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gpio_request(CAN_RST, "can_rst");
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gpio_direction_output(CAN_RST, 0);
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msleep(20);
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gpio_set_value(CAN_RST, 1);
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imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
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cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
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spi_register_board_info(cpuimx51sd_spi_device,
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ARRAY_SIZE(cpuimx51sd_spi_device));
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if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
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eukrea_cpuimx51sd_i2c_devices[1].irq =
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gpio_to_irq(TSC2007_IRQGPIO_REV2),
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platform_add_devices(rev2_platform_devices,
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ARRAY_SIZE(rev2_platform_devices));
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gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
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gpio_direction_input(TSC2007_IRQGPIO_REV2);
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gpio_free(TSC2007_IRQGPIO_REV2);
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} else {
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eukrea_cpuimx51sd_i2c_devices[1].irq =
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gpio_to_irq(TSC2007_IRQGPIO_REV3),
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imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
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gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
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gpio_direction_input(TSC2007_IRQGPIO_REV3);
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gpio_free(TSC2007_IRQGPIO_REV3);
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}
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i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
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ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
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if (otg_mode_host)
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imx51_add_mxc_ehci_otg(&dr_utmi_config);
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else {
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initialize_otg_port(NULL);
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imx51_add_fsl_usb2_udc(&usb_pdata);
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}
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gpio_request(USBH1_RST, "usb_rst");
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gpio_direction_output(USBH1_RST, 0);
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msleep(20);
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gpio_set_value(USBH1_RST, 1);
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imx51_add_mxc_ehci_hs(1, &usbh1_config);
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#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
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eukrea_mbimxsd51_baseboard_init();
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#endif
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}
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static void __init eukrea_cpuimx51sd_timer_init(void)
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{
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mx51_clocks_init(32768, 24000000, 22579200, 0);
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}
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MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
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/* Maintainer: Eric Bénard <eric@eukrea.com> */
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.atag_offset = 0x100,
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.map_io = mx51_map_io,
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.init_early = imx51_init_early,
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.init_irq = mx51_init_irq,
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.handle_irq = imx51_handle_irq,
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.init_time = eukrea_cpuimx51sd_timer_init,
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.init_machine = eukrea_cpuimx51sd_init,
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.init_late = imx51_init_late,
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.restart = mxc_restart,
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MACHINE_END
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