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Ole André Vadla Ravnås
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51358 changed files with 23120455 additions and 0 deletions
195
include/linux/iio/frequency/ad9523.h
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195
include/linux/iio/frequency/ad9523.h
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/*
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* AD9523 SPI Low Jitter Clock Generator
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#ifndef IIO_FREQUENCY_AD9523_H_
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#define IIO_FREQUENCY_AD9523_H_
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enum outp_drv_mode {
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TRISTATE,
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LVPECL_8mA,
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LVDS_4mA,
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LVDS_7mA,
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HSTL0_16mA,
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HSTL1_8mA,
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CMOS_CONF1,
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CMOS_CONF2,
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CMOS_CONF3,
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CMOS_CONF4,
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CMOS_CONF5,
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CMOS_CONF6,
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CMOS_CONF7,
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CMOS_CONF8,
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CMOS_CONF9
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};
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enum ref_sel_mode {
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NONEREVERTIVE_STAY_ON_REFB,
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REVERT_TO_REFA,
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SELECT_REFA,
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SELECT_REFB,
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EXT_REF_SEL
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};
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/**
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* struct ad9523_channel_spec - Output channel configuration
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*
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* @channel_num: Output channel number.
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* @divider_output_invert_en: Invert the polarity of the output clock.
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* @sync_ignore_en: Ignore chip-level SYNC signal.
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* @low_power_mode_en: Reduce power used in the differential output modes.
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* @use_alt_clock_src: Channel divider uses alternative clk source.
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* @output_dis: Disables, powers down the entire channel.
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* @driver_mode: Output driver mode (logic level family).
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* @divider_phase: Divider initial phase after a SYNC. Range 0..63
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LSB = 1/2 of a period of the divider input clock.
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* @channel_divider: 10-bit channel divider.
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* @extended_name: Optional descriptive channel name.
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*/
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struct ad9523_channel_spec {
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unsigned channel_num;
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bool divider_output_invert_en;
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bool sync_ignore_en;
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bool low_power_mode_en;
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/* CH0..CH3 VCXO, CH4..CH9 VCO2 */
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bool use_alt_clock_src;
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bool output_dis;
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enum outp_drv_mode driver_mode;
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unsigned char divider_phase;
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unsigned short channel_divider;
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char extended_name[16];
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};
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enum pll1_rzero_resistor {
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RZERO_883_OHM,
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RZERO_677_OHM,
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RZERO_341_OHM,
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RZERO_135_OHM,
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RZERO_10_OHM,
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RZERO_USE_EXT_RES = 8,
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};
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enum rpole2_resistor {
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RPOLE2_900_OHM,
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RPOLE2_450_OHM,
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RPOLE2_300_OHM,
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RPOLE2_225_OHM,
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};
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enum rzero_resistor {
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RZERO_3250_OHM,
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RZERO_2750_OHM,
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RZERO_2250_OHM,
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RZERO_2100_OHM,
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RZERO_3000_OHM,
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RZERO_2500_OHM,
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RZERO_2000_OHM,
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RZERO_1850_OHM,
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};
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enum cpole1_capacitor {
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CPOLE1_0_PF,
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CPOLE1_8_PF,
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CPOLE1_16_PF,
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CPOLE1_24_PF,
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_CPOLE1_24_PF, /* place holder */
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CPOLE1_32_PF,
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CPOLE1_40_PF,
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CPOLE1_48_PF,
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};
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/**
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* struct ad9523_platform_data - platform specific information
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*
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* @vcxo_freq: External VCXO frequency in Hz
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* @refa_diff_rcv_en: REFA differential/single-ended input selection.
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* @refb_diff_rcv_en: REFB differential/single-ended input selection.
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* @zd_in_diff_en: Zero Delay differential/single-ended input selection.
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* @osc_in_diff_en: OSC differential/ single-ended input selection.
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* @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable.
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* @refb_cmos_neg_inp_en: REFB single-ended neg./pos. input enable.
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* @zd_in_cmos_neg_inp_en: Zero Delay single-ended neg./pos. input enable.
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* @osc_in_cmos_neg_inp_en: OSC single-ended neg./pos. input enable.
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* @refa_r_div: PLL1 10-bit REFA R divider.
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* @refb_r_div: PLL1 10-bit REFB R divider.
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* @pll1_feedback_div: PLL1 10-bit Feedback N divider.
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* @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
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* @zero_delay_mode_internal_en: Internal, external Zero Delay mode selection.
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* @osc_in_feedback_en: PLL1 feedback path, local feedback from
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* the OSC_IN receiver or zero delay mode
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* @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
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* @ref_mode: Reference selection mode.
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* @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
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* @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
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* @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
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* @pll2_freq_doubler_en: PLL2 frequency doubler enable.
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* @pll2_r2_div: PLL2 R2 divider, range 0..31.
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* @pll2_vco_diff_m1: VCO1 divider, range 3..5.
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* @pll2_vco_diff_m2: VCO2 divider, range 3..5.
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* @rpole2: PLL2 loop filter Rpole resistor value.
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* @rzero: PLL2 loop filter Rzero resistor value.
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* @cpole1: PLL2 loop filter Cpole capacitor value.
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* @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
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* @num_channels: Array size of struct ad9523_channel_spec.
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* @channels: Pointer to channel array.
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* @name: Optional alternative iio device name.
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*/
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struct ad9523_platform_data {
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unsigned long vcxo_freq;
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/* Differential/ Single-Ended Input Configuration */
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bool refa_diff_rcv_en;
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bool refb_diff_rcv_en;
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bool zd_in_diff_en;
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bool osc_in_diff_en;
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/*
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* Valid if differential input disabled
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* if false defaults to pos input
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*/
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bool refa_cmos_neg_inp_en;
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bool refb_cmos_neg_inp_en;
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bool zd_in_cmos_neg_inp_en;
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bool osc_in_cmos_neg_inp_en;
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/* PLL1 Setting */
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unsigned short refa_r_div;
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unsigned short refb_r_div;
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unsigned short pll1_feedback_div;
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unsigned short pll1_charge_pump_current_nA;
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bool zero_delay_mode_internal_en;
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bool osc_in_feedback_en;
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enum pll1_rzero_resistor pll1_loop_filter_rzero;
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/* Reference */
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enum ref_sel_mode ref_mode;
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/* PLL2 Setting */
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unsigned int pll2_charge_pump_current_nA;
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unsigned char pll2_ndiv_a_cnt;
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unsigned char pll2_ndiv_b_cnt;
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bool pll2_freq_doubler_en;
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unsigned char pll2_r2_div;
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unsigned char pll2_vco_diff_m1; /* 3..5 */
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unsigned char pll2_vco_diff_m2; /* 3..5 */
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/* Loop Filter PLL2 */
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enum rpole2_resistor rpole2;
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enum rzero_resistor rzero;
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enum cpole1_capacitor cpole1;
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bool rzero_bypass_en;
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/* Output Channel Configuration */
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int num_channels;
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struct ad9523_channel_spec *channels;
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char name[SPI_NAME_SIZE];
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};
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#endif /* IIO_FREQUENCY_AD9523_H_ */
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128
include/linux/iio/frequency/adf4350.h
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128
include/linux/iio/frequency/adf4350.h
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/*
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* ADF4350/ADF4351 SPI PLL driver
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#ifndef IIO_PLL_ADF4350_H_
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#define IIO_PLL_ADF4350_H_
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/* Registers */
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#define ADF4350_REG0 0
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#define ADF4350_REG1 1
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#define ADF4350_REG2 2
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#define ADF4350_REG3 3
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#define ADF4350_REG4 4
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#define ADF4350_REG5 5
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/* REG0 Bit Definitions */
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#define ADF4350_REG0_FRACT(x) (((x) & 0xFFF) << 3)
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#define ADF4350_REG0_INT(x) (((x) & 0xFFFF) << 15)
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/* REG1 Bit Definitions */
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#define ADF4350_REG1_MOD(x) (((x) & 0xFFF) << 3)
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#define ADF4350_REG1_PHASE(x) (((x) & 0xFFF) << 15)
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#define ADF4350_REG1_PRESCALER (1 << 27)
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/* REG2 Bit Definitions */
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#define ADF4350_REG2_COUNTER_RESET_EN (1 << 3)
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#define ADF4350_REG2_CP_THREESTATE_EN (1 << 4)
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#define ADF4350_REG2_POWER_DOWN_EN (1 << 5)
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#define ADF4350_REG2_PD_POLARITY_POS (1 << 6)
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#define ADF4350_REG2_LDP_6ns (1 << 7)
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#define ADF4350_REG2_LDP_10ns (0 << 7)
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#define ADF4350_REG2_LDF_FRACT_N (0 << 8)
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#define ADF4350_REG2_LDF_INT_N (1 << 8)
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#define ADF4350_REG2_CHARGE_PUMP_CURR_uA(x) (((((x)-312) / 312) & 0xF) << 9)
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#define ADF4350_REG2_DOUBLE_BUFF_EN (1 << 13)
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#define ADF4350_REG2_10BIT_R_CNT(x) ((x) << 14)
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#define ADF4350_REG2_RDIV2_EN (1 << 24)
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#define ADF4350_REG2_RMULT2_EN (1 << 25)
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#define ADF4350_REG2_MUXOUT(x) ((x) << 26)
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#define ADF4350_REG2_NOISE_MODE(x) ((x) << 29)
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#define ADF4350_MUXOUT_THREESTATE 0
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#define ADF4350_MUXOUT_DVDD 1
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#define ADF4350_MUXOUT_GND 2
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#define ADF4350_MUXOUT_R_DIV_OUT 3
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#define ADF4350_MUXOUT_N_DIV_OUT 4
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#define ADF4350_MUXOUT_ANALOG_LOCK_DETECT 5
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#define ADF4350_MUXOUT_DIGITAL_LOCK_DETECT 6
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/* REG3 Bit Definitions */
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#define ADF4350_REG3_12BIT_CLKDIV(x) ((x) << 3)
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#define ADF4350_REG3_12BIT_CLKDIV_MODE(x) ((x) << 16)
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#define ADF4350_REG3_12BIT_CSR_EN (1 << 18)
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#define ADF4351_REG3_CHARGE_CANCELLATION_EN (1 << 21)
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#define ADF4351_REG3_ANTI_BACKLASH_3ns_EN (1 << 22)
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#define ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH (1 << 23)
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/* REG4 Bit Definitions */
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#define ADF4350_REG4_OUTPUT_PWR(x) ((x) << 3)
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#define ADF4350_REG4_RF_OUT_EN (1 << 5)
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#define ADF4350_REG4_AUX_OUTPUT_PWR(x) ((x) << 6)
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#define ADF4350_REG4_AUX_OUTPUT_EN (1 << 8)
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#define ADF4350_REG4_AUX_OUTPUT_FUND (1 << 9)
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#define ADF4350_REG4_AUX_OUTPUT_DIV (0 << 9)
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#define ADF4350_REG4_MUTE_TILL_LOCK_EN (1 << 10)
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#define ADF4350_REG4_VCO_PWRDOWN_EN (1 << 11)
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#define ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(x) ((x) << 12)
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#define ADF4350_REG4_RF_DIV_SEL(x) ((x) << 20)
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#define ADF4350_REG4_FEEDBACK_DIVIDED (0 << 23)
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#define ADF4350_REG4_FEEDBACK_FUND (1 << 23)
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/* REG5 Bit Definitions */
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#define ADF4350_REG5_LD_PIN_MODE_LOW (0 << 22)
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#define ADF4350_REG5_LD_PIN_MODE_DIGITAL (1 << 22)
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#define ADF4350_REG5_LD_PIN_MODE_HIGH (3 << 22)
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/* Specifications */
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#define ADF4350_MAX_OUT_FREQ 4400000000ULL /* Hz */
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#define ADF4350_MIN_OUT_FREQ 137500000 /* Hz */
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#define ADF4351_MIN_OUT_FREQ 34375000 /* Hz */
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#define ADF4350_MIN_VCO_FREQ 2200000000ULL /* Hz */
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#define ADF4350_MAX_FREQ_45_PRESC 3000000000ULL /* Hz */
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#define ADF4350_MAX_FREQ_PFD 32000000 /* Hz */
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#define ADF4350_MAX_BANDSEL_CLK 125000 /* Hz */
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#define ADF4350_MAX_FREQ_REFIN 250000000 /* Hz */
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#define ADF4350_MAX_MODULUS 4095
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#define ADF4350_MAX_R_CNT 1023
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/**
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* struct adf4350_platform_data - platform specific information
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* @name: Optional device name.
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* @clkin: REFin frequency in Hz.
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* @channel_spacing: Channel spacing in Hz (influences MODULUS).
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* @power_up_frequency: Optional, If set in Hz the PLL tunes to the desired
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* frequency on probe.
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* @ref_div_factor: Optional, if set the driver skips dynamic calculation
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* and uses this default value instead.
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* @ref_doubler_en: Enables reference doubler.
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* @ref_div2_en: Enables reference divider.
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* @r2_user_settings: User defined settings for ADF4350/1 REGISTER_2.
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* @r3_user_settings: User defined settings for ADF4350/1 REGISTER_3.
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* @r4_user_settings: User defined settings for ADF4350/1 REGISTER_4.
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* @gpio_lock_detect: Optional, if set with a valid GPIO number,
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* pll lock state is tested upon read.
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* If not used - set to -1.
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*/
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struct adf4350_platform_data {
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char name[32];
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unsigned long clkin;
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unsigned long channel_spacing;
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unsigned long long power_up_frequency;
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unsigned short ref_div_factor; /* 10-bit R counter */
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bool ref_doubler_en;
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bool ref_div2_en;
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unsigned r2_user_settings;
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unsigned r3_user_settings;
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unsigned r4_user_settings;
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int gpio_lock_detect;
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};
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#endif /* IIO_PLL_ADF4350_H_ */
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