/*
 * arch/arm64/include/asm/arch_timer.h
 *
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_ARCH_TIMER_H
#define __ASM_ARCH_TIMER_H

#include <asm/barrier.h>

#include <linux/init.h>
#include <linux/types.h>

#include <clocksource/arm_arch_timer.h>

/*
 * These register accessors are marked inline so the compiler can
 * nicely work out which register we want, and chuck away the rest of
 * the code.
 */
static __always_inline
void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
{
	if (access == ARCH_TIMER_PHYS_ACCESS) {
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			asm volatile("msr cntp_ctl_el0,  %0" : : "r" (val));
			break;
		case ARCH_TIMER_REG_TVAL:
			asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
			break;
		}
	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			asm volatile("msr cntv_ctl_el0,  %0" : : "r" (val));
			break;
		case ARCH_TIMER_REG_TVAL:
			asm volatile("msr cntv_tval_el0, %0" : : "r" (val));
			break;
		}
	}

	isb();
}

static __always_inline
u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
{
	u32 val;

	if (access == ARCH_TIMER_PHYS_ACCESS) {
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
			break;
		case ARCH_TIMER_REG_TVAL:
			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
			break;
		}
	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
			break;
		case ARCH_TIMER_REG_TVAL:
			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
			break;
		}
	}

	return val;
}

static __always_inline
u64 arch_timer_reg_read_cval(int access)
{
	u64 cval;

	if (access == ARCH_TIMER_PHYS_ACCESS)
		asm volatile("mrs %0, cntp_cval_el0" : "=r" (cval));
	else if (access == ARCH_TIMER_VIRT_ACCESS)
		asm volatile("mrs %0, cntv_cval_el0" : "=r" (cval));
	else
		cval = 0;

	return cval;
}

static inline u32 arch_timer_get_cntfrq(void)
{
	u32 val;
	asm volatile("mrs %0,   cntfrq_el0" : "=r" (val));
	return val;
}

static inline u32 arch_timer_get_cntkctl(void)
{
	u32 cntkctl;
	asm volatile("mrs	%0, cntkctl_el1" : "=r" (cntkctl));
	return cntkctl;
}

static inline void arch_timer_set_cntkctl(u32 cntkctl)
{
	asm volatile("msr	cntkctl_el1, %0" : : "r" (cntkctl));
}

static inline void __cpuinit arch_counter_set_user_access(void)
{
	u32 cntkctl = arch_timer_get_cntkctl();

	/* Disable user access to the timers and the physical counter */
	/* Also disable virtual event stream */
	cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
			| ARCH_TIMER_USR_VT_ACCESS_EN
			| ARCH_TIMER_VIRT_EVT_EN
			| ARCH_TIMER_USR_PCT_ACCESS_EN);

	/* Enable user access to the virtual counter */
	cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;

	arch_timer_set_cntkctl(cntkctl);
}

static inline void arch_timer_evtstrm_enable(int divider)
{
	u32 cntkctl = arch_timer_get_cntkctl();
	cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
	/* Set the divider and enable virtual event stream */
	cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
			| ARCH_TIMER_VIRT_EVT_EN;
	arch_timer_set_cntkctl(cntkctl);
	elf_hwcap |= HWCAP_EVTSTRM;
#ifdef CONFIG_COMPAT
	compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
#endif
}

#if defined(CONFIG_ARCH_SUN50IW1P1) \
	|| defined(CONFIG_ARCH_SUN50IW2P1)
#define ARCH_VCNT_TRY_MAX_TIME (12)
#define ARCH_VCNT_MAX_DELTA    (8)
static inline u64 arch_counter_get_cntvct(void)
{
	u64 vct0;
	u64 vct1;
	u64 delta;
	u32 retry = 0;

	/* sun50i vcnt maybe imprecise,
	 * we should try to fix this.
	 */
	while (retry < ARCH_VCNT_TRY_MAX_TIME) {
		isb();
		asm volatile("mrs %0, cntvct_el0" : "=r" (vct0));
		isb();
		asm volatile("mrs %0, cntvct_el0" : "=r" (vct1));
		delta = vct1 - vct0;
		if ((vct1 >= vct0) && (delta < ARCH_VCNT_MAX_DELTA)) {
			/* read valid vcnt */
			return vct1;
		}
		/* vcnt value error, try again */
		retry++;
	}
	/* Do not warry for this, just return the last time vcnt.
	 * arm64 have enabled CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE.
	 */
	return vct1;
}
#else
static inline u64 arch_counter_get_cntvct(void)
{
	u64 vct;

	isb();
	asm volatile("mrs %0, cntvct_el0" : "=r" (vct));

	return vct;
}
#endif /* CONFIG_ARCH_SUN50I */

#if defined(CONFIG_ARCH_SUN50IW1P1) \
	|| defined(CONFIG_ARCH_SUN50IW2P1)
#define ARCH_PCNT_TRY_MAX_TIME (12)
#define ARCH_PCNT_MAX_DELTA    (8)
static inline u64 arch_counter_get_cntpct(void)
{
	u64 pct0;
	u64 pct1;
	u64 delta;
	u32 retry = 0;

	/* sun50i vcnt maybe imprecise,
	 * we should try to fix this.
	 */
	while (retry < ARCH_PCNT_TRY_MAX_TIME) {
		isb();
		asm volatile("mrs %0, cntvct_el0" : "=r" (pct0));
		isb();
		asm volatile("mrs %0, cntvct_el0" : "=r" (pct1));
		delta = pct1 - pct0;
		if ((pct1 >= pct0) && (delta < ARCH_PCNT_MAX_DELTA)) {
			/* read valid vcnt */
			return pct1;
		}
		/* vcnt value error, try again */
		retry++;
	}
	/* Do not warry for this, just return the last time vcnt.
	 * arm64 have enabled CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE.
	 */
	return pct1;
}
#else
static inline u64 arch_counter_get_cntpct(void)
{
	u64 pct;

	isb();
	asm volatile("mrs %0, cntvct_el0" : "=r" (pct));

	return pct;
}
#endif /* CONFIG_ARCH_SUN50I */


static inline int arch_timer_arch_init(void)
{
	return 0;
}

#endif