/*
 * Allwinner sun8iw8p1 clk config info.
 * Modified by czy
 */

/{
clocks {
	compatible = "allwinner,sunxi-clk-init";
	device_type = "clocks";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	reg = <0x0 0x01c20000 0x0 0x324>,   /*cpux space*/
		<0x0 0x01c20460 0x0 0x4>;
/* register fixed rate clock*/
		clk_losc: losc {
			#clock-cells = <0>;
			compatible = "allwinner,fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "losc";
		};

		clk_hosc: hosc {
			#clock-cells = <0>;
			compatible = "allwinner,fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "hosc";
		};

/* register allwinner,sunxi-pll-clock */
		clk_pll_cpu: pll_cpu {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-pll-clock";
			lock-mode = "new";
			assigned-clock-rates = <528000000>;
			clock-output-names = "pll_cpu";
		};

		clk_pll_ddr0: pll_ddr0 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-pll-clock";
			lock-mode = "new";
			assigned-clock-rates = <312000000>;	/* 156MHZ */
			clock-output-names = "pll_ddr0";
		};

		clk_pll_ddr1: pll_ddr1 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-pll-clock";
			lock-mode = "new";
			clock-output-names = "pll_ddr1";
		};

		clk_pll_periph0: pll_periph0 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-pll-clock";
			lock-mode = "new";
			clock-output-names = "pll_periph0";
		};

		clk_pll_periph1: pll_periph1 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-pll-clock";
			lock-mode = "new";
			clock-output-names = "pll_periph1";
		};


/* register allwinner,sunxi-periph-clock */
		clk_cpu: cpu {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "cpu";
		};

		clk_axi: axi {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "axi";
		};

		clk_ahb0: ahb0 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "ahb0";
		};

		clk_apb0: apb0 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "apb0";
		};

		clk_ahb1: ahb1 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "ahb1";
		};
		clk_apb1: apb1 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "apb1";
		};

		clk_dma: dma {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "dma";
		};

		clk_uart0: uart0 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "uart0";
		};

		clk_uart1: uart1 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "uart1";
		};

		clk_pio: pio {
                         #clock-cells = <0>;
                         compatible = "allwinner,sunxi-periph-clock";
			 clock-output-names = "pio";
		};

		clk_hoscx2: hoscx2 {
			#clock-cells = <0>;
			compatible = "allwinner,fixed-factor-clock";
			clocks = <&clk_hosc>;
			clock-mult = <2>;
			clock-div = <1>;
			clock-output-names = "hoscx2";
		};

		clk_pll_periphahb0: pll_periphahb0 {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "pll_periphahb0";
		};

		clk_losc_out: losc_out {
			#clock-cells = <0>;
			compatible = "allwinner,sunxi-periph-clock";
			clock-output-names = "losc_out";
		};
	};
};