/*
 * ARM Ltd. Juno Plaform
 *
 * Fast Models FVP v2 support
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Juno";
	compatible = "arm,juno", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &soc_uart0;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "psci";
		};

		cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x102>;
			enable-method = "psci";
		};

		cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x103>;
			enable-method = "psci";
		};

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57","arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57","arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0x0 0x7f000000>,
		      <0x00000008 0x80000000 0x1 0x80000000>;
	};

	/* memory@14000000 {
		device_type = "memory";
		reg = <0x00000000 0x14000000 0x0 0x02000000>;
	}; */

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x0 0x2c010000 0 0x1000>,
		      <0x0 0x2c02f000 0 0x1000>,
		      <0x0 0x2c04f000 0 0x2000>,
		      <0x0 0x2c06f000 0 0x2000>;
		interrupts = <GIC_PPI 9 0xf04>;
	};

	msi0: msi@2c1c0000 {
		compatible = "arm,gic-msi";
		reg = <0x0 0x2c1c0000 0 0x10000
		       0x0 0x2c1d0000 0 0x10000
		       0x0 0x2c1e0000 0 0x10000
		       0x0 0x2c1f0000 0 0x10000>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 0xff01>,
			     <GIC_PPI 14 0xff01>,
			     <GIC_PPI 11 0xff01>,
			     <GIC_PPI 10 0xff01>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 60 4>,
			     <GIC_SPI 61 4>,
			     <GIC_SPI 62 4>,
			     <GIC_SPI 63 4>;
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_suspend = <0xC4000001>;
		cpu_off = <0x84000002>;
		cpu_on = <0xC4000003>;
		migrate = <0xC4000005>;
	};

	pci0: pci@30000000 {
		compatible = "arm,pcie-xr3";
		device_type = "pci";
		reg = <0 0x7ff30000 0 0x1000
		       0 0x7ff20000 0 0x10000
		       0 0x40000000 0 0x10000000>;
		bus-range = <0 255>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000
		          0x02000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000
			  0x42000000 0x0 0x80000000 0x40 0x80000000 0x0 0x80000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic 0 136 4
			         0 0 0 2 &gic 0 137 4
				 0 0 0 3 &gic 0 138 4
				 0 0 0 4 &gic 0 139 4>;
	};

	scpi: scpi@2b1f0000 {
		compatible = "arm,scpi-mhu";
		reg = <0x0 0x2b1f0000 0x0 0x10000>,   /* MHU registers */
		      <0x0 0x2e000000 0x0 0x10000>;   /* Payload area */
		interrupts = <0 36 4>,   /* low priority interrupt */
			     <0 35 4>,   /* high priority interrupt */
			     <0 37 4>;   /* secure channel interrupt */
		#clock-cells = <1>;
		clock-output-names = "a57", "a53", "gpu", "hdlcd0", "hdlcd1";
	};

	hdlcd0_osc: scpi_osc@3 {
		compatible = "arm,scpi-osc";
		#clock-cells = <0>;
		clocks = <&scpi 3>;
		frequency-range = <23000000 210000000>;
		clock-output-names = "pxlclk0";
	};

	hdlcd1_osc: scpi_osc@4 {
		compatible = "arm,scpi-osc";
		#clock-cells = <0>;
		clocks = <&scpi 4>;
		frequency-range = <23000000 210000000>;
		clock-output-names = "pxlclk1";
	};

	soc_uartclk: refclk72738khz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <7273800>;
		clock-output-names = "juno:uartclk";
	};

	soc_refclk24mhz: clk24mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "juno:clk24mhz";
	};

	mb_eth25mhz: clk25mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "ethclk25mhz";
	};

	soc_usb48mhz: clk48mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <48000000>;
		clock-output-names = "clk48mhz";
	};

	soc_smc50mhz: clk50mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
		clock-output-names = "smc_clk";
	};

	soc_refclk100mhz: refclk100mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "apb_pclk";
	};

	soc_faxiclk: refclk533mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <533000000>;
		clock-output-names = "faxi_clk";
	};

	soc_fixed_3v3: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0 0x7ffd0000 0 0x1000>;
		interrupts = <0 86 4>,
			     <0 87 4>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		chip5-memwidth = <16>;
	};

	dma0: dma@0x7ff00000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0x7ff00000 0 0x1000>;
		interrupts = <0 95 4>,
			     <0 88 4>,
			     <0 89 4>,
			     <0 90 4>,
			     <0 91 4>,
			     <0 108 4>,
			     <0 109 4>,
			     <0 110 4>,
			     <0 111 4>;
		#dma-cells = <1>;
		#dma-channels = <8>;
		#dma-requests = <32>;
		clocks = <&soc_faxiclk>;
		clock-names = "apb_pclk";
	};

	soc_uart0: uart@7ff80000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x0 0x7ff80000 0x0 0x1000>;
		interrupts = <0 83 4>;
		clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
		clock-names = "uartclk", "apb_pclk";
		dmas = <&dma0 1
			&dma0 2>;
		dma-names = "rx", "tx";
	};

	/* this UART is reserved for secure software.
	soc_uart1: uart@7ff70000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x0 0x7ff70000 0x0 0x1000>;
		interrupts = <0 84 4>;
		clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
		clock-names = "uartclk", "apb_pclk";
	}; */

	ulpi_phy: phy@0 {
		compatible = "phy-ulpi-generic";
		reg = <0x0 0x94 0x0 0x4>;
		phy-id = <0>;
	};

	ehci@7ffc0000 {
		compatible = "snps,ehci-h20ahb";
		/* compatible = "arm,h20ahb-ehci"; */
		reg = <0x0 0x7ffc0000 0x0 0x10000>;
		interrupts = <0 117 4>;
		clocks = <&soc_usb48mhz>;
		clock-names = "otg";
		phys = <&ulpi_phy>;
	};

	ohci@0x7ffb0000 {
		compatible = "generic-ohci";
		reg = <0x0 0x7ffb0000 0x0 0x10000>;
		interrupts = <0 116 4>;
		clocks = <&soc_usb48mhz>;
		clock-names = "otg";
	};

	i2c@0x7ffa0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,designware-i2c";
		reg = <0x0 0x7ffa0000 0x0 0x1000>;
		interrupts = <0 104 4>;
		clock-frequency = <400000>;
		i2c-sda-hold-time-ns = <500>;
		clocks = <&soc_smc50mhz>;

		dvi0: dvi-transmitter@70 {
			compatible = "nxp,tda998x";
			reg = <0x70>;
		};

		dvi1: dvi-transmitter@71 {
			compatible = "nxp,tda998x";
			reg = <0x71>;
		};
	};

	/* mmci@1c050000 {
		compatible = "arm,pl180", "arm,primecell";
		reg = <0x0 0x1c050000 0x0 0x1000>;
		interrupts = <0 73 4>,
			     <0 74 4>;
		max-frequency = <12000000>;
		vmmc-supply = <&soc_fixed_3v3>;
		clocks = <&soc_refclk24mhz>, <&soc_refclk100mhz>;
		clock-names = "mclk", "apb_pclk";
	}; */

	hdlcd@7ff60000 {
		compatible = "arm,hdlcd";
		reg = <0 0x7ff60000 0 0x1000>;
		interrupts = <0 85 4>;
		clocks = <&hdlcd0_osc>;
		clock-names = "pxlclk";
		i2c-slave = <&dvi0>;

		/* display-timings {
			native-mode = <&timing0>;
			timing0: timing@0 {
				/* 1024 x 768 framebufer, standard VGA timings * /
				clock-frequency = <65000>;
				hactive = <1024>;
				vactive = <768>;
				hfront-porch = <24>;
				hback-porch = <160>;
				hsync-len = <136>;
				vfront-porch = <3>;
				vback-porch = <29>;
				vsync-len = <6>;
			};
		}; */
	};

	hdlcd@7ff50000 {
		compatible = "arm,hdlcd";
		reg = <0 0x7ff50000 0 0x1000>;
		interrupts = <0 93 4>;
		clocks = <&hdlcd1_osc>;
		clock-names = "pxlclk";
		i2c-slave = <&dvi1>;

		display-timings {
			native-mode = <&timing1>;
			timing1: timing@1 {
				/* 1024 x 768 framebufer, standard VGA timings */
				clock-frequency = <65000>;
				hactive = <1024>;
				vactive = <768>;
				hfront-porch = <24>;
				hback-porch = <160>;
				hsync-len = <136>;
				vfront-porch = <3>;
				vback-porch = <29>;
				vsync-len = <6>;
			};
		};
	};

	smb {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 15>;
		interrupt-map = <0 0  0 &gic 0  68 4>,
				<0 0  1 &gic 0  69 4>,
				<0 0  2 &gic 0  70 4>,
				<0 0  3 &gic 0 160 4>,
				<0 0  4 &gic 0 161 4>,
				<0 0  5 &gic 0 162 4>,
				<0 0  6 &gic 0 163 4>,
				<0 0  7 &gic 0 164 4>,
				<0 0  8 &gic 0 165 4>,
				<0 0  9 &gic 0 166 4>,
				<0 0 10 &gic 0 167 4>,
				<0 0 11 &gic 0 168 4>,
				<0 0 12 &gic 0 169 4>;

		motherboard {
			model = "V2M-Juno";
			arm,hbi = <0x252>;
			arm,vexpress,site = <0>;
			arm,v2m-memory-map = "rs1";
			compatible = "arm,vexpress,v2p-p1", "simple-bus";
			#address-cells = <2>;  /* SMB chipselect number and offset */
			#size-cells = <1>;
			#interrupt-cells = <1>;
			ranges;

			usb@5,00000000 {
				compatible = "nxp,usb-isp1763";
				reg = <5 0x00000000 0x20000>;
				bus-width = <16>;
				interrupts = <4>;
			};

			ethernet@2,00000000 {
				compatible = "smsc,lan9118", "smsc,lan9115";
				reg = <2 0x00000000 0x10000>;
				interrupts = <3>;
				phy-mode = "mii";
				reg-io-width = <4>;
				smsc,irq-active-high;
				smsc,irq-push-pull;
				clocks = <&mb_eth25mhz>;
				vdd33a-supply = <&soc_fixed_3v3>; /* change this */
				vddvario-supply = <&soc_fixed_3v3>; /* and this */
			};

			iofpga@3,00000000 {
				compatible = "arm,amba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 3 0 0x200000>;

				kmi@060000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x060000 0x1000>;
					interrupts = <8>;
					clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				kmi@070000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x070000 0x1000>;
					interrupts = <8>;
					clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				wdt@0f0000 {
					compatible = "arm,sp805", "arm,primecell";
					reg = <0x0f0000 0x10000>;
					interrupts = <7>;
					clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
					clock-names = "wdogclk", "apb_pclk";
				};

				v2m_timer01: timer@110000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x110000 0x10000>;
					interrupts = <9>;
					clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
					clock-names = "timclken1", "apb_pclk";
				};

				v2m_timer23: timer@120000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x120000 0x10000>;
					interrupts = <9>;
					clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
					clock-names = "timclken1", "apb_pclk";
				};

				rtc@170000 {
					compatible = "arm,pl031", "arm,primecell";
					reg = <0x170000 0x10000>;
					interrupts = <0>;
					clocks = <&soc_smc50mhz>;
					clock-names = "apb_pclk";
				};
			};
		};
	};
};