/*
 * Allwinner Technology CO., Ltd. sun8iw10p1 platform
 *
 * fpga support
 * modify base on juno.dts & sun50iw1
 */
/* kernel used */
/memreserve/ 0x43000000 0x00000800; /* super standby range        : [0x43000000~0x43000800], size = 2K  */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun8iw10p1-clk.dtsi"
#include "sun8iw10p1-pinctrl.dtsi"
/ {
	model = "sun8iw10p1";
	compatible = "arm,sun8iw10p1", "arm,sun8iw10p1";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		twi0 = &twi0;
		twi1 = &twi1;
		twi2 = &twi2;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		global_timer0  = &soc_timer0;
		cci0 = &csi_cci0;
		csi_res0 = &csi_res0;
		vfe0 = &csi0;
		mmc0 = &sdc0;
		mmc2 = &sdc2;
		mmc3 = &sdc3;
		nand0 =&nand0;
		disp = &disp;
		lcd0 = &lcd0;
		pwm = &pwm;
		pwm0 = &pwm0;
		pwm1 = &pwm1;
		boot_disp = &boot_disp;
		charger0 = &charger0;
		regulator0 = &regulator0;
	};

	chosen {
		bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
		linux,initrd-start = <0x0 0x0>;
		linux,initrd-end = <0x0 0x0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			cpufreq_tbl = < 240000
					480000
					600000
					720000
					816000
					912000
					1008000>;
			clock-latency = <2000000>;
			clock-frequency = <1008000000>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			clock-frequency = <1008000000>;
		};
	};

	n_brom {
		compatible = "allwinner,n-brom";
		reg = <0x0 0x0 0x0 0xc000>;
	};

	s_brom {
		compatible = "allwinner,s-brom";
		reg = <0x0 0x0 0x0 0x10000>;
	};

	sram_ctrl {
		device_type = "sram_ctrl";
		compatible = "allwinner,sram_ctrl";
		reg = <0x0 0x01c00000 0x0 0x100>; /*sram base*/
	};

	sram_a1 {
		compatible = "allwinner,sram_a1";
		reg = <0x0 0x00000000 0x0 0x4000>;
	};

	sram_a2 {
		compatible = "allwinner,sram_a2";
		reg = <0x0 0x00040000 0x0 0x14000>;
	};

	prcm {
		compatible = "allwinner,prcm";
		reg = <0x0 0x01f01400 0x0 0x400>;
	};

	cpuscfg {
		compatible = "allwinner,cpuscfg";
		reg = <0x0 0x01f01c00 0x0 0x400>;
	};

	ion {
		compatible = "allwinner,sunxi-ion";
		/*types is list here:
			ION_HEAP_TYPE_SYSTEM = 0,
			ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
			ION_HEAP_TYPE_CARVEOUT = 2,
			ION_HEAP_TYPE_CHUNK = 3,
			ION_HEAP_TYPE_DMA = 4
		**/
		system_contig{
			type = <1>;
			name = "system_contig";
		};
		cma{
			type = <4>;
			name = "cma";
		};
		system{
			type = <0>;
			name = "system";
		};
	};

	dram: dram {
		compatible = "allwinner,dram";
		clocks = <&clk_pll_ddr0>, <&clk_pll_ddr1>;
		clock-names = "pll_ddr0", "pll_ddr1";
		dram_clk        = <672>;
		dram_type       = <3>;
		dram_zq         = <0x003F3FDD>;
		dram_odt_en     = <1>;
		dram_para1      = <0x10f41000>;
		dram_para2      = <0x00001200>;
		dram_mr0        = <0x1A50>;
		dram_mr1        = <0x40>;
		dram_mr2        = <0x10>;
		dram_mr3        = <0>;
		dram_tpr0       = <0x04E214EA>;
		dram_tpr1       = <0x004214AD>;
		dram_tpr2       = <0x10A75030>;
		dram_tpr3       = <0>;
		dram_tpr4       = <0>;
		dram_tpr5       = <0>;
		dram_tpr6       = <0>;
		dram_tpr7       = <0>;
		dram_tpr8       = <0>;
		dram_tpr9       = <0>;
		dram_tpr10      = <0>;
		dram_tpr11      = <0>;
		dram_tpr12      = <168>;
		dram_tpr13      = <0x823>;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0x00000000 0x40000000>;
	};

	gic: interrupt-controller@1c81000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		device_type = "gic";
		interrupt-controller;
		reg = <0x0 0x01c81000 0 0x1000>, /* GIC Dist */
		      <0x0 0x01c82000 0 0x2000>, /* GIC CPU */
			  <0x0 0x01c84000 0 0x2000>, /* GIC VCPU Control */
			  <0x0 0x01c86000 0 0x2000>; /* GIC VCPU */
		interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
	};

	chipid: sunxi-chipid@1c14000 {
		compatible = "allwinner,sunxi-chipid";
		device_type = "chipid";
		reg = <0x0 0x01c14000 0 0x0020>; /* chipid */
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 0xff01>, /* Secure Phys IRQ */
			     <GIC_PPI 14 0xff01>; /* Non-secure Phys IRQ */
		clock-frequency = <24000000>;
	};

	wdt: watchdog@01c20ca0 {
		 compatible = "allwinner,sun8i-wdt";
		 reg = <0x0 0x01c20ca0 0 0x18>;
	 };

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 120 4>,
			     <GIC_SPI 121 4>,
			     <GIC_SPI 122 4>,
			     <GIC_SPI 123 4>;
	};

	dvfs_table: dvfs_table {
		compatible = "allwinner,dvfs_table";
		max_freq = <1200000000>;
		min_freq = <480000000>;
		lv_count = <8>;
		lv1_freq = <1200000000>;
		lv1_volt = <1300>;
		lv2_freq = <1008000000>;
		lv2_volt = <1200>;
		lv3_freq = <816000000>;
		lv3_volt = <1100>;
		lv4_freq = <648000000>;
		lv4_volt = <1040>;
		lv5_freq = <0>;
		lv5_volt = <1040>;
		lv6_freq = <0>;
		lv6_volt = <1040>;
		lv7_freq = <0>;
		lv7_volt = <1040>;
		lv8_freq = <0>;
		lv8_volt = <1040>;
	};

	dramfreq {
		compatible = "allwinner,sunxi-dramfreq";
		reg = <0x0 0x01c62000 0x0 0x1000>,
				<0x0 0x01c63000 0x0 0x1000>,
				<0x0 0x01c20000 0x0 0x800>;
		interrupts = <GIC_SPI 69 0x4>;
		clocks = <&clk_pll_ddr0>,<&clk_pll_ddr1>,<&clk_ahb1>;
		status = "okay";
	};

	uboot: uboot {
	};
	soc: soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		device_type = "soc";
		dma0:dma-controller@01c02000 {
			compatible = "allwinner,sun50i-dma";
			reg = <0x0 0x01c02000 0x0 0x1000>;
			interrupts = <0 50 4>;
			clocks = <&clk_dma>;
			#dma-cells = <1>;
		};

		mbus0:mbus-controller@01c62000 {
			compatible = "allwinner,sun8i-mbus";
			reg = <0x0 0x01c62000 0x0 0x110>;
			#mbus-cells = <1>;
		};

		standby_space {
			compatible = "allwinner,standby_space";
			/* num    dst        offset     size						*/
			space1 = <0x43000000 0x00000000 0x00000800>; /* super standby para space        */
		};

		soc_timer0: timer@1c20c00 {
			compatible = "allwinner,sunxi-timer";
			device_type = "timer";
			reg = <0x0 0x01c20c00 0x0 0x90>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <24000000>;
			timer-prescale = <16>;
		};

		rtc: rtc@01c20400 {
			compatible = "allwinner,sun8iw10-rtc";
			device_type = "rtc";
			reg = <0x0 0x1c20400 0x0 0x218>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			gpr_offset = <0x100>;
			gpr_len	   = <4>;
		};

		uart0: uart@01c28000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart0";
			reg = <0x0 0x01c28000 0x0 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart0>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart0_pins_a>;
			pinctrl-1 = <&uart0_pins_b>;
			uart0_port = <0>;
			uart0_type = <2>;
			status = "disabled";
		};

		uart1: uart@01c28400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart1";
			reg = <0x0 0x01c28400 0x0 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart1_pins_a>;
			pinctrl-1 = <&uart1_pins_b>;
			uart1_port = <1>;
			uart1_type = <8>;
			status = "disabled";
		};

		uart2: uart@01c28800 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart2";
			reg = <0x0 0x01c28800 0x0 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart2>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart2_pins_a>;
			pinctrl-1 = <&uart2_pins_b>;
			uart2_port = <2>;
			uart2_type = <4>;
			status = "disabled";
		};

		uart3: uart@01c28c00 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart3";
			reg = <0x0 0x01c28c00 0x0 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart3>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart3_pins_a>;
			pinctrl-1 = <&uart3_pins_b>;
			uart3_port = <3>;
			uart3_type = <4>;
			status = "disabled";
		};

		uart4: uart@01c29000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart4";
			reg = <0x0 0x01c29000 0x0 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart4>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart4_pins_a>;
			pinctrl-1 = <&uart4_pins_b>;
			uart4_port = <4>;
			uart4_type = <4>;
			status = "disabled";
		};

		uart5: uart@01c29400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart5";
			reg = <0x0 0x01c29400 0x0 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart5>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart5_pins_a>;
			pinctrl-1 = <&uart5_pins_b>;
			uart5_port = <5>;
			uart5_type = <4>;
			status = "disabled";
		};

		twi0: twi@0x01c2ac00{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi0";
			reg = <0x0 0x01c2ac00 0x0 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi0>;
			clock-frequency = <400000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi0_pins_a>;
			pinctrl-1 = <&twi0_pins_b>;
			status = "disabled";

			pmu0: pmu@0{
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				status = "okay";

				powerkey0: powerkey@0{
					status = "okay";
				};

				regulator0: regulator@0{
					status = "okay";
				};

				axp_gpio0: axp_gpio@0{
					gpio-controller;
					#size-cells = <0>;
					#gpio-cells = <6>;
					status = "okay";
				};

				charger0: charger@0{
					status = "okay";
				};
			};

			pmu1: pmu@1{
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				status = "okay";

				powerkey1: powerkey@1{
					status = "okay";
				};

				charger1: charger@1{
					status = "okay";
				};

				axp_gpio1: axp_gpio@1{
					gpio-controller;
					#size-cells = <0>;
					#gpio-cells = <6>;
					status = "okay";
				};
			};
		};

		twi1: twi@0x01c2b000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi1";
			reg = <0x0 0x01c2b000 0x0 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi1>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi1_pins_a>;
			pinctrl-1 = <&twi1_pins_b>;
			status = "disabled";
		};

		twi2: twi@0x01c2b400{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi2";
			reg = <0x0 0x01c2b400 0x0 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi2>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi2_pins_a>;
			pinctrl-1 = <&twi2_pins_b>;
			status = "disabled";
		};

		spi0: spi@01c68000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi0";
			reg = <0x0 0x01c68000 0x0 0x1000>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0x2>, <&clk_spi0>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
			pinctrl-1 = <&spi0_pins_c>;
			spi0_cs_number = <1>;
			spi0_cs_bitmap = <1>;
			status = "disabled";
		};

		spi1: spi@01c69000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi1";
			reg = <0x0 0x01c69000 0x0 0x1000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0x2>, <&clk_spi1>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
			pinctrl-1 = <&spi1_pins_c>;
			spi1_cs_number = <1>;
			spi1_cs_bitmap = <1>;
			status = "disabled";
		};

		spi2: spi@01c6a000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi2";
			reg = <0x0 0x01c6a000 0x0 0x1000>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0x2>, <&clk_spi2>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_pins_a &spi2_pins_b>;
			pinctrl-1 = <&spi2_pins_c>;
			spi2_cs_number = <1>;
			spi2_cs_bitmap = <1>;
			status = "disabled";
		};

		usbc0:usbc0@0 {
			device_type         = "usbc0";
			compatible          = "allwinner,sunxi-otg-manager";
			usb_port_type       = <2>;
			usb_detect_type     = <1>;
			usb_detect_mode     = <0>;
			usb_id_gpio         = <&pio PB 16 0 1 1 1>;
			usb_det_vbus_gpio   = "axp_ctrl";
			usb_drv_vbus_gpio   = "axp_ctrl";
			usb_host_init_state = <0>;
			usb_regulator_io    = "nocare";
			usb_wakeup_suspend  = <0>;
			usb_luns            = <3>;
			usb_serial_unique   = <0>;
			usb_serial_number   = "20080411";
			rndis_wceis         = <1>;
			status              = "okay";
		};

		udc:udc-controller@0x01c19000 {
			compatible          = "allwinner,sunxi-udc";
			reg                 = <0x0 0x01c19000 0x0 0x1000>, /*udc base*/
			                      <0x0 0x01c00000 0x0 0x100>; /*sram base*/
			interrupts          = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy0>, <&clk_usbotg>;
			status              = "okay";
		};

		ehci0:ehci0-controller@0x01c1a000 {
			compatible          = "allwinner,sunxi-ehci0";
			reg                 = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/
			                      <0x0 0x01c00000 0x0 0x100>, /*sram base*/
			                      <0x0 0x01c19000 0x0 0x1000>; /*otg base*/
			interrupts          = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy0>, <&clk_usbehci0>;
			hci_ctrl_no         = <0>;
			status              = "okay";
		};

		ohci0:ohci0-controller@0x01c1a400 {
			compatible          = "allwinner,sunxi-ohci0";
			reg                 = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/
			                      <0x0 0x01c00000 0x0 0x100>, /*sram base*/
			                      <0x0 0x01c19000 0x0 0x1000>; /*otg base*/
			interrupts          = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci012m>, <&clk_hoscx2>, <&clk_hosc>, <&clk_losc>;
			hci_ctrl_no         = <0>;
			status              = "okay";
		};

		codec:codec@0x01c22c00 {
			compatible = "allwinner,sunxi-internal-codec";
			reg = <0x0 0x01c22c00 0x0 0x2bc>,/*digital baseadress*/
			      <0x0 0x01c23000 0x0 0x4>;/*analog baseadress*/
			clocks = <&clk_pll_audio>,<&clk_adda>;
			headphonevol =  <0x3b>;
			spkervol =  <0x1b>;
			maingain =  <0x4>;
			hp_dirused = <0x1>;
			pa_sleep_time = <0x15e>;
			status = "okay";
		};

		cpudai:cpudai0-controller@0x01c22c00 {
			compatible = "allwinner,sunxi-internal-cpudai";
			reg = <0x0 0x01c22c00 0x0 0x2bc>;/*digital baseadress*/
			status = "okay";
		};

		daudio0:daudio@0x01c22000 {
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x01c22000 0x0 0x70>;
			clocks = <&clk_pll_audio>,<&clk_i2s0>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&daudio0_pins_a>;
			pinctrl-1 = <&daudio0_pins_b>;
			pcm_lrck_period =  <0x20>;
			pcm_lrckr_period =  <0x01>;
			slot_width_select =  <0x20>;
			pcm_lsb_first =  <0x0>;
			tx_data_mode =  <0x0>;
			rx_data_mode =  <0x0>;
			daudio_master =  <0x04>;
			audio_format =  <0x01>;
			signal_inversion =  <0x01>;
			frametype =  <0x0>;
			tdm_config =  <0x01>;
			mclk_div = <0x0>;
			tdm_num = <0x0>;
			status = "okay";
		};
		daudio1:daudio@0x01c22400 {
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x01c22400 0x0 0x70>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&daudio1_pins_a>;
			pinctrl-1 = <&daudio1_pins_b>;
			clocks = <&clk_pll_audio>,<&clk_i2s1>;
			pcm_lrck_period =  <0x20>;
			pcm_lrckr_period =  <0x01>;
			slot_width_select =  <0x20>;
			pcm_lsb_first =  <0x0>;
			tx_data_mode =  <0x0>;
			rx_data_mode =  <0x0>;
			daudio_master =  <0x04>;
			audio_format =  <0x01>;
			signal_inversion =  <0x01>;
			frametype =  <0x0>;
			tdm_config =  <0x01>;
			tdm_num = <0x1>;
			mclk_div = <0x0>;
			status = "okay";
		};
		spdif:spdif-controller@0x01c21000{
			compatible = "allwinner,sunxi-spdif";
			reg = <0x0 0x01c21000 0x0 0x38>;
			clocks = <&clk_pll_audio>,<&clk_spdif>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&spdif_pins_a>;
			pinctrl-1 = <&spdif_pins_b>;
			status = "okay";
		};
		dsd:dsd-controller@0x01c23400{
			compatible = "allwinner,sunxi-dsd";
			reg = <0x0 0x01c23400 0x0 0x2c>;
			clocks = <&clk_pll_audio>,<&clk_dsd>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&dsd_pins_a>;
			pinctrl-1 = <&dsd_pins_b>;
			mode_select =  <0x0>;
			status = "okay";
		};

		dmic:dmic-controller@0x01c23800{
			compatible = "allwinner,sunxi-dmic";
			reg = <0x0 0x01c23800 0x0 0x34>;
			clocks = <&clk_pll_audio>,<&clk_dmic>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&dmic_pins_a>;
			pinctrl-1 = <&dmic_pins_b>;
			status = "okay";
		};
		sndcodec:sound@0 {
			compatible = "allwinner,sunxi-codec-machine";
			interrupts = <GIC_SPI 28 4>;
			sunxi,cpudai-controller = <&cpudai>;
			sunxi,audio-codec = <&codec>;
			hp_detect_case = <0x00>;
			status = "okay";
		};

		snddaudio0:sound@1{
			compatible = "allwinner,sunxi-daudio0-machine";
			sunxi,daudio0-controller = <&daudio0>;
                        sunxi,snddaudio-codec = "cx2081x.1-003b";
                        sunxi,snddaudio-codec-dai = "cx2081x-pcm1";
			status = "okay";
		};
		snddaudio1:sound@2{
			compatible = "allwinner,sunxi-daudio1-machine";
			sunxi,daudio1-controller = <&daudio1>;
                        sunxi,snddaudio-codec = "sta32x.1-001c";
                        sunxi,snddaudio-codec-dai = "STA32X";
			status = "okay";
		};

		sndspdif:sound@3{
			compatible = "allwinner,sunxi-spdif-machine";
			sunxi,spdif-controller = <&spdif>;
			status = "okay";
		};
		snddsd:sound@4{
			compatible = "allwinner,sunxi-dsd-machine";
			sunxi,dsd-controller = <&dsd>;
			status = "okay";
		};
		snddmic:sound@5{
			compatible = "allwinner,sunxi-dmic-machine";
			sunxi,dmic-controller = <&dmic>;
			status = "okay";
		};

		sdc3: sdmmc@01C12000 {
			compatible = "allwinner,sunxi-mmc-v4p5x";
			device_type = "sdc3";
			reg = <0x0 0x01C12000 0x0 0x1000>;
			interrupts = <GIC_SPI 63 0x0104>;  /*  */
			clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc3_mod>,<&clk_sdmmc3_bus>,<&clk_sdmmc3_rst>;
                        clock-names = "osc24m","pll_periph","mmc","ahb","rst";
                        pinctrl-names = "default","sleep";
                        pinctrl-0 = <&sdc3_pins_a>;
                        pinctrl-1 = <&sdc3_pins_b>;
                        bus-width = <8>;
                        /*mmc-ddr-1_8v;*/
                        /*mmc-hs200-1_8v;*/
                        /*mmc-hs400-1_8v;*/
                        /*non-removable;*/
                        /*max-frequency = <200000000>;*/
                        max-frequency = <50000000>;

                        /*-- speed mode --*/
                        /*sm0: DS26_SDR12*/
                        /*sm1: HSSDR52_SDR25*/
                        /*sm2: HSDDR52_DDR50*/
                        /*sm3: HS200_SDR104*/
                        /*sm4: HS400*/
                        /*-- frequency point --
			/*f0: CLK_400K*/
			/*f1: CLK_25M*/
			/*f2: CLK_50M*/
			/*f3: CLK_100M*/
			/*f4: CLK_150M*/
			/*f5: CLK_200M*/
                        sdc_tm4_sm0_freq0 = <0>;
                        sdc_tm4_sm0_freq1 = <0>;
                        sdc_tm4_sm1_freq0 = <0x00000000>;
                        sdc_tm4_sm1_freq1 = <0>;
                        sdc_tm4_sm2_freq0 = <0x00000000>;
                        sdc_tm4_sm2_freq1 = <0>;
                        sdc_tm4_sm3_freq0 = <0x05000000>;
                        sdc_tm4_sm3_freq1 = <0x00000005>;
                        sdc_tm4_sm4_freq0 = <0x00050000>;
                        sdc_tm4_sm4_freq1 = <0x00000004>;

			/*vmmc-supply = <&reg_3p3v>;*/
			/*vqmc-supply = <&reg_3p3v>;*/
			/*vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
                        /*sunxi-power-save-mode;*/
			status = "disabled";
			/*status = "okay";*/
		};

		sdc2: sdmmc@01C11000 {
			compatible = "allwinner,sunxi-mmc-v5px";
			device_type = "sdc2";
			reg = <0x0 0x01C11000 0x0 0x1000>;
			interrupts = <GIC_SPI 62 0x0104>;  /*  */
			clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc2_mod>,<&clk_sdmmc2_bus>,<&clk_sdmmc2_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc2_pins_a>;
			pinctrl-1 = <&sdc2_pins_b>;
			bus-width = <8>;
			/*mmc-ddr-1_8v;*/
			/*mmc-hs200-1_8v;*/
			/*mmc-hs400-1_8v;*/
			/*non-removable;*/
			/*max-frequency = <200000000>;*/
			max-frequency = <50000000>;

			/*-- speed mode --*/
			/*sm0: DS26_SDR12*/
			/*sm1: HSSDR52_SDR25*/
			/*sm2: HSDDR52_DDR50*/
			/*sm3: HS200_SDR104*/
			/*sm4: HS400*/
			/*-- frequency point --
			/*f0: CLK_400K*/
			/*f1: CLK_25M*/
			/*f2: CLK_50M*/
			/*f3: CLK_100M*/
			/*f4: CLK_150M*/
			/*f5: CLK_200M*/

			sdc_tm4_sm0_freq0 = <0>;
			sdc_tm4_sm0_freq1 = <0>;
			sdc_tm4_sm1_freq0 = <0x00000000>;
			sdc_tm4_sm1_freq1 = <0>;
			sdc_tm4_sm2_freq0 = <0x00000000>;
			sdc_tm4_sm2_freq1 = <0>;
			sdc_tm4_sm3_freq0 = <0x05000000>;
			sdc_tm4_sm3_freq1 = <0x00000005>;
			sdc_tm4_sm4_freq0 = <0x00050000>;
			sdc_tm4_sm4_freq1 = <0x00000004>;

			/*vmmc-supply = <&reg_3p3v>;*/
			/*vqmc-supply = <&reg_3p3v>;*/
			/*vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sunxi-power-save-mode;*/
			status = "disabled";
			/*status = "okay";*/

		};

		sdc0: sdmmc@01c0f000 {
			compatible = "allwinner,sunxi-mmc-v4p1x";
			device_type = "sdc0";
			reg = <0x0 0x01c0f000 0x0 0x1000>; /* only sdmmc0 */
			interrupts = <GIC_SPI 60 0x0104>;  /*  */
			clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc0_mod>,<&clk_sdmmc0_bus>,<&clk_sdmmc0_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc0_pins_a>;
			pinctrl-1 = <&sdc0_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*non-removable;*/
			/*cd-inverted*/
			cd-gpios = <&pio PF 6 0 1 2 0>;
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr4  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr8  = <1 0 0 0>;*/
			/*sunxi-dly-104M  = <1 0 0 0>;*/
			/*sunxi-dly-208M  = <1 0 0 0>;*/
			/*sunxi-dly-104M-ddr  = <1 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0>;*/

			status = "okay";
			/*status = "disabled";*/
		};


		sdc1: sdmmc@1C10000 {
			compatible = "allwinner,sunxi-mmc-v4p1x";
			device_type = "sdc1";
			reg = <0x0 0x1C10000 0x0 0x1000>;
			interrupts = <GIC_SPI 61 0x0104>;  /*  */
			clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc1_mod>,<&clk_sdmmc1_bus>,<&clk_sdmmc1_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			sunxi-dly-52M-ddr4  = <1 0 0 0 2>;
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			sunxi-dly-104M  = <1 0 0 0 1>;
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			sunxi-dly-208M  = <1 0 0 0 1>;
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/

			/*status = "okay";*/
			status = "disabled";
		};


		disp: disp@01000000 {
			compatible = "allwinner,sun8iw10p1-disp";
			reg = <0x0 0x01000000 0x0 0x00300000>,/*de*/
				<0x0 0x01c0c000 0x0 0x17fc>,/*lcd*/
				<0x0 0x01400000 0x0 0x420>;/*eink*/
			interrupts = <GIC_SPI 86 0x0104>, <GIC_SPI 95 0x0104>,
				<GIC_SPI 106 0x0104>;/* for ee */
			clocks = <&clk_de>,<&clk_tcon0>,<&clk_ee>,<&clk_edma>;
			boot_disp = <0>;
			fb_base = <0>;

			status = "okay";
		};

		lcd0: lcd0@01c0c000 {
			compatible = "allwinner,sunxi-lcd0";
			pinctrl-names = "active","sleep";

			status = "okay";
		};

		pwm: pwm@01c21400 {
			compatible = "allwinner,sunxi-pwm";
			reg = <0x0 0x01c21400 0x0 0x154>;
			pwm-number = <1>;
			pwm-base = <0x0>;
			pwms = <&pwm0>, <&pwm1>;
		};

		pwm0: pwm0@01c21400 {
			compatible = "allwinner,sunxi-pwm0";
			pinctrl-names = "active", "sleep";
			reg_base = <0x01c21400>;
			reg_peci_offset = <0x00>;
			reg_peci_shift = <0x00>;
			reg_peci_width = <0x01>;

			reg_pis_offset = <0x04>;
			reg_pis_shift = <0x00>;
			reg_pis_width = <0x01>;

			reg_crie_offset = <0x10>;
			reg_crie_shift = <0x00>;
			reg_crie_width = <0x01>;

			reg_cfie_offset = <0x10>;
			reg_cfie_shift = <0x01>;
			reg_cfie_width = <0x01>;

			reg_cris_offset = <0x14>;
			reg_cris_shift = <0x00>;
			reg_cris_width = <0x01>;

			reg_cfis_offset = <0x14>;
			reg_cfis_shift = <0x01>;
			reg_cfis_width = <0x01>;

			reg_clk_src_offset = <0x20>;
			reg_clk_src_shift = <0x07>;
			reg_clk_src_width = <0x02>;

			reg_bypass_offset = <0x20>;
			reg_bypass_shift = <0x05>;
			reg_bypass_width = <0x01>;

			reg_clk_gating_offset = <0x20>;
			reg_clk_gating_shift = <0x04>;
			reg_clk_gating_width = <0x01>;

			reg_clk_div_m_offset = <0x20>;
			reg_clk_div_m_shift = <0x00>;
			reg_clk_div_m_width = <0x04>;

			reg_pdzintv_offset = <0x30>;
			reg_pdzintv_shift = <0x08>;
			reg_pdzintv_width = <0x08>;

			reg_dz_en_offset = <0x30>;
			reg_dz_en_shift = <0x00>;
			reg_dz_en_width = <0x01>;

			reg_enable_offset = <0x40>;
			reg_enable_shift = <0x00>;
			reg_enable_width = <0x01>;

			reg_cap_en_offset = <0x44>;
			reg_cap_en_shift = <0x00>;
			reg_cap_en_width = <0x01>;

			reg_period_rdy_offset = <0x60>;
			reg_period_rdy_shift = <0x0b>;
			reg_period_rdy_width = <0x01>;

			reg_pul_start_offset = <0x60>;
			reg_pul_start_shift = <0x0a>;
			reg_pul_start_width = <0x01>;

			reg_mode_offset = <0x60>;
			reg_mode_shift = <0x09>;
			reg_mode_width = <0x01>;

			reg_act_sta_offset = <0x60>;
			reg_act_sta_shift = <0x08>;
			reg_act_sta_width = <0x01>;

			reg_prescal_offset = <0x60>;
			reg_prescal_shift = <0x00>;
			reg_prescal_width = <0x08>;

			reg_entire_offset = <0x64>;
			reg_entire_shift = <0x10>;
			reg_entire_width = <0x10>;

			reg_active_offset = <0x64>;
			reg_active_shift = <0x00>;
			reg_active_width = <0x10>;
			dead_time = <20000>;
		};

		pwm1: pwm1@01c21400 {
			compatible = "allwinner,sunxi-pwm1";
			pinctrl-names = "active", "sleep";
			reg_base = <0x01c21400>;
			reg_peci_offset = <0x00>;
			reg_peci_shift = <0x01>;
			reg_peci_width = <0x01>;

			reg_pis_offset = <0x04>;
			reg_pis_shift = <0x01>;
			reg_pis_width = <0x01>;

			reg_crie_offset = <0x10>;
			reg_crie_shift = <0x00>;
			reg_crie_width = <0x01>;

			reg_cfie_offset = <0x10>;
			reg_cfie_shift = <0x01>;
			reg_cfie_width = <0x01>;

			reg_cris_offset = <0x14>;
			reg_cris_shift = <0x01>;
			reg_cris_width = <0x01>;

			reg_cfis_offset = <0x14>;
			reg_cfis_shift = <0x01>;
			reg_cfis_width = <0x01>;

			reg_clk_src_offset = <0x20>;
			reg_clk_src_shift = <0x07>;
			reg_clk_src_width = <0x02>;

			reg_bypass_offset = <0x20>;
			reg_bypass_shift = <0x06>;
			reg_bypass_width = <0x01>;

			reg_clk_gating_offset = <0x20>;
			reg_clk_gating_shift = <0x04>;
			reg_clk_gating_width = <0x01>;

			reg_clk_div_m_offset = <0x20>;
			reg_clk_div_m_shift = <0x00>;
			reg_clk_div_m_width = <0x04>;

			reg_pdzintv_offset = <0x30>;
			reg_pdzintv_shift = <0x08>;
			reg_pdzintv_width = <0x08>;

			reg_dz_en_offset = <0x30>;
			reg_dz_en_shift = <0x00>;
			reg_dz_en_width = <0x01>;

			reg_enable_offset = <0x40>;
			reg_enable_shift = <0x01>;
			reg_enable_width = <0x01>;

			reg_cap_en_offset = <0x44>;
			reg_cap_en_shift = <0x01>;
			reg_cap_en_width = <0x01>;

			reg_period_rdy_offset = <0x80>;
			reg_period_rdy_shift = <0x0b>;
			reg_period_rdy_width = <0x01>;

			reg_pul_start_offset = <0x80>;
			reg_pul_start_shift = <0x0a>;
			reg_pul_start_width = <0x01>;

			reg_mode_offset = <0x80>;
			reg_mode_shift = <0x09>;
			reg_mode_width = <0x01>;

			reg_act_sta_offset = <0x80>;
			reg_act_sta_shift = <0x08>;
			reg_act_sta_width = <0x01>;

			reg_prescal_offset = <0x80>;
			reg_prescal_shift = <0x00>;
			reg_prescal_width = <0x08>;

			reg_entire_offset = <0x84>;
			reg_entire_shift = <0x10>;
			reg_entire_width = <0x10>;

			reg_active_offset = <0x84>;
			reg_active_shift = <0x00>;
			reg_active_width = <0x10>;
			dead_time = <20000>;
		};

		soc_tr: tr@01000000 {
			compatible = "allwinner,sun50i-tr";
			reg = <0x0 0x01000000 0x0 0x000200bc>;
			interrupts = <GIC_SPI 96 0x0104>;
			clocks = <&clk_de>;
			status = "okay";
		};

		boot_disp: boot_disp {
			compatible = "allwinner,boot_disp";
		};

		csi_cci0:cci@0x01cb3000 {
			compatible = "allwinner,sunxi-csi_cci";
			reg = <0x0 0x01cb3000 0x0 0x1000>;	/*0x01cb3000--0x01cb4000*/
			interrupts = <GIC_SPI 85 4>;/*SUNXI_IRQ_CSI0_CCI (SUNXI_GIC_START + 85) = 117*/
			status = "okay";
		};
		csi_res0:csi_res@0x01cb0000 {
			compatible = "allwinner,sunxi-csi";
			reg = <0x0 0x01cb0000 0x0 0x1000>;/*0x01cb0000--0x01cb1000*/
			clocks		= <&clk_csi_s>, <&clk_csi_m>,<&clk_csi_misc>,
					<&clk_pll_periph0>,<&clk_pll_periph0>,<&clk_pll_periph0>;
			clocks-index	= <0 1 2 3 4 5>;
			status = "okay";
		};
		csi0:vfe@0 {
			device_type= "csi0";
			compatible = "allwinner,sunxi-vfe";
			interrupts = <GIC_SPI 84 4>;/*SUNXI_IRQ_CSI0 (SUNXI_GIC_START + 84 ) = 116*/
			pinctrl-names 		= "default","sleep";
			pinctrl-0		= <&csi0_pins_a>;
			pinctrl-1		= <&csi0_pins_b>;
			cci_sel			= <0>;
			csi_sel			= <0>;
			mipi_sel		= <0>;
			isp_sel			= <0>;
			csi0_sensor_list	= <0>;
			csi0_mck		= <&pio PD 9 1 0 1 0>; /*PD9 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
			status = "okay";
			csi0_dev0:dev@0{
				csi0_dev0_mname         = "ov5640";
				csi0_dev0_twi_addr      = <0x78>;
				csi0_dev0_pos		= "rear";
				csi0_dev0_isp_used      = <0>;
				csi0_dev0_fmt           = <0>;
				csi0_dev0_stby_mode     = <0>;
				csi0_dev0_vflip         = <0>;
				csi0_dev0_hflip         = <0>;
				csi0_dev0_iovdd         = "iovdd-csi";
				csi0_dev0_iovdd_vol     = <2800000>;
				csi0_dev0_avdd          = "avdd-csi";
				csi0_dev0_avdd_vol      = <2800000>;
				csi0_dev0_dvdd          = "dvdd-csi-18";
				csi0_dev0_dvdd_vol      = <1500000>;
				csi0_dev0_afvdd         = "afvcc-csi";
				csi0_dev0_afvdd_vol     = <2800000>;
				csi0_dev0_power_en	= <>;
				csi0_dev0_reset		= <&pio PB 03 1 0 1 0>; /*PB03 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
				csi0_dev0_pwdn		= <&pio PB 10 1 0 1 0>; /*PB10 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
				csi0_dev0_flash_en	= <>;
				csi0_dev0_flash_mode	= <>;
				csi0_dev0_af_pwdn	= <>;
				csi0_dev0_act_used      = <0>;
				csi0_dev0_act_name      = "ad5820_act";
				csi0_dev0_act_slave	= <0x18>;
				status = "okay";
			};
			csi0_dev1:dev@1{
				csi0_dev1_mname         = "";
				csi0_dev1_twi_addr      = <0x78>;
				csi0_dev1_pos		= "rear";
				csi0_dev1_isp_used      = <1>;
				csi0_dev1_fmt           = <0>;
				csi0_dev1_stby_mode     = <0>;
				csi0_dev1_vflip         = <0>;
				csi0_dev1_hflip         = <0>;
				csi0_dev1_iovdd         = "iovdd-csi";
				csi0_dev1_iovdd_vol     = <2800000>;
				csi0_dev1_avdd          = "avdd-csi";
				csi0_dev1_avdd_vol      = <2800000>;
				csi0_dev1_dvdd          = "dvdd-csi-18";
				csi0_dev1_dvdd_vol      = <1500000>;
				csi0_dev1_afvdd         = "afvcc-csi";
				csi0_dev1_afvdd_vol     = <2800000>;
				csi0_dev1_power_en	= <>;
				csi0_dev1_reset		= <>;
				csi0_dev1_pwdn		= <>;
				csi0_dev1_flash_en	= <>;
				csi0_dev1_flash_mode	= <>;
				csi0_dev1_af_pwdn	= <>;
				csi0_dev1_act_used      = <0>;
				csi0_dev1_act_name      = "ad5820_act";
				csi0_dev1_act_slave	= <0x18>;
				status = "disabled";
			};
		};
		Vdevice: vdevice@0{
			compatible = "allwinner,sun8i-vdevice";
			device_type = "Vdevice";
			pinctrl-names = "default";
			pinctrl-0 = <&vdevice_pins_a>;
			test-gpios = <&pio PB 2 1 2 2 1>;
			status = "okay";
		};
		nmi:nmi@0{
			compatible = "allwinner,sunxi-nmi";
			reg = <0x0 0x01c00000 0x0 0x100>;
			nmi_irq_ctrl = <0xd0>;
			nmi_irq_en = <0xd4>;
			nmi_irq_status = <0xd8>;
			status = "okay";
		};

		nand0:nand0@01c03000 {
			compatible = "allwinner,sun8iw10-nand";
			device_type = "nand0";
			reg = <0x0 0x01c03000 0x0 0x1000>; /* nand0 */
			interrupts = <GIC_SPI 70 0x04>;
			clocks = <&clk_pll_periph0x2>,<&clk_nand>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
			pinctrl-1 = <&nand0_pins_c>;
			nand0_regulator1 = "vcc-nand";
			nand0_regulator2 = "none";
			nand0_cache_level = <0x55aaaa55>;
			nand0_flush_cache_num = <0x55aaaa55>;
			nand0_capacity_level = <0x55aaaa55>;
			nand0_id_number_ctl = <0x55aaaa55>;
			nand0_print_level = <0x55aaaa55>;
			nand0_p0 = <0x55aaaa55>;
			nand0_p1 = <0x55aaaa55>;
			nand0_p2 = <0x55aaaa55>;
			nand0_p3 = <0x55aaaa55>;
			status = "okay";
		};

		sunxi_thermal_sensor:thermal_sensor{
			compatible = "allwinner,thermal_sensor";
			reg = <0x0 0x01c25000 0x0 0x400>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_NONE>;
			clocks = <&clk_hosc>,<&clk_ths>;
			sensor_num = <2>;
			shut_temp= <120>;
			status = "okay";

			combine0:combine0{
				#thermal-sensor-cells = <1>;
				combine_cnt = <2>;
				combine_type = "max";
				combine_chn = <0 1>;
			};
		};

		cpu_budget_cooling:cpu_budget_cool{
			compatible = "allwinner,budget_cooling";
			#cooling-cells = <2>;
			status = "okay";
			state_cnt = <2>;
			cluster_num = <1>;
			state0 = <1008000 2>;
			state1 = <1008000 1>;
		};

		thermal-zones{
			soc_thermal{

				polling-delay-passive = <1000>;
				polling-delay = <10000>;
				thermal-sensors = <&combine0 0>;

				trips{
					cpu_trip0:t0{
						temperature = <100>;
						type = "passive";
						hysteresis = <0>;
					};
					crt_trip:t1{
						temperature = <115>;
						type = "critical";
						hysteresis = <0>;
					};
				};

				cooling-maps{
					bind0{
						contribution = <0>;
						trip = <&cpu_trip0>;
						cooling-device = <&cpu_budget_cooling 1 1>;
					};
				};
			};
		};

		gpadc:gpadc{
			compatible = "allwinner,sunxi-gpadc";
			reg = <0x0 0x01c25400 0x0 0x400>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
			clocks = <&clk_gpadc>;
			status = "okay";
		};

		keyboard0:keyboard{
			compatible = "allwinner,keyboard_2000mv";
			reg = <0x0 0x01c21800 0x0 0x400>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_NONE>;
			clocks = <&clk_keyadc>;
			status = "okay";
			key_cnt = <9>;
			key0 = <190 115>;
			key1 = <390 114>;
			key2 = <600 0x1ac>;
			key3 = <800 28>;
			key4 = <980 102>;
			key5 = <1180 0x192>;
			key6 = <1400 0x193>;
			key7 = <1600 9>;
			key8 = <1800 10>;
		};
	};
};