/*
 * Allwinner Technology CO., Ltd. sun8iw11p1 platform
 *
 * fpga support
 * modify base on juno.dts & sun8iw10
 */
/* kernel used */
/memreserve/ 0x43000000 0x00000800; /* super standby range        : [0x43000000~0x43000800], size = 2K  */
/* carveout used */
/memreserve/ 0x59200000 0x0C800000; /* ion carvout heap revserve  : [0x59200000~0x60000000], size = 200M  */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun8iw11p1-clk.dtsi"
#include "sun8iw11p1-pinctrl.dtsi"
/ {
	model = "sun8iw11p1";
	compatible = "arm,sun8iw11p1", "arm,sun8iw11p1";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
		twi0 = &twi0;
		twi1 = &twi1;
		twi2 = &twi2;
		twi3 = &twi3;
		twi4 = &twi4;
		ir0 = &ir0;
		ir1 = &ir1;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		global_timer0  = &soc_timer0;
		cci0 = &csi_cci0;
		mipi0 = &mipi0;
		mipi1 = &mipi1;
		csi0 = &csi0;
		csi1 = &csi1;
		isp0 = &isp0;
		isp1 = &isp1;
		scaler0 = &scaler0;
		scaler1 = &scaler1;
		scaler2 = &scaler2;
		scaler3 = &scaler3;
		flash0 = &flash0;
		vinc0 = &vinc0;
		vinc1 = &vinc1;
		mmc0 = &sdc0;
		mmc2 = &sdc2;
		nand0 =&nand0;
		disp = &disp;
		lcd0 = &lcd0;
		pwm = &pwm;
		pwm0 = &pwm0;
		tv0 = &tv0;
		tv1 = &tv1;
		hdmi = &hdmi;
		tvd = &tvd;
		boot_disp = &boot_disp;
		charger0 = &charger0;
		regulator0 = &regulator0;
	};

	chosen {
		bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
		linux,initrd-start = <0x0 0x0>;
		linux,initrd-end = <0x0 0x0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			cpufreq_tbl = < 480000
					600000
					720000
					816000
					1008000
					1104000
					1152000
					1200000>;
			clock-latency = <2000000>;
			clock-frequency = <1008000000>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			clock-frequency = <1008000000>;
		};
	};

	n_brom {
		compatible = "allwinner,n-brom";
		reg = <0x0 0x0 0x0 0xc000>;
	};

	s_brom {
		compatible = "allwinner,s-brom";
		reg = <0x0 0x0 0x0 0x10000>;
	};

	prcm {
		compatible = "allwinner,prcm";
		reg = <0x0 0x01f01400 0x0 0x400>;
	};

	cpuscfg {
		compatible = "allwinner,cpuscfg";
		reg = <0x0 0x01f01c00 0x0 0x400>;
	};

	ion {
		compatible = "allwinner,sunxi-ion";
		/*types is list here:
			ION_HEAP_TYPE_SYSTEM = 0,
			ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
			ION_HEAP_TYPE_CARVEOUT = 2,
			ION_HEAP_TYPE_CHUNK = 3,
			ION_HEAP_TYPE_DMA = 4
		**/
		system_contig{
			type = <1>;
			name = "system_contig";
		};
		carvout{
			type = <2>;
			name = "carvout";
			base = <0x59200000>;
			size = <0x0C800000>;
		};
		system{
			type = <0>;
			name = "system";
		};
	};

	dram: dram {
		compatible = "allwinner,dram";
		clocks = <&clk_pll_ddr0>, <&clk_pll_ddr1>;
		clock-names = "pll_ddr0", "pll_ddr1";
		dram_clk        = <672>;
		dram_type       = <3>;
		dram_zq         = <0x003F3FDD>;
		dram_odt_en     = <1>;
		dram_para1      = <0x10f41000>;
		dram_para2      = <0x00001200>;
		dram_mr0        = <0x1A50>;
		dram_mr1        = <0x40>;
		dram_mr2        = <0x10>;
		dram_mr3        = <0>;
		dram_tpr0       = <0x04E214EA>;
		dram_tpr1       = <0x004214AD>;
		dram_tpr2       = <0x10A75030>;
		dram_tpr3       = <0>;
		dram_tpr4       = <0>;
		dram_tpr5       = <0>;
		dram_tpr6       = <0>;
		dram_tpr7       = <0>;
		dram_tpr8       = <0>;
		dram_tpr9       = <0>;
		dram_tpr10      = <0>;
		dram_tpr11      = <0>;
		dram_tpr12      = <168>;
		dram_tpr13      = <0x823>;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0x00000000 0x40000000>;
	};

	gic: interrupt-controller@1c81000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		device_type = "gic";
		interrupt-controller;
		reg = <0x0 0x01c81000 0 0x1000>, /* GIC Dist */
		      <0x0 0x01c82000 0 0x2000>, /* GIC CPU */
			  <0x0 0x01c84000 0 0x2000>, /* GIC VCPU Control */
			  <0x0 0x01c86000 0 0x2000>; /* GIC VCPU */
		interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
	};

	sid: sunxi-sid@1c1B000 {
		compatible = "allwinner,sunxi-sid";
		device_type = "sid";
		reg = <0x0 0x01c1B000 0 0x0200>;
	};

	chipid: sunxi-chipid@1c1B200 {
		compatible = "allwinner,sunxi-chipid";
		device_type = "chipid";
		reg = <0x0 0x01c1B200 0 0x0200>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 0xff01>, /* Secure Phys IRQ */
			     <GIC_PPI 14 0xff01>; /* Non-secure Phys IRQ */
		clock-frequency = <24000000>;
	};

	wdt: watchdog@01c20ca0 {
		 compatible = "allwinner,sun4i-wdt";
		 reg = <0x0 0x01c20c90 0 0x18>;
	 };

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 120 4>,
			     <GIC_SPI 121 4>,
			     <GIC_SPI 122 4>,
			     <GIC_SPI 123 4>;
	};

	dvfs_table: dvfs_table {
		compatible = "allwinner,dvfs_table";
		max_freq = <1200000000>;
		min_freq = <480000000>;
		lv_count = <8>;
		lv1_freq = <1200000000>;
		lv1_volt = <1300>;
		lv2_freq = <1104000000>;
		lv2_volt = <1240>;
		lv3_freq = <1008000000>;
		lv3_volt = <1160>;
		lv4_freq = <912000000>;
		lv4_volt = <1100>;
		lv5_freq = <720000000>;
		lv5_volt = <1000>;
		lv6_freq = <0>;
		lv6_volt = <1000>;
		lv7_freq = <0>;
		lv7_volt = <1000>;
		lv8_freq = <0>;
		lv8_volt = <1000>;
	};

	dramfreq {
		compatible = "allwinner,sunxi-dramfreq";
		reg = <0x0 0x01c62000 0x0 0x1000>,
				<0x0 0x01c63000 0x0 0x1000>,
				<0x0 0x01c20000 0x0 0x800>;
		interrupts = <GIC_SPI 66 0x4>;
		clocks = <&clk_pll_ddr0>,<&clk_pll_ddr1>,<&clk_ahb1>;
		status = "okay";
	};

	uboot: uboot {
	};

	gpu_mali400_0: gpu@0x01c40000 {
		compatible = "arm,mali-400", "arm,mali-utgard";
		reg = <0x0 0x01c40000 0x0 0x10000>;
		interrupts = <GIC_SPI 69 4>, <GIC_SPI 70 4>, <GIC_SPI 71 4>, <GIC_SPI 72 4>, <GIC_SPI 74 4>, <GIC_SPI 75 4>;
		interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
		clocks = <&clk_pll_gpu>, <&clk_gpu>;
	};

	soc: soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		device_type = "soc";

		sram-controller@01c00000 {
			device_type = "sram-controller";
			compatible = "allwinner,sun4i-a10-sram-controller";
			reg = <0x0 0x01c00000 0x0 0x24>;
			#address-cells = <1>;
			#size-cells = <1>;

			sram_a: sram@00000000 {
				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;

				emac_sram: sram-section@8000 {
					compatible = "allwinner,sun4i-a10-sram-a3-a4";
					#size-cells = <1>;
					reg = <0x8000 0x4000>;
					status = "okay";
				};
			};

			sram_d: sram@00010000 {
				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

				otg_sram: sram-section@0000 {
					compatible = "allwinner,sun4i-a10-sram-d";
					#size-cells = <1>;
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

		dma0:dma-controller@01c02000 {
			compatible = "allwinner,sun50i-dma";
			reg = <0x0 0x01c02000 0x0 0x1000>;
			interrupts = <GIC_SPI 27 4>;
			clocks = <&clk_dma>;
			#dma-cells = <1>;
		};

		mbus0:mbus-controller@01c62000 {
			compatible = "allwinner,sun8i-b100-mbus";
			reg = <0x0 0x01c62000 0x0 0x110>;
			#mbus-cells = <1>;
		};

		standby_space {
			compatible = "allwinner,standby_space";
			/* num    dst        offset     size						*/
			space1 = <0x43000000 0x00000000 0x00000800>; /* super standby para space        */
		};

		soc_timer0: timer@1c20c00 {
			compatible = "allwinner,sunxi-timer";
			device_type = "timer";
			reg = <0x0 0x01c20c00 0x0 0x90>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			clock-frequency = <24000000>;
			timer-prescale = <16>;
		};

		rtc: rtc@01c20400 {
			compatible = "allwinner,sun8iw11p1-rtc";
			device_type = "rtc";
			reg = <0x0 0x01c20400 0x0 0x1FC>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			gpr_offset = <0x100>;
			gpr_len	   = <4>;
		};

		ir0: ir@01c21800 {
			compatible = "allwinner,ir";
			reg = <0x0 0x01c21800 0x0 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&ir0_pins_a>;
			clocks = <&clk_hosc>,<&clk_ir0>;
			supply = "vcc-pl";
			supply_vol = <3300000>;
			status = "okay";
		};

		ir1: ir@01c21c00 {
			compatible = "allwinner,ir";
			reg = <0x0 0x01c21c00 0x0 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&ir1_pins_a>;
			clocks = <&clk_hosc>,<&clk_ir1>;
			supply = "vcc-pl";
			supply_vol = <3300000>;
			status = "disabled";
		};

		ve:	ve@01c0e000 {
			compatible = "allwinner,sunxi-cedar-ve";
			reg = <0x0 0x01c0e000 0x0 0x1000>,
					<0x0 0x01c00000 0x0 0x10>,
					<0x0 0x01c20000 0x0 0x800>;
			interrupts = <GIC_SPI 53 4>;
			clocks = <&clk_pll_ve>,
							<&clk_ve>;

		};

		uart0: uart@01c28000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart0";
			reg = <0x0 0x01c28000 0x0 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart0>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart0_pins_a>;
			pinctrl-1 = <&uart0_pins_b>;
			uart0_port = <0>;
			uart0_type = <2>;
			status = "disabled";
		};

		uart1: uart@01c28400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart1";
			reg = <0x0 0x01c28400 0x0 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart1_pins_a>;
			pinctrl-1 = <&uart1_pins_b>;
			uart1_port = <1>;
			uart1_type = <8>;
			status = "disabled";
		};

		uart2: uart@01c28800 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart2";
			reg = <0x0 0x01c28800 0x0 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart2>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart2_pins_a>;
			pinctrl-1 = <&uart2_pins_b>;
			uart2_port = <2>;
			uart2_type = <4>;
			status = "disabled";
		};

		uart3: uart@01c28c00 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart3";
			reg = <0x0 0x01c28c00 0x0 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart3>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart3_pins_a>;
			pinctrl-1 = <&uart3_pins_b>;
			uart3_port = <3>;
			uart3_type = <4>;
			status = "disabled";
		};

		uart4: uart@01c29000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart4";
			reg = <0x0 0x01c29000 0x0 0x400>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart4>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart4_pins_a>;
			pinctrl-1 = <&uart4_pins_b>;
			uart4_port = <4>;
			uart4_type = <2>;
			status = "disabled";
		};

		uart5: uart@01c29400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart5";
			reg = <0x0 0x01c29400 0x0 0x400>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart5>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart5_pins_a>;
			pinctrl-1 = <&uart5_pins_b>;
			uart5_port = <5>;
			uart5_type = <2>;
			status = "disabled";
		};

		uart6: uart@01c29800 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart6";
			reg = <0x0 0x01c29800 0x0 0x400>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart6>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart6_pins_a>;
			pinctrl-1 = <&uart6_pins_b>;
			uart6_port = <6>;
			uart6_type = <2>;
			status = "disabled";
		};

		uart7: uart@01c29c00 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart7";
			reg = <0x0 0x01c29c00 0x0 0x400>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart7>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart7_pins_a>;
			pinctrl-1 = <&uart7_pins_b>;
			uart7_port = <7>;
			uart7_type = <2>;
			status = "disabled";
		};

		can0: can@0x01c2bc00{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sunxi-can";
			device_type = "can0";
			reg = <0x0 0x01c2bc00 0x0 0x400>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_can>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&can0_pins_a>;
			pinctrl-1 = <&can0_pins_b>;
			status = "disabled";
		};

		twi0: twi@0x01c2ac00{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi0";
			reg = <0x0 0x01c2ac00 0x0 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi0>;
			clock-frequency = <400000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi0_pins_a>;
			pinctrl-1 = <&twi0_pins_b>;
			status = "disabled";

			pmu0: pmu@0{
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
				status = "okay";

				powerkey0: powerkey@0{
					status = "okay";
				};

				regulator0: regulator@0{
					status = "okay";
				};

				axp_gpio0: axp_gpio@0{
					gpio-controller;
					#size-cells = <0>;
					#gpio-cells = <6>;
					status = "okay";
					device_type = "axp_pio";
				};

				charger0: charger@0{
					status = "okay";
				};
			};
		};

		twi1: twi@0x01c2b000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi1";
			reg = <0x0 0x01c2b000 0x0 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi1>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi1_pins_a>;
			pinctrl-1 = <&twi1_pins_b>;
			status = "disabled";
		};

		twi2: twi@0x01c2b400{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi2";
			reg = <0x0 0x01c2b400 0x0 0x400>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi2>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi2_pins_a>;
			pinctrl-1 = <&twi2_pins_b>;
			status = "disabled";
		};

		twi3: twi@0x01c2b800{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi3";
			reg = <0x0 0x01c2b800 0x0 0x400>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi3>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi3_pins_a>;
			pinctrl-1 = <&twi3_pins_b>;
			status = "disabled";
		};

		twi4: twi@0x01c2c000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi4";
			reg = <0x0 0x01c2c000 0x0 0x400>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi4>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi4_pins_a>;
			pinctrl-1 = <&twi4_pins_b>;
			status = "disabled";
		};

		spi0: spi@01c05000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi0";
			reg = <0x0 0x01c05000 0x0 0x1000>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0>, <&clk_spi0>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi0_pins_a &spi0_pins_b &spi0_pins_c>;
			pinctrl-1 = <&spi0_pins_d>;
			spi0_cs_number = <2>;
			spi0_cs_bitmap = <3>;
			status = "disabled";
		};

		spi1: spi@01c06000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi1";
			reg = <0x0 0x01c06000 0x0 0x1000>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0>, <&clk_spi1>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
			pinctrl-1 = <&spi1_pins_c>;
			spi1_cs_number = <2>;
			spi1_cs_bitmap = <3>;
			status = "disabled";
		};

		spi2: spi@01c17000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi2";
			reg = <0x0 0x01c17000 0x0 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0>, <&clk_spi2>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_pins_a &spi2_pins_b>;
			pinctrl-1 = <&spi2_pins_c>;
			spi2_cs_number = <2>;
			spi2_cs_bitmap = <3>;
			status = "disabled";
		};

		spi3: spi@01c1F000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi3";
			reg = <0x0 0x01c1F000 0x0 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0>, <&clk_spi3>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi3_pins_a &spi3_pins_b>;
			pinctrl-1 = <&spi3_pins_c>;
			spi3_cs_number = <2>;
			spi3_cs_bitmap = <3>;
			status = "disabled";
		};
		usbc0:usbc0@0 {
			device_type         = "usbc0";
			compatible          = "allwinner,sunxi-otg-manager";
			usb_port_type       = <2>;
			usb_detect_type     = <1>;
			usb_detect_mode     = <0>;
			usb_id_gpio;
			usb_det_vbus_gpio;
			usb_drv_vbus_gpio;
			usb_host_init_state = <0>;
			usb_regulator_io    = "nocare";
			usb_wakeup_suspend  = <0>;
			usb_luns            = <3>;
			usb_serial_unique   = <0>;
			usb_serial_number   = "20080411";
			rndis_wceis         = <1>;
			status              = "okay";
		};

		udc:udc-controller@0x01c13000 {
			compatible          = "allwinner,sunxi-udc";
			reg                 = <0x0 0x01c13000 0x0 0x1000>, /*udc base*/
			                      <0x0 0x01c00000 0x0 0x100>; /*sram base*/
			interrupts          = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy0>, <&clk_usbotg>;
			status              = "okay";
		};

		ehci0:ehci0-controller@0x01c14000 {
			compatible          = "allwinner,sunxi-ehci0";
			reg                 = <0x0 0x01c14000 0x0 0xFFF>, /*hci0 base*/
			                      <0x0 0x01c00000 0x0 0x100>, /*sram base*/
			                      <0x0 0x01c13000 0x0 0x1000>; /*otg base*/
			interrupts          = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy0>, <&clk_usbehci0>;
			hci_ctrl_no         = <0>;
			status              = "okay";
		};

		ohci0:ohci0-controller@0x01c14400 {
			compatible          = "allwinner,sunxi-ohci0";
			reg                 = <0x0 0x01c14000 0x0 0xFFF>, /*hci0 base*/
			                      <0x0 0x01c00000 0x0 0x100>, /*sram base*/
			                      <0x0 0x01c13000 0x0 0x1000>; /*otg base*/
			interrupts          = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci012m>, <&clk_hoscx2>, <&clk_hosc>, <&clk_losc>;
			hci_ctrl_no         = <0>;
			status              = "okay";
		};

		usbc1:usbc1@0 {
			device_type         = "usbc1";
			usb_drv_vbus_gpio;
			usb_host_init_state = <1>;
			usb_regulator_io    = "nocare";
			usb_wakeup_suspend  = <0>;
			status              = "okay";
		};

		ehci1:ehci1-controller@0x01c19000 {
			compatible          = "allwinner,sunxi-ehci1";
			reg                 = <0x0 0x01c19000 0x0 0xFFF>, /*hci1 base*/
			                      <0x0 0x01c00000 0x0 0x100>, /*sram base*/
			                      <0x0 0x01c13000 0x0 0x1000>; /*otg base*/
			interrupts          = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy1>, <&clk_usbehci1>;
			hci_ctrl_no         = <1>;
			status              = "okay";
		};

		ohci1:ohci1-controller@0x01c19400 {
			compatible          = "allwinner,sunxi-ohci1";
			reg                 = <0x0 0x01c19000 0x0 0xFFF>, /*hci1 base*/
			                      <0x0 0x01c00000 0x0 0x100>, /*sram base*/
			                      <0x0 0x01c13000 0x0 0x1000>; /*otg base*/
			interrupts          = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy1>, <&clk_usbohci1>, <&clk_usbohci112m>, <&clk_hoscx2>, <&clk_hosc>, <&clk_losc>;
			hci_ctrl_no         = <1>;
			status              = "okay";
		};

		usbc2:usbc2@0 {
			device_type         = "usbc2";
			usb_drv_vbus_gpio;
			usb_host_init_state = <1>;
			usb_regulator_io    = "nocare";
			usb_wakeup_suspend  = <0>;
			status              = "okay";
		};

		ehci2:ehci2-controller@0x01c1c000 {
			compatible          = "allwinner,sunxi-ehci2";
			reg                 = <0x0 0x01c1c000 0x0 0xFFF>, /*hci2 base*/
			                      <0x0 0x01c00000 0x0 0x100>, /*sram base*/
			                      <0x0 0x01c13000 0x0 0x1000>; /*otg base*/
			interrupts          = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy2>, <&clk_usbehci2>;
			hci_ctrl_no         = <2>;
			status              = "okay";
		};

		ohci2:ohci2-controller@0x01c1c400 {
			compatible          = "allwinner,sunxi-ohci2";
			reg                 = <0x0 0x01c1c000 0x0 0xFFF>, /*hci2 base*/
			                      <0x0 0x01c00000 0x0 0x100>, /*sram base*/
			                      <0x0 0x01c13000 0x0 0x1000>; /*otg base*/
			interrupts          = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			clocks              = <&clk_usbphy2>, <&clk_usbohci2>, <&clk_usbohci212m>, <&clk_hoscx2>, <&clk_hosc>, <&clk_losc>;
			hci_ctrl_no         = <2>;
			status              = "okay";
		};

		codec:codec@0x01c22c00 {
			compatible = "allwinner,sunxi-internal-codec";
			reg = <0x0 0x01c22c00 0x0 0x2bc>,/*digital baseadress*/
			      <0x0 0x01c22f00 0x0 0x4>;/*analog baseadress*/
			clocks = <&clk_pll_audio>,<&clk_adda>;
			headphonevol =  <0x3b>;
			spkervol =  <0x1b>;
			maingain =  <0x4>;
			hp_dirused = <0x0>;
			pa_sleep_time = <0x15e>;
			status = "okay";
		};

		cpudai:cpudai0-controller@0x01c22c00 {
			compatible = "allwinner,sunxi-internal-cpudai";
			reg = <0x0 0x01c22c00 0x0 0x2bc>;/*digital baseadress*/
			status = "okay";
		};

		daudio0:daudio@0x01c22000 {
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x01c22000 0x0 0x70>;
			clocks = <&clk_pll_audio>,<&clk_i2s0>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&daudio0_pins_a>;
			pinctrl-1 = <&daudio0_pins_b>;
			pcm_lrck_period =  <0x20>;
			pcm_lrckr_period =  <0x01>;
			slot_width_select =  <0x20>;
			pcm_lsb_first =  <0x0>;
			tx_data_mode =  <0x0>;
			rx_data_mode =  <0x0>;
			daudio_master =  <0x04>;
			audio_format =  <0x01>;
			signal_inversion =  <0x01>;
			frametype =  <0x0>;
			tdm_config =  <0x01>;
			mclk_div = <0x0>;
			tdm_num = <0x0>;
			status = "okay";
		};
		daudio1:daudio@0x01c22400 {
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x01c22400 0x0 0x70>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&daudio1_pins_a>;
			pinctrl-1 = <&daudio1_pins_b>;
			clocks = <&clk_pll_audio>,<&clk_i2s1>;
			pcm_lrck_period =  <0x20>;
			pcm_lrckr_period =  <0x01>;
			slot_width_select =  <0x20>;
			pcm_lsb_first =  <0x0>;
			tx_data_mode =  <0x0>;
			rx_data_mode =  <0x0>;
			daudio_master =  <0x04>;
			audio_format =  <0x01>;
			signal_inversion =  <0x01>;
			frametype =  <0x0>;
			tdm_config =  <0x01>;
			mclk_div = <0x0>;
			tdm_num = <0x1>;
			status = "okay";
		};
		daudio2:daudio@0x01c22800{
			compatible = "allwinner,sunxi-tdmhdmi";
			reg = <0x0 0x01c22800 0x0 0x58>;
			clocks = <&clk_pll_audio>,<&clk_i2s2>;
			status = "okay";
		};
		spdif:spdif-controller@0x01c21000{
			compatible = "allwinner,sunxi-spdif";
			reg = <0x0 0x01c21000 0x0 0x38>;
			clocks = <&clk_pll_audio>,<&clk_spdif>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&spdif_pins_a>;
			pinctrl-1 = <&spdif_pins_b>;
			status = "okay";
		};
		sndcodec:sound@0 {
			compatible = "allwinner,sunxi-codec-machine";
			interrupts = <GIC_SPI 28 4>;
			sunxi,cpudai-controller = <&cpudai>;
			sunxi,audio-codec = <&codec>;
			hp_detect_case = <0x00>;
			/* jack_det_gpio = <&pio PH 12 1 0 1 0>; */
			/* invert: 0->high is plug_in, 1->high is plug_out */
			jack_invert = <1>;
			status = "okay";
		};
		snddaudio0:sound@1{
			compatible = "allwinner,sunxi-daudio0-machine";
			sunxi,daudio0-controller = <&daudio0>;
			status = "okay";
		};
		snddaudio1:sound@2{
			compatible = "allwinner,sunxi-daudio1-machine";
			sunxi,daudio1-controller = <&daudio1>;
			status = "okay";
		};
		sndhdmi:sound@3{
			compatible = "allwinner,sunxi-hdmi-machine";
			sunxi,hdmi-controller = <&daudio2>;
			status = "okay";
		};
		sndspdif:sound@4{
			compatible = "allwinner,sunxi-spdif-machine";
			sunxi,spdif-controller = <&spdif>;
			status = "okay";
		};
		sdc2: sdmmc@01C11000 {
			compatible = "allwinner,sunxi-mmc-v4p5x";
			device_type = "sdc2";
			reg = <0x0 0x01C11000 0x0 0x1000>;
			interrupts = <GIC_SPI 34 0x0104>;  /*  */
			clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc2_mod>,<&clk_sdmmc2_bus>,<&clk_sdmmc2_rst>;
	    clock-names = "osc24m","pll_periph","mmc","ahb","rst";
      pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc2_pins_a>;
			pinctrl-1 = <&sdc2_pins_b>;
				bus-width = <8>;
			/*mmc-ddr-1_8v;*/
			/*mmc-hs200-1_8v;*/
			/*mmc-hs400-1_8v;*/
			/*non-removable;*/
			/*max-frequency = <200000000>;*/
			max-frequency = <50000000>;

			/*-- speed mode --*/
			/*sm0: DS26_SDR12*/
			/*sm1: HSSDR52_SDR25*/
			/*sm2: HSDDR52_DDR50*/
			/*sm3: HS200_SDR104*/
			/*sm4: HS400*/
			/*-- frequency point --
			/*f0: CLK_400K*/
			/*f1: CLK_25M*/
			/*f2: CLK_50M*/
			/*f3: CLK_100M*/
			/*f4: CLK_150M*/
			/*f5: CLK_200M*/

			sdc_tm4_sm0_freq0 = <0>;
			sdc_tm4_sm0_freq1 = <0>;
			sdc_tm4_sm1_freq0 = <0x00000000>;
			sdc_tm4_sm1_freq1 = <0>;
			sdc_tm4_sm2_freq0 = <0x00000000>;
			sdc_tm4_sm2_freq1 = <0>;
			sdc_tm4_sm3_freq0 = <0x05000000>;
			sdc_tm4_sm3_freq1 = <0x00000005>;
			sdc_tm4_sm4_freq0 = <0x00050000>;
			sdc_tm4_sm4_freq1 = <0x00000004>;

			/*vmmc-supply = <&reg_3p3v>;*/
			/*vqmc-supply = <&reg_3p3v>;*/
			/*vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
	    /*sunxi-power-save-mode;*/
			status = "disabled";
			/*status = "okay";*/

       };

		sdc0: sdmmc@01c0f000 {
			compatible = "allwinner,sunxi-mmc-v4p1x";
			device_type = "sdc0";
			reg = <0x0 0x01c0f000 0x0 0x1000>; /* only sdmmc0 */
			interrupts = <GIC_SPI 32 0x0104>;  /*  */
			clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc0_mod>,<&clk_sdmmc0_bus>,<&clk_sdmmc0_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc0_pins_a>;
			pinctrl-1 = <&sdc0_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*cd-inverted*/
			cd-gpios = <&pio PF 6 0 1 2 0>;
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 1>;*/
			/*sunxi-dly-52M-ddr4  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr8  = <1 0 0 0>;*/
			/*sunxi-dly-104M  = <1 0 0 0>;*/
			/*sunxi-dly-208M  = <1 0 0 0>;*/
			/*sunxi-dly-104M-ddr  = <1 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0>;*/

			status = "okay";
			/*status = "disabled";*/
		};


		sdc1: sdmmc@1C10000 {
			compatible = "allwinner,sunxi-mmc-v4p1x";
			device_type = "sdc1";
			reg = <0x0 0x1C10000 0x0 0x1000>;
			interrupts = <GIC_SPI 33 0x0104>;  /*  */
			clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc1_mod>,<&clk_sdmmc1_bus>,<&clk_sdmmc1_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc1_pins_a>;
			pinctrl-1 = <&sdc1_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			sunxi-dly-52M-ddr4  = <1 0 0 0 2>;
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			sunxi-dly-104M  = <1 0 0 0 1>;
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			sunxi-dly-208M  = <1 0 0 0 1>;
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/


			/*status = "okay";*/
			status = "disabled";
		};


		sdc3: sdmmc@01C12000 {
			compatible = "allwinner,sunxi-mmc-v4p1x";
			device_type = "sdc3";
			reg = <0x0 0x01C12000 0x0 0x1000>;
			interrupts = <GIC_SPI 35 0x0104>;  /*  */
			clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc3_mod>,<&clk_sdmmc3_bus>,<&clk_sdmmc3_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc3_pins_a>;
			pinctrl-1 = <&sdc3_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			sunxi-dly-52M-ddr4  = <1 0 0 0 2>;
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			sunxi-dly-104M  = <1 0 0 0 1>;
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			sunxi-dly-208M  = <1 0 0 0 1>;
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/


			/*status = "okay";*/
			status = "disabled";
		};

		disp: disp@01000000 {
			compatible = "allwinner,sun50i-disp";
			reg = <0x0 0x01000000 0x0 0x00300000>,/*de*/
				<0x0 0x01c70000 0x0 0xfff>,/*tcon top*/
				<0x0 0x01c71000 0x0 0xfff>,/*tcon0*/
				<0x0 0x01c72000 0x0 0xfff>,/*tcon1*/
				<0x0 0x01c73000 0x0 0xfff>,/*tcon2*/
				<0x0 0x01c74000 0x0 0xfff>,/*tcon3*/
				<0x0 0x01ca0000 0x0 0x10fc>;/*dsi*/
			interrupts = <GIC_SPI 44 0x0104>, <GIC_SPI 45 0x0104>,
				<GIC_SPI 51 0x0104>, <GIC_SPI 52 0x0104>,
				<GIC_SPI 57 0x0104>;/* for dsi */
			clocks = <&clk_de>,<&clk_tcon_top>,
						<&clk_tcon0>,<&clk_tcon1>,
						<&clk_tcon_tv0>,<&clk_tcon_tv1>,<&clk_lvds>,<&clk_mipidsi>;
			boot_disp = <0>;
			fb_base = <0>;

			status = "okay";
		};

		hdmi: hdmi@01ee0000 {
			compatible = "allwinner,sunxi-hdmi";
			reg = <0x0 0x01ee0000 0x0 0x20000>;
			clocks = <&clk_hdmi>,<&clk_hdmi_slow>;
		};

		lcd0: lcd0@01c0c000 {
			compatible = "allwinner,sunxi-lcd0";
			pinctrl-names = "active","sleep";

			status = "okay";
		};

		tv0: tv0@01c94000 {
			compatible = "allwinner,sunxi-tv";
			reg = <0x0 0x01c90000 0x0 0x100>,
				<0x0 0x01c94000 0x0 0x3fc>;
			clocks = <&clk_tve_top>,<&clk_tve0>;
			device_type = "tv0";
			pinctrl-names = "active","sleep";
			status = "disabled";
		};

		tv1: tv1@01c98000 {
			compatible = "allwinner,sunxi-tv";
			reg = <0x0 0x01c90000 0x0 0x100>,
				<0x0 0x01c98000 0x0 0x3fc>;
			clocks = <&clk_tve_top>,<&clk_tve1>;
			device_type = "tv1";
			pinctrl-names = "active","sleep";
			status = "disabled";
		};

		tvd: tvd@01c30000 {
			compatible = "allwinner,sunxi-tvd";
			reg = <0x0 0x01c30000 0x0 0x00010000>;/*tvd_top*/
			clocks = <&clk_tvd_top>;
			interrupts = <GIC_SPI 61 0x0104>;
			tvd-number = <4>;
			tvds = <&tvd0>, <&tvd1>, <&tvd2>, <&tvd3>;
			status = "okay";
		};

		tvd0: tvd0@01c31000 {
			compatible = "allwinner,sunxi-tvd0";
			reg = <0x0 0x01c31000 0x0 0x00010000>;
			interrupts = <GIC_SPI 97 0x0104>;
			clocks = <&clk_tvd0>;
			tvd_used = <1>;
			tvd_if = <0>;
			status = "okay";
		};

		tvd1: tvd1@01c32000 {
			compatible = "allwinner,sunxi-tvd1";
			reg = <0x0 0x01c32000 0x0 0x00010000>;
			interrupts = <GIC_SPI 98 0x0104>;
			clocks = <&clk_tvd1>;
			tvd_used = <1>;
			tvd_if = <0>;
			status = "okay";
		};

		tvd2: tvd2@01c33000 {
			compatible = "allwinner,sunxi-tvd2";
			reg = <0x0 0x01c33000 0x0 0x00010000>;
			interrupts = <GIC_SPI 99 0x0104>;
			clocks = <&clk_tvd2>;
			tvd_used = <1>;
			tvd_if = <0>;
			status = "okay";
		};

		tvd3: tvd3@01c34000 {
			compatible = "allwinner,sunxi-tvd3";
			reg = <0x0 0x01c34000 0x0 0x00010000>;
			interrupts = <GIC_SPI 100 0x0104>;
			clocks = <&clk_tvd3>;
			tvd_used = <1>;
			tvd_if = <0>;
			status = "okay";
		};

		soc_tr: tr@01000000 {
			compatible = "allwinner,sun8iw11-tr";
			reg = <0x0 0x01000000 0x0 0x000200bc>;
			interrupts = <GIC_SPI 96 0x0104>;
			clocks = <&clk_de>;
			status = "okay";
		};

		g2d: g2d@01e80000 {
			compatible = "allwinner,sunxi-g2d";
			reg = <0x0 0x01e80000 0x0 0x800>;
			interrupts = <GIC_SPI 46 0x0104>;
			clocks = <&clk_de_mp>;
			status = "okay";
		};

		pwm: pwm@01c23400 {
			compatible = "allwinner,sunxi-pwm";
			reg = <0x0 0x01c23400 0x0 0x154>;
			pwm-number = <1>;
			pwm-base = <0x0>;
			pwms = <&pwm0>, <&pwm1>;
		};

		pwm0: pwm0@01c23400 {
			compatible = "allwinner,sunxi-pwm0";
			pinctrl-names = "active", "sleep";
			reg_base = <0x01c23400>;
			reg_peci_offset = <0x00>;
			reg_peci_shift = <0x00>;
			reg_peci_width = <0x01>;

			reg_pis_offset = <0x04>;
			reg_pis_shift = <0x00>;
			reg_pis_width = <0x01>;

			reg_crie_offset = <0x10>;
			reg_crie_shift = <0x00>;
			reg_crie_width = <0x01>;

			reg_cfie_offset = <0x10>;
			reg_cfie_shift = <0x01>;
			reg_cfie_width = <0x01>;

			reg_cris_offset = <0x14>;
			reg_cris_shift = <0x00>;
			reg_cris_width = <0x01>;

			reg_cfis_offset = <0x14>;
			reg_cfis_shift = <0x01>;
			reg_cfis_width = <0x01>;

			reg_clk_src_offset = <0x20>;
			reg_clk_src_shift = <0x07>;
			reg_clk_src_width = <0x02>;

			reg_bypass_offset = <0x20>;
			reg_bypass_shift = <0x05>;
			reg_bypass_width = <0x01>;

			reg_clk_gating_offset = <0x20>;
			reg_clk_gating_shift = <0x04>;
			reg_clk_gating_width = <0x01>;

			reg_clk_div_m_offset = <0x20>;
			reg_clk_div_m_shift = <0x00>;
			reg_clk_div_m_width = <0x04>;

			reg_pdzintv_offset = <0x30>;
			reg_pdzintv_shift = <0x08>;
			reg_pdzintv_width = <0x08>;

			reg_dz_en_offset = <0x30>;
			reg_dz_en_shift = <0x00>;
			reg_dz_en_width = <0x01>;

			reg_enable_offset = <0x40>;
			reg_enable_shift = <0x00>;
			reg_enable_width = <0x01>;

			reg_cap_en_offset = <0x44>;
			reg_cap_en_shift = <0x00>;
			reg_cap_en_width = <0x01>;

			reg_period_rdy_offset = <0x60>;
			reg_period_rdy_shift = <0x0b>;
			reg_period_rdy_width = <0x01>;

			reg_pul_start_offset = <0x60>;
			reg_pul_start_shift = <0x0a>;
			reg_pul_start_width = <0x01>;

			reg_mode_offset = <0x60>;
			reg_mode_shift = <0x09>;
			reg_mode_width = <0x01>;

			reg_act_sta_offset = <0x60>;
			reg_act_sta_shift = <0x08>;
			reg_act_sta_width = <0x01>;

			reg_prescal_offset = <0x60>;
			reg_prescal_shift = <0x00>;
			reg_prescal_width = <0x08>;

			reg_entire_offset = <0x64>;
			reg_entire_shift = <0x10>;
			reg_entire_width = <0x10>;

			reg_active_offset = <0x64>;
			reg_active_shift = <0x00>;
			reg_active_width = <0x10>;
		};

		pwm1: pwm1@01c23400 {
			compatible = "allwinner,sunxi-pwm1";
			pinctrl-names = "active", "sleep";
			reg_base = <0x01c23400>;
			reg_peci_offset = <0x00>;
			reg_peci_shift = <0x01>;
			reg_peci_width = <0x01>;

			reg_pis_offset = <0x04>;
			reg_pis_shift = <0x01>;
			reg_pis_width = <0x01>;

			reg_crie_offset = <0x10>;
			reg_crie_shift = <0x00>;
			reg_crie_width = <0x01>;

			reg_cfie_offset = <0x10>;
			reg_cfie_shift = <0x01>;
			reg_cfie_width = <0x01>;

			reg_cris_offset = <0x14>;
			reg_cris_shift = <0x01>;
			reg_cris_width = <0x01>;

			reg_cfis_offset = <0x14>;
			reg_cfis_shift = <0x01>;
			reg_cfis_width = <0x01>;

			reg_clk_src_offset = <0x20>;
			reg_clk_src_shift = <0x07>;
			reg_clk_src_width = <0x02>;

			reg_bypass_offset = <0x20>;
			reg_bypass_shift = <0x06>;
			reg_bypass_width = <0x01>;

			reg_clk_gating_offset = <0x20>;
			reg_clk_gating_shift = <0x04>;
			reg_clk_gating_width = <0x01>;

			reg_clk_div_m_offset = <0x20>;
			reg_clk_div_m_shift = <0x00>;
			reg_clk_div_m_width = <0x04>;

			reg_pdzintv_offset = <0x30>;
			reg_pdzintv_shift = <0x08>;
			reg_pdzintv_width = <0x08>;

			reg_dz_en_offset = <0x30>;
			reg_dz_en_shift = <0x00>;
			reg_dz_en_width = <0x01>;

			reg_enable_offset = <0x40>;
			reg_enable_shift = <0x01>;
			reg_enable_width = <0x01>;

			reg_cap_en_offset = <0x44>;
			reg_cap_en_shift = <0x01>;
			reg_cap_en_width = <0x01>;

			reg_period_rdy_offset = <0x80>;
			reg_period_rdy_shift = <0x0b>;
			reg_period_rdy_width = <0x01>;

			reg_pul_start_offset = <0x80>;
			reg_pul_start_shift = <0x0a>;
			reg_pul_start_width = <0x01>;

			reg_mode_offset = <0x80>;
			reg_mode_shift = <0x09>;
			reg_mode_width = <0x01>;

			reg_act_sta_offset = <0x80>;
			reg_act_sta_shift = <0x08>;
			reg_act_sta_width = <0x01>;

			reg_prescal_offset = <0x80>;
			reg_prescal_shift = <0x00>;
			reg_prescal_width = <0x08>;

			reg_entire_offset = <0x84>;
			reg_entire_shift = <0x10>;
			reg_entire_width = <0x10>;

			reg_active_offset = <0x84>;
			reg_active_shift = <0x00>;
			reg_active_width = <0x10>;
		};

		boot_disp: boot_disp {
			compatible = "allwinner,boot_disp";
		};

		csi_cci0:cci@0x01cb3000 {
			compatible = "allwinner,sunxi-csi_cci";
			reg = <0x0 0x01cb3000 0x0 0x1000>;	/*0x01cb3000--0x01cb4000*/
			interrupts = <GIC_SPI 85 4>;/*SUNXI_IRQ_CSI0_CCI (SUNXI_GIC_START + 85) = 117*/
			status = "disabled";
		};
		csi0:csi@0x01c09000 {
			device_type = "csi0";
			compatible = "allwinner,sunxi-csi";
			reg = <0x0 0x01c09000 0x0 0x1000>;/*0x01c09000--0x01c0a000*/
			clocks 				= <&clk_csi_s>, <&clk_csi0_m>,
							<&clk_pll_periph0>,<&clk_hosc>;
			clocks-index		= <0 1 0xff 2 3 0xff>;
			pinctrl-names 		= "default","sleep";
			pinctrl-0 		= <&csi0_pins_a>;
			pinctrl-1 		= <&csi0_pins_b>;
			status = "okay";
		};
		csi1:csi@0x01c1d000 {
			device_type = "csi1";
			compatible = "allwinner,sunxi-csi";
			reg = <0x0 0X01c1d000 0x0 0x1000>;/*0X01c1d000--0x01c0e000*/
			clocks 				= <&clk_csi_s>, <&clk_csi1_m>,
							<&clk_pll_periph0>,<&clk_hosc>;
			clocks-index		= <0 1 0xff 2 3 0xff>;
			pinctrl-names 		= "default","sleep";
			pinctrl-0 		= <&csi1_pins_a>;
			pinctrl-1 		= <&csi1_pins_b>;
			status = "okay";
		};
		mipi0:mipi@0 {
			compatible = "allwinner,sunxi-mipi";
			status = "disabled";
		};
		mipi1:mipi@1 {
			compatible = "allwinner,sunxi-mipi";
			status = "disabled";
		};
		isp0:isp@0 {
			compatible = "allwinner,sunxi-isp";
			status = "okay";
		};
		isp1:isp@1 {
			compatible = "allwinner,sunxi-isp";
			status = "okay";
		};
		scaler0:scaler@0 {
			compatible = "allwinner,sunxi-scaler";
			status = "okay";
		};
		scaler1:scaler@1 {
			compatible = "allwinner,sunxi-scaler";
			status = "okay";
		};
		scaler2:scaler@2 {
			compatible = "allwinner,sunxi-scaler";
			status = "okay";
		};
		scaler3:scaler@3 {
			compatible = "allwinner,sunxi-scaler";
			status = "okay";
		};
		actuator0:actuator@0 {
			device_type = "actuator0";
			compatible = "allwinner,sunxi-actuator";
			actuator0_name		= "ad5820_act";
			actuator0_slave		= <0x18>;
			actuator0_af_pwdn	= <>;
			actuator0_afvdd         = "afvcc-csi";
			actuator0_afvdd_vol     = <2800000>;
			status = "disabled";
		};
		flash0:flash@0 {
			device_type = "flash0";
			compatible = "allwinner,sunxi-flash";
			flash0_type		= <2>;
			flash0_en		= <>;
			flash0_mode		= <>;
			flash0_flvdd		= "";
			flash0_flvdd_vol	= <>;
			status = "disabled";
		};
		sensor0:sensor@0{
			device_type = "sensor0";
			sensor0_mname         	= "ov5640";
			sensor0_twi_addr	= <0x78>;
			sensor0_pos		= "rear";
			sensor0_isp_used	= <0>;
			sensor0_fmt		= <0>;
			sensor0_stby_mode	= <0>;
			sensor0_vflip		= <0>;
			sensor0_hflip		= <0>;
			sensor0_iovdd		= "csi-iovdd";
			sensor0_iovdd_vol	= <2800000>;
			sensor0_avdd		= "";
			sensor0_avdd_vol	= <2800000>;
			sensor0_dvdd		= "";
			sensor0_dvdd_vol	= <1500000>;
			sensor0_power_en	= <>;
			sensor0_reset		= <&pio PH 13 1 0 1 0>; /*PH13 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
			sensor0_pwdn 		= <&pio PH 16 1 0 1 0>; /*PH16 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
			flash_handle		= <&flash0>;
			act_handle		= <&actuator0>;
			status	= "okay";
		};
		sensor1:sensor@1{
			device_type = "sensor1";
			sensor1_mname         	= "ov2686";
			sensor1_twi_addr	= <0x20>;
			sensor1_pos		= "front";
			sensor1_isp_used	= <0>;
			sensor1_fmt		= <0>;
			sensor1_stby_mode	= <0>;
			sensor1_vflip		= <0>;
			sensor1_hflip		= <0>;
			sensor1_iovdd		= "csi-iovdd";
			sensor1_iovdd_vol	= <2800000>;
			sensor1_avdd		= "";
			sensor1_avdd_vol	= <2800000>;
			sensor1_dvdd		= "";
			sensor1_dvdd_vol	= <1500000>;
			sensor1_power_en	= <>;
			sensor1_reset		= <&pio PH 14 1 0 1 0>; /*PH14 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
			sensor1_pwdn 		= <&pio PH 17 1 0 1 0>; /*PH17 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
			flash_handle		= <>;
			act_handle		= <>;
			status	= "okay";
		};
		vinc0:vinc@0 {
			device_type = "vinc0";
			compatible = "allwinner,sunxi-vin-core";
			interrupts = <GIC_SPI 42 4>;/*SUNXI_IRQ_CSI0 (SUNXI_GIC_START + 42 ) = 74*/
			cci_sel			= <4>;
			csi_sel			= <0>;
			mipi_sel		= <0xff>;
			isp_sel			= <0>;
			scaler_sel		= <0>;
			vinc0_sensor_list	= <1>;
			isp_handle		= <&isp0>;
			sensor_handle		= <&sensor0>;
			status = "okay";
		};
		vinc1:vinc@1 {
			device_type = "vinc1";
			compatible = "allwinner,sunxi-vin-core";
			interrupts = <GIC_SPI 43 4>;/*SUNXI_IRQ_CSI1 (SUNXI_GIC_START + 43 ) = 75*/
			cci_sel			= <2>;
			csi_sel			= <1>;
			mipi_sel		= <0xff>;
			isp_sel			= <1>;
			scaler_sel		= <1>;
			vinc1_sensor_list	= <1>;
			isp_handle		= <&isp1>;
			sensor_handle		= <&sensor1>;
			status = "okay";
		};

		vind0:vind@0 {
			compatible = "allwinner,sunxi-vin-media";
			status = "okay";
		};
		Vdevice: vdevice@0{
			compatible = "allwinner,sun8i-vdevice";
			device_type = "Vdevice";
			pinctrl-names = "default";
			pinctrl-0 = <&vdevice_pins_a>;
			test-gpios = <&pio PH 0 1 2 2 1>;
			status = "okay";
		};
		cryptoengine: ce@1c15000 {
			compatible = "allwinner,sunxi-ce";
			reg = <0x0 0x01c15000 0x0 0x80>, /* non-secure space */
				  <0x0 0x01c15800 0x0 0x80>; /* secure space */
			interrupts = <GIC_SPI 94 0xff01>, /* non-secure space */
						 <GIC_SPI 80 0xff01>; /* secure space */
			clock-frequency = <300000000>, /* 300MHz */
							  <200000000>; /* 200MHz for RSA */
			clocks = <&clk_ce>, <&clk_pll_periph0x2>;
		};
		di:deinterlace@0x01400000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sunxi-deinterlace";
			reg = <0x0 0x01400000 0x0 0x77c>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_deinterlace> ,<&clk_pll_periph0>;
			status = "okay";
		};
		smc:smartcard@0x01c2c400{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sunxi-scr";
			reg = <0x0 0x01c2c400 0x0 0x400>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_scr0>, <&clk_apb2>;
			clock-frequency = <24000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&scr0_pins_a>;
			pinctrl-1 = <&scr0_pins_b>;
			status = "okay";
		};
		nmi:nmi@0{
			compatible = "allwinner,sunxi-nmi";
			reg = <0x0 0x01c00030 0x0 0x0c>;
			nmi_irq_ctrl = <0x00>;
			nmi_irq_en = <0x08>;
			nmi_irq_status = <0x04>;
			status = "okay";
		};

		nand0:nand0@01c03000 {
			compatible = "allwinner,sun8iw11-nand";
			device_type = "nand0";
			reg = <0x0 0x01c03000 0x0 0x1000>; /* nand0 */
			interrupts = <GIC_SPI 37 0x04>;
			clocks = <&clk_pll_periph0>,<&clk_nand>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
			pinctrl-1 = <&nand0_pins_c>;
			nand0_regulator1 = "vcc-nand";
			nand0_regulator2 = "none";
			nand0_cache_level = <0x55aaaa55>;
			nand0_flush_cache_num = <0x55aaaa55>;
			nand0_capacity_level = <0x55aaaa55>;
			nand0_id_number_ctl = <0x55aaaa55>;
			nand0_print_level = <0x55aaaa55>;
			nand0_p0 = <0x55aaaa55>;
			nand0_p1 = <0x55aaaa55>;
			nand0_p2 = <0x55aaaa55>;
			nand0_p3 = <0x55aaaa55>;
			status = "okay";
		};

		sunxi_thermal_sensor:thermal_sensor{
			compatible = "allwinner,thermal_sensor";
			reg = <0x0 0x01c24c00 0x0 0x84>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_NONE>;
			clocks = <&clk_hosc>,<&clk_ths>;
			sensor_num = <2>;
			shut_temp= <120>;
			status = "okay";

			combine0:combine0{
				#thermal-sensor-cells = <1>;
				combine_cnt = <2>;
				combine_type = "max";
				combine_chn = <0 1>;
			};
		};

		cpu_budget_cooling:cpu_budget_cool{
			compatible = "allwinner,budget_cooling";
			#cooling-cells = <2>;
			status = "okay";
			state_cnt = <7>;
			cluster_num = <1>;
			state0 = <1200000 4>;
			state1 = <1104000 4>;
			state2 = <1008000 4>;
			state3 = <912000 4>;
			state4 = <720000 4>;
			state5 = <720000 2>;
			state6 = <720000 1>;
		};

		gpu_cooling:gpu_cooling{
			compatible = "allwinner,gpu_cooling";
			reg = <0x0 0x0 0x0 0x0>;
			#cooling-cells = <2>;
			status = "okay";
			state_cnt = <4>;
			state0 = <384>;
			state1 = <312>;
			state2 = <240>;
			state3 = <144>;
		};

		thermal-zones{
			soc_thermal{

				polling-delay-passive = <1000>;
				polling-delay = <10000>;
				thermal-sensors = <&combine0 0>;

				trips{
					cpu_trip0:t0{
						temperature = <80>;
						type = "passive";
						hysteresis = <0>;
					};
					cpu_trip1:t1{
						temperature = <95>;
						type = "passive";
						hysteresis = <0>;
					};
					cpu_trip2:t2{
						temperature = <105>;
						type = "passive";
						hysteresis = <0>;
					};
					cpu_trip3:t3{
						temperature = <115>;
						type = "passive";
						hysteresis = <0>;
					};
					gpu_trip0:t4{
						temperature = <90>;
						type = "passive";
						hysteresis = <0>;
					};
					gpu_trip1:t5{
						temperature = <100>;
						type = "passive";
						hysteresis = <0>;
					};
					gpu_trip2:t6{
						temperature = <110>;
						type = "passive";
						hysteresis = <0>;
					};
					crt_trip:t7{
						temperature = <120>;
						type = "critical";
						hysteresis = <0>;
					};
				};

				cooling-maps{
					bind0{
						contribution = <0>;
						trip = <&cpu_trip0>;
						cooling-device = <&cpu_budget_cooling 1 1>;
					};
					bind1{
						contribution = <0>;
						trip = <&cpu_trip1>;
						cooling-device = <&cpu_budget_cooling 2 2>;
					};
					bind2{
						contribution = <0>;
						trip = <&cpu_trip2>;
						cooling-device = <&cpu_budget_cooling 3 3>;
					};
					bind3{
						contribution = <0>;
						trip = <&cpu_trip3>;
						cooling-device = <&cpu_budget_cooling 4 6>;
					};
					bind4{
						contribution = <0>;
						trip = <&gpu_trip0>;
						cooling-device = <&gpu_cooling 1 1>;
					};
					bind5{
						contribution = <0>;
						trip = <&gpu_trip1>;
						cooling-device = <&gpu_cooling 2 2>;
					};
					bind6{
						contribution = <0>;
						trip = <&gpu_trip2>;
						cooling-device = <&gpu_cooling 3 3>;
					};
				};
			};
		};

		keyboard0:keyboard{
			compatible = "allwinner,keyboard_2000mv";
			reg = <0x0 0x01c24400 0x0 0x400>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_NONE>;
			status = "okay";
			key_cnt = <5>;
			key1 = <240 115>;
			key2 = <500 114>;
			key3 = <700 139>;
			key4 = <890 28>;
			key5 = <2000 102>;
		};
		keypad0:keypad{
			compatible = "allwinner,keypad";
			reg = <0x0 0x01c23000 0x0 0x400>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_NONE>;
			clocks = <&clk_losc>,<&clk_keypad>;
			keypad_power_key_code = <0x00>;

			/* need to add keypad pinctrl */
			/* pinctrl-names = "default"; */
			/* pinctrl-0 = <&keypad pinctrl>; */
			status = "okay";
		};
		sata:sata@01c18000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-sata";
			device_type = "sata";
			reg = <0x0 0x01c18000 0x0 0x200>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_sata>, <&clk_sata>;
			sata_regulator0="vdd-sata-25";
			sata_regulator1="vdd-sata-12";
			sata_power_en;
			status = "okay";
		};

		ps20: ps2@01c2a000 {
			compatible = "allwinner,sun4i-a10-ps2";
			reg = <0x0 0x01c2a000 0x0 0x400>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_ps20>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&ps20_pins_a>;
			status = "disabled";
		};

		ps21: ps2@01c2a400 {
			compatible = "allwinner,sun4i-a10-ps2";
			reg = <0x0 0x01c2a400 0x0 0x400>;
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_ps21>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&ps21_pins_a>;
			status = "disabled";
		};

		gmac0: eth@01c50000 {
			compatible = "allwinner,sunxi-gmac";
			reg = <0x0 0x01c50000 0x0 0x40000>,
			    <0x0 0x01c20164 0x0 0x04>;
			pinctrl-names = "default";
			pinctrl-0     = <&gmac_pins_a>;
			interrupts      = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gmacirq";
			clocks   = <&clk_gmac>;
			clock-names = "gmac";
			phy-mode = "mii";
			tx-delay = <7>;
			rx-delay = <31>;
			phy-rst;
			gmac_power1 = "";
			gmac_power2 = "";
			gmac_power3 = "";
			status = "disabled";
		};

		emac0: eth@01c0B000 {
			compatible = "allwinner,sun4i-emac";
			reg = <0x0 0x01c0b000 0x0 0x0c000>;
			pinctrl-names = "default";
			pinctrl-0     = <&emac_pins_a>;
			interrupts      = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "emacirq";
			clocks   = <&clk_emac>;
			clock-names = "emac";
			phy = <&phy1>;
			phy-rst;
			allwinner,sram = <&emac_sram 1>;
			emac_power1 = "";
			emac_power2 = "";
			emac_power3 = "";
			status = "disabled";
		};

		mdio: mdio@01c0b080 {
			compatible = "allwinner,sun4i-a10-mdio";
			reg = <0x0 0x01c0b080 0x0 0x14>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";

			phy1: ethernet-phy@1 {
				reg = <1>;
			};
		};
	};
};