231 lines
8.6 KiB
C
Executable file
231 lines
8.6 KiB
C
Executable file
/*
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* linux-3.10/drivers/media/platform/sunxi-vfe/csi/csi_reg.c
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*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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***************************************************************************************
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*
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* csi_reg.c
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*
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* Hawkview ISP - csi_reg.c module
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*
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* Copyright (c) 2014 by Allwinnertech Co., Ltd. http://www.allwinnertech.com
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*
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* Version Author Date Description
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*
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* 2.0 Yang Feng 2014/07/15 Second Version
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*
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****************************************************************************************
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*/
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#include <linux/kernel.h>
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#include "csi_reg_i.h"
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#include "csi_reg.h"
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#include "../utility/vfe_io.h"
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#if defined CONFIG_ARCH_SUN8IW1P1
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#define ADDR_BIT_R_SHIFT 0
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#define CLK_POL 0
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#elif defined CONFIG_ARCH_SUN8IW3P1
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#define ADDR_BIT_R_SHIFT 0
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#define CLK_POL 1
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#elif defined CONFIG_ARCH_SUN9IW1P1
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#define ADDR_BIT_R_SHIFT 2
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#define CLK_POL 1
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#elif defined CONFIG_ARCH_SUN8IW5P1
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#define ADDR_BIT_R_SHIFT 0
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#define CLK_POL 1
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#elif defined CONFIG_ARCH_SUN8IW6P1
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#define ADDR_BIT_R_SHIFT 2
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#define CLK_POL 1
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#elif defined CONFIG_ARCH_SUN8IW7P1
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#define ADDR_BIT_R_SHIFT 2
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#define CLK_POL 1
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#elif defined CONFIG_ARCH_SUN8IW8P1
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#define ADDR_BIT_R_SHIFT 2
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#define CLK_POL 1
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#elif defined CONFIG_ARCH_SUN8IW9P1
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#define ADDR_BIT_R_SHIFT 2
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#define CLK_POL 1
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//#elif defined CONFIG_ARCH_SUN50IW1P1 //todo 2014.11.18
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#elif defined CONFIG_ARCH_SUN50I
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#define ADDR_BIT_R_SHIFT 2
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#define CLK_POL 1
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#elif defined CONFIG_ARCH_SUN8IW10P1
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#define ADDR_BIT_R_SHIFT 2
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#define CLK_POL 1
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//#else
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//#define ADDR_BIT_R_SHIFT 2
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//#define CLK_POL 1
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#endif
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volatile void __iomem *csi_base_addr[2];
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int csi_set_base_addr(unsigned int sel, unsigned long addr)
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{
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if(sel > MAX_CSI-1)
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return -1;
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csi_base_addr[sel] = (volatile void __iomem *)addr;
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return 0;
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}
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/* open module */
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void csi_enable(unsigned int sel)
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{
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vfe_reg_set(csi_base_addr[sel] + CSI_EN_REG_OFF, 1 << CSI_EN_REG_CSI_EN);
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}
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void csi_disable(unsigned int sel)
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{
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vfe_reg_clr(csi_base_addr[sel] + CSI_EN_REG_OFF, 1 << CSI_EN_REG_CSI_EN);
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}
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/* configure */
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void csi_if_cfg(unsigned int sel, struct csi_if_cfg *csi_if_cfg)
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{
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_IF_CFG_REG_OFF, CSI_IF_CFG_REG_SRC_TYPE_MASK,
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csi_if_cfg->src_type << CSI_IF_CFG_REG_SRC_TYPE);
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if(csi_if_cfg->interface < 0x80)
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_IF_CFG_REG_OFF, CSI_IF_CFG_REG_CSI_IF_MASK,
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csi_if_cfg->interface << CSI_IF_CFG_REG_CSI_IF);
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else
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_IF_CFG_REG_OFF, CSI_IF_CFG_REG_MIPI_IF_MASK,
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1 << CSI_IF_CFG_REG_MIPI_IF);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_IF_CFG_REG_OFF, CSI_IF_CFG_REG_IF_DATA_WIDTH_MASK,
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csi_if_cfg->data_width << CSI_IF_CFG_REG_IF_DATA_WIDTH);
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}
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void csi_timing_cfg(unsigned int sel, struct csi_timing_cfg *csi_tmg_cfg)
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{
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_IF_CFG_REG_OFF, CSI_IF_CFG_REG_VREF_POL_MASK,
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csi_tmg_cfg->vref<< CSI_IF_CFG_REG_VREF_POL);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_IF_CFG_REG_OFF, CSI_IF_CFG_REG_HREF_POL_MASK,
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csi_tmg_cfg->href<< CSI_IF_CFG_REG_HREF_POL);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_IF_CFG_REG_OFF, CSI_IF_CFG_REG_CLK_POL_MASK,
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((csi_tmg_cfg->sample==CLK_POL)?1:0)<< CSI_IF_CFG_REG_CLK_POL);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_IF_CFG_REG_OFF, CSI_IF_CFG_REG_FIELD_MASK,
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csi_tmg_cfg->field<< CSI_IF_CFG_REG_FIELD);
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}
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void csi_fmt_cfg(unsigned int sel, unsigned int ch, struct csi_fmt_cfg *csi_fmt_cfg)
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{
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_CFG_REG_OFF+ch*CSI_CH_OFF, CSI_CH_CFG_REG_INPUT_FMT_MASK,
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csi_fmt_cfg->input_fmt<< CSI_CH_CFG_REG_INPUT_FMT);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_CFG_REG_OFF+ch*CSI_CH_OFF, CSI_CH_CFG_REG_OUTPUT_FMT_MASK,
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csi_fmt_cfg->output_fmt<< CSI_CH_CFG_REG_OUTPUT_FMT);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_CFG_REG_OFF+ch*CSI_CH_OFF, CSI_CH_CFG_REG_FIELD_SEL_MASK,
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csi_fmt_cfg->field_sel<< CSI_CH_CFG_REG_FIELD_SEL);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_CFG_REG_OFF+ch*CSI_CH_OFF, CSI_CH_CFG_REG_INPUT_SEQ_MASK,
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csi_fmt_cfg->input_seq<< CSI_CH_CFG_REG_INPUT_SEQ);
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}
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/* buffer */
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void csi_set_buffer_address(unsigned int sel, unsigned int ch, enum csi_buf_sel buf, u64 addr)
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{
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_F0_BUFA_REG_OFF+ch*CSI_CH_OFF+ (buf<<2), 0xffffffff,
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addr >> ADDR_BIT_R_SHIFT);
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}
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u64 csi_get_buffer_address(unsigned int sel, unsigned int ch, enum csi_buf_sel buf)
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{
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unsigned int reg_val = vfe_reg_readl(csi_base_addr[sel] + CSI_CH_F0_BUFA_REG_OFF + ch*CSI_CH_OFF + (buf<<2));
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return reg_val << ADDR_BIT_R_SHIFT;
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}
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/* capture */
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void csi_capture_start(unsigned int sel, unsigned int ch_total_num, enum csi_cap_mode csi_cap_mode)
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{
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u32 reg_val = (((ch_total_num == 4) ? csi_cap_mode:0)<<24) +
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(((ch_total_num == 3) ? csi_cap_mode:0)<<16) +
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(((ch_total_num == 2) ? csi_cap_mode:0)<<8 )+
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(((ch_total_num == 1) ? csi_cap_mode:0));
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vfe_reg_writel(csi_base_addr[sel] + CSI_CAP_REG_OFF, reg_val);
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}
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void csi_capture_stop(unsigned int sel, unsigned int ch_total_num, enum csi_cap_mode csi_cap_mode)
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{
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vfe_reg_writel(csi_base_addr[sel] + CSI_CAP_REG_OFF, 0);
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}
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void csi_capture_get_status(unsigned int sel, unsigned int ch, struct csi_capture_status *status)
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{
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unsigned int reg_val = vfe_reg_readl(csi_base_addr[sel] + CSI_CH_STA_REG_OFF + ch*CSI_CH_OFF);
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status->picture_in_progress = (reg_val>>CSI_CH_STA_REG_SCAP_STA)&0x1;
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status->video_in_progress = (reg_val>>CSI_CH_STA_REG_VCAP_STA)&0x1;
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// status->field_status = (reg_val>>CSI_CH_STA_REG_FIELD_STA)&0x1;
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}
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/* size */
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void csi_set_size(unsigned int sel, unsigned int ch, unsigned int length_h, unsigned int length_v, unsigned int buf_length_y, unsigned int buf_length_c)
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{
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_HSIZE_REG_OFF + ch*CSI_CH_OFF, CSI_CH_HSIZE_REG_HOR_LEN_MASK,
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length_h<<CSI_CH_HSIZE_REG_HOR_LEN);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_VSIZE_REG_OFF + ch*CSI_CH_OFF, CSI_CH_VSIZE_REG_VER_LEN_MASK,
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length_v<<CSI_CH_VSIZE_REG_VER_LEN);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_BUF_LEN_REG_OFF + ch*CSI_CH_OFF, CSI_CH_BUF_LEN_REG_BUF_LEN_MASK,
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buf_length_y<<CSI_CH_BUF_LEN_REG_BUF_LEN);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_BUF_LEN_REG_OFF + ch*CSI_CH_OFF, CSI_CH_BUF_LEN_REG_BUF_LEN_C_MASK,
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buf_length_c<<CSI_CH_BUF_LEN_REG_BUF_LEN_C);
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}
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/* offset */
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void csi_set_offset(unsigned int sel, unsigned int ch, unsigned int start_h, unsigned int start_v)
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{
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_HSIZE_REG_OFF + ch*CSI_CH_OFF, CSI_CH_HSIZE_REG_HOR_START_MASK,
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start_h<<CSI_CH_HSIZE_REG_HOR_START);
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vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_VSIZE_REG_OFF + ch*CSI_CH_OFF, CSI_CH_VSIZE_REG_VER_START_MASK,
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start_v<<CSI_CH_VSIZE_REG_VER_START);
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}
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/* interrupt */
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void csi_int_enable(unsigned int sel, unsigned int ch, enum csi_int_sel interrupt)
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{
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vfe_reg_set(csi_base_addr[sel] + CSI_CH_INT_EN_REG_OFF + ch*CSI_CH_OFF, interrupt);
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}
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void csi_int_disable(unsigned int sel, unsigned int ch, enum csi_int_sel interrupt)
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{
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vfe_reg_clr(csi_base_addr[sel] + CSI_CH_INT_EN_REG_OFF + ch*CSI_CH_OFF, interrupt);
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}
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void csi_int_get_status(unsigned int sel, unsigned int ch,struct csi_int_status *status)
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{
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unsigned int reg_val = vfe_reg_readl(csi_base_addr[sel] + CSI_CH_INT_STA_REG_OFF + ch*CSI_CH_OFF);
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status->capture_done = (reg_val >> CSI_CH_INT_STA_REG_CD_PD)&0x1;
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status->frame_done = (reg_val >> CSI_CH_INT_STA_REG_FD_PD)&0x1;
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status->buf_0_overflow = (reg_val >> CSI_CH_INT_STA_REG_FIFO0_OF_PD)&0x1;
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status->buf_1_overflow = (reg_val >> CSI_CH_INT_STA_REG_FIFO1_OF_PD)&0x1;
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status->buf_2_overflow = (reg_val >> CSI_CH_INT_STA_REG_FIFO2_OF_PD)&0x1;
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status->protection_error = (reg_val >> CSI_CH_INT_STA_REG_PRTC_ERR_PD)&0x1;
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status->hblank_overflow = (reg_val >> CSI_CH_INT_STA_REG_HB_OF_PD)&0x1;
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status->vsync_trig = (reg_val >> CSI_CH_INT_STA_REG_VS_PD)&0x1;
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}
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void csi_int_clear_status(unsigned int sel, unsigned int ch, enum csi_int_sel interrupt)
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{
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//vfe_reg_clr_set(csi_base_addr[sel] + CSI_CH_INT_STA_REG_OFF + ch*CSI_CH_OFF, 0xffffffff,interrupt);
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vfe_reg_writel(csi_base_addr[sel] + CSI_CH_INT_STA_REG_OFF, interrupt);
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//vfe_reg_set(csi_base_addr[sel] + CSI_CH_INT_STA_REG_OFF + ch*CSI_CH_OFF, interrupt);
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}
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