429 lines
10 KiB
C
429 lines
10 KiB
C
/*
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* drivers/usb/sunxi_usb/usbc/usbc_phy.c
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* (C) Copyright 2010-2015
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* daniel, 2009.10.21
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*
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* usb common ops.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#include "usbc_i.h"
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/*
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* define USB PHY controller reg bit
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*/
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//Common Control Bits for Both PHYs
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#define USBC_PHY_PLL_BW 0x03
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#define USBC_PHY_RES45_CAL_EN 0x0c
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//Private Control Bits for Each PHY
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#define USBC_PHY_TX_AMPLITUDE_TUNE 0x20
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#define USBC_PHY_TX_SLEWRATE_TUNE 0x22
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#define USBC_PHY_VBUSVALID_TH_SEL 0x25
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#define USBC_PHY_PULLUP_RES_SEL 0x27
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#define USBC_PHY_OTG_FUNC_EN 0x28
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#define USBC_PHY_VBUS_DET_EN 0x29
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#define USBC_PHY_DISCON_TH_SEL 0x2a
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#if 0
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/*
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*
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* read out one bit of USB PHY register
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*/
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static __u32 __USBC_PHY_REG_READ(void __iomem *usbc_base_addr, __u32 usbc_phy_reg_addr)
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{
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__u32 reg_val = 0;
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__u32 i = 0;
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USBC_Writeb(usbc_phy_reg_addr, USBC_REG_PHYCTL(USBC0_REGS_BASE) + 1);
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for(i=0; i<0x4; i++);
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reg_val = USBC_Readb(USBC_REG_PHYCTL(USBC0_REGS_BASE) + 2);
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if (usbc_base_addr == USBC0_REGS_BASE)
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return (reg_val & 0x1);
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else
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return ((reg_val >> 1) & 0x1);
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}
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/*
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*
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* Write one bit of USB PHY register
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*/
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static void __USBC_PHY_REG_WRITE(void __iomem *usbc_base_addr, __u32 usbc_phy_reg_addr, __u32 usbc_phy_reg_data)
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{
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__u32 reg_val = 0;
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USBC_Writeb(usbc_phy_reg_addr, USBC_REG_PHYCTL(USBC0_REGS_BASE) + 1);
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reg_val = USBC_Readb(USBC_REG_PHYCTL(USBC0_REGS_BASE));
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reg_val &= ~(0x1 << 7);
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reg_val |= (usbc_phy_reg_data & 0x1) << 7;
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if (usbc_base_addr == USBC0_REGS_BASE) {
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reg_val &= ~0x1;
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USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE));
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reg_val |= 0x1;
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USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE));
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reg_val &= ~0x1;
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USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE));
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} else {
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reg_val &= ~0x2;
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USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE));
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reg_val |= 0x2;
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USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE));
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reg_val &= ~0x2;
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USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE));
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}
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}
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/*
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* Set USB PLL BandWidth, val = 0~3, defualt = 0x2
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*/
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/*
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static void __USBC_PHY_SET_PLL_BW(__u32 val)
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{
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__USBC_PHY_REG_WRITE(USBC0_REGS_BASE, USBC_PHY_PLL_BW, val);
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__USBC_PHY_REG_WRITE(USBC0_REGS_BASE, USBC_PHY_PLL_BW + 1, val >> 1);
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}
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*/
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/*
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* Enable/Disable USB res45 Calibration, val = 0--Disable；1--Enable, default = 0
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*/
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static void __USBC_PHY_RES45_CALIBRATION_ENABLE(__u32 val)
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{
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__USBC_PHY_REG_WRITE(USBC0_REGS_BASE, USBC_PHY_RES45_CAL_EN, val);
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}
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/*
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* Set USB TX Signal Amplitude, val = 0~3, default = 0x0
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*/
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static void __USBC_PHY_SET_TX_AMPLITUDE(void __iomem* usbc_base_addr, __u32 val)
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{
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_AMPLITUDE_TUNE, val);
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_AMPLITUDE_TUNE + 1, val >> 1);
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}
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/*
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* Set USB TX Signal Slew Rate, val = 0~7, default = 0x5
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*/
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static void __USBC_PHY_SET_TX_SLEWRATE(void __iomem* usbc_base_addr, __u32 val)
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{
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_SLEWRATE_TUNE, val);
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_SLEWRATE_TUNE + 1, val >> 1);
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_SLEWRATE_TUNE + 2, val >> 2);
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}
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/*
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* Set USB VBUS Valid Threshold, val = 0~3, default = 2
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*/
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/*
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static void __USBC_PHY_SET_VBUS_VALID_THRESHOLD(void __iomem* usbc_base_addr, __u32 val)
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{
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_VBUSVALID_TH_SEL, val);
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_VBUSVALID_TH_SEL + 1, val >> 1);
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}
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*/
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/*
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* Enable/Diasble USB OTG Function, val = 0--Disable；1--Enable, default = 1
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*/
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/*
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static void __USBC_PHY_OTG_FUNC_ENABLE(void __iomem* usbc_base_addr, __u32 val)
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{
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_OTG_FUNC_EN, val);
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}
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*/
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/*
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* Enable/Diasble USB VBUS Detect Function, val = 0--Disable；1--Enable, default = 1
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*/
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/*
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static void __USBC_PHY_VBUS_DET_ENABLE(void __iomem* usbc_base_addr, __u32 val)
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{
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_VBUS_DET_EN, val);
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}
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*/
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/*
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* Set USB Disconnect Detect Threshold, val = 0~3, default = 1
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*/
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static void __USBC_PHY_SET_DISCON_DET_THRESHOLD(void __iomem* usbc_base_addr, __u32 val)
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{
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_DISCON_TH_SEL, val);
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__USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_DISCON_TH_SEL + 1, val >> 1);
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}
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#endif
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/* usb PHY common set, initialize */
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void USBC_PHY_SetCommonConfig(void)
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{
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//__USBC_PHY_RES45_CALIBRATION_ENABLE(1);
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}
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/* usb PHY specific set
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* @hUSB: handle returned by USBC_open_otg, include some key data that the USBC need.
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*
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*/
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void USBC_PHY_SetPrivateConfig(__hdle hUSB)
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{
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//__usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
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//
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//if (usbc_otg == NULL) {
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// return ;
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//}
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//
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//USBC_REG_set_bit_l(0, USBC_REG_PHYTUNE(usbc_otg->base_addr));
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//USBC_REG_set_bit_l(7, USBC_REG_PHYTUNE(usbc_otg->base_addr));
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//USBC_REG_set_bit_l(6, USBC_REG_PHYTUNE(usbc_otg->base_addr));
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//USBC_REG_set_bit_l(5, USBC_REG_PHYTUNE(usbc_otg->base_addr));
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//USBC_REG_set_bit_l(4, USBC_REG_PHYTUNE(usbc_otg->base_addr));
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////__USBC_PHY_SET_TX_AMPLITUDE(usbc_otg->base_addr, 2);
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////__USBC_PHY_SET_TX_SLEWRATE(usbc_otg->base_addr, 6);
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////__USBC_PHY_SET_DISCON_DET_THRESHOLD(usbc_otg->base_addr, 3);
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}
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/* get PHY's common setting. for debug, to see if PHY is set correctly.
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*
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* return the 32bit usb PHY common setting value.
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*/
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__u32 USBC_PHY_GetCommonConfig(void)
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{
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__u32 reg_val = 0;
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/*
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__u32 i = 0;
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reg_val = 0;
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for(i=0; i<0x20; i++)
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{
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reg_val = reg_val << 1;
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reg_val |= __USBC_PHY_REG_READ(USBC0_REGS_BASE, (0x1f - i)) & 0x1;
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}
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*/
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return reg_val;
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}
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/* write usb PHY0's phy reg setting. mainly for phy0 standby.
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*
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* return the data wrote
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*/
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static __u32 usb_phy0_write(__u32 addr, __u32 data, __u32 dmask, void __iomem *usbc_base_addr)
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{
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__u32 i=0;
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data = data & 0x0f;
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addr = addr & 0x0f;
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dmask = dmask & 0x0f;
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USBC_Writeb((dmask<<4)|data, usbc_base_addr + 0x404 + 2);
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USBC_Writeb(addr|0x10, usbc_base_addr + 0x404);
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for(i=0;i<5;i++);
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USBC_Writeb(addr|0x30, usbc_base_addr + 0x404);
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for(i=0;i<5;i++);
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USBC_Writeb(addr|0x10, usbc_base_addr + 0x404);
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for(i=0;i<5;i++);
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return (USBC_Readb(usbc_base_addr + 0x404 + 3) & 0x0f);
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}
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/* Standby the usb phy with the input usb phy index number
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* @phy_index: usb phy index number, which used to select the phy to standby
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*
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*/
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void USBC_phy_Standby(__hdle hUSB, __u32 phy_index)
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{
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__usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
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if (phy_index == 0) {
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usb_phy0_write(0xB, 0x8, 0xf, usbc_otg->base_addr);
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usb_phy0_write(0x7, 0xf, 0xf, usbc_otg->base_addr);
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usb_phy0_write(0x1, 0xf, 0xf, usbc_otg->base_addr);
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usb_phy0_write(0x2, 0xf, 0xf, usbc_otg->base_addr);
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}
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return;
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}
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/* Recover the standby phy with the input index number
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* @phy_index: usb phy index number
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*
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*/
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void USBC_Phy_Standby_Recover(__hdle hUSB, __u32 phy_index)
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{
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__u32 i;
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if (phy_index == 0) {
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for(i=0; i<0x10; i++);
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}
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return;
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}
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#if 0
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static __u32 USBC_Phy_TpRead(__u32 usbc_no, __u32 addr, __u32 len)
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{
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void __iomem *otgc_base = NULL;
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void __iomem *phyctl_val = NULL;
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__u32 temp = 0, ret = 0;
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__u32 i=0;
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__u32 j=0;
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otgc_base = get_otgc_vbase();
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if(otgc_base == NULL){
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return 0;
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}
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phyctl_val = otgc_base + USBPHYC_REG_o_PHYCTL;
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for(j = len; j > 0; j--)
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{
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/* set the bit address to be read */
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temp = USBC_Readl(phyctl_val);
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temp &= ~(0xff << 8);
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temp |= ((addr + j -1) << 8);
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USBC_Writel(temp, phyctl_val);
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for(i = 0; i < 0x4; i++);
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temp = USBC_Readl(phyctl_val);
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ret <<= 1;
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ret |= ((temp >> (16 + usbc_no)) & 0x1);
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}
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return ret;
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}
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#endif
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static __u32 USBC_Phy_TpWrite(__u32 usbc_no, __u32 addr, __u32 data, __u32 len)
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{
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void __iomem *otgc_base = NULL;
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void __iomem *phyctl_val = NULL;
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__u32 temp = 0, dtmp = 0;
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__u32 j=0;
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otgc_base = get_otgc_vbase();
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if(otgc_base == NULL){
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return 0;
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}
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phyctl_val = otgc_base + USBPHYC_REG_o_PHYCTL;
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dtmp = data;
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for(j = 0; j < len; j++)
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{
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/* set the bit address to be write */
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temp = USBC_Readl(phyctl_val);
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temp &= ~(0xff << 8);
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temp |= ((addr + j) << 8);
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USBC_Writel(temp, phyctl_val);
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temp = USBC_Readb(phyctl_val);
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temp &= ~(0x1 << 7);
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temp |= (dtmp & 0x1) << 7;
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temp &= ~(0x1 << (usbc_no << 1));
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USBC_Writeb(temp, phyctl_val);
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temp = USBC_Readb(phyctl_val);
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temp |= (0x1 << (usbc_no << 1));
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USBC_Writeb( temp, phyctl_val);
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temp = USBC_Readb(phyctl_val);
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temp &= ~(0x1 << (usbc_no <<1 ));
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USBC_Writeb(temp, phyctl_val);
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dtmp >>= 1;
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}
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return data;
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}
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#if 0
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static __u32 USBC_Phy_Read(__u32 usbc_no, __u32 addr, __u32 len)
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{
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return USBC_Phy_TpRead(usbc_no, addr, len);
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}
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#endif
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static __u32 USBC_Phy_Write(__u32 usbc_no, __u32 addr, __u32 data, __u32 len)
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{
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return USBC_Phy_TpWrite(usbc_no, addr, data, len);
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}
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void UsbPhyCtl(void __iomem *regs)
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{
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__u32 reg_val = 0;
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reg_val = USBC_Readl(regs + USBPHYC_REG_o_PHYCTL);
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reg_val |= (0x01 << USBC_PHY_CTL_VBUSVLDEXT);
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USBC_Writel(reg_val, (regs + USBPHYC_REG_o_PHYCTL));
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return;
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}
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void USBC_PHY_Set_Ctl(void __iomem *regs, __u32 mask)
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{
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__u32 reg_val = 0;
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reg_val = USBC_Readl(regs + USBPHYC_REG_o_PHYCTL);
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reg_val |= (0x01 << mask);
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USBC_Writel(reg_val, (regs + USBPHYC_REG_o_PHYCTL));
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return;
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}
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void USBC_PHY_Clear_Ctl(void __iomem *regs, __u32 mask)
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{
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__u32 reg_val = 0;
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reg_val = USBC_Readl(regs + USBPHYC_REG_o_PHYCTL);
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reg_val &= ~(0x01 << mask);
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USBC_Writel(reg_val, (regs + USBPHYC_REG_o_PHYCTL));
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return;
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}
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void UsbPhyInit(__u32 usbc_no)
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{
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/* adjust the 45 ohm resistor */
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if (usbc_no == 0) {
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USBC_Phy_Write(usbc_no, 0x0c, 0x01, 1);
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}
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/* adjust USB0 PHY range and rate */
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USBC_Phy_Write(usbc_no, 0x20, 0x14, 5);
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/* adjust disconnect threshold */
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USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
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/*by wangjx*/
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return;
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}
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void UsbPhyEndReset(__u32 usbc_no)
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{
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int i;
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if (usbc_no == 0) {
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//Disable Sequelch Detect for a while before Release USB Reset
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USBC_Phy_Write(usbc_no, 0x3c, 0x2, 2);
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for(i=0; i<0x100; i++);
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USBC_Phy_Write(usbc_no, 0x3c, 0x0, 2);
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}
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return;
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}
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void usb_otg_phy_txtune(void __iomem *regs)
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{
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__u32 reg_val = 0;
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reg_val = USBC_Readl(regs + USBC_REG_o_PHYTUNE);
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reg_val |= 0x03 << 2; /* TXRESTUNE */
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reg_val &= ~(0xf << 8);
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reg_val |= 0xc << 8; /* TXVREFTUNE */
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USBC_Writel(reg_val, (regs + USBC_REG_o_PHYTUNE));
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}
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