405 lines
10 KiB
C
Executable file
405 lines
10 KiB
C
Executable file
/*
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* linux-3.10/drivers/char/sunxi_tr/sun50iw1_transform.c
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*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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//*********************************************************************************************************************
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// All Winner Tech, All Right Reserved. 2014-2015 Copyright (c)
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//
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// File name : de_tr.c
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//
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// Description : display engine 2.0 transform processing base functions implement
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//
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// History : 2014/04/08 iptang v0.1 Initial version
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//
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//*********************************************************************************************************************
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#include "transform.h"
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#define TR_OFFSET 0x00020000
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#define TR_CTL (0x000)
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#define TR_IRQ (0x004)
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#define TR_IN_FMT (0x020)
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#define TR_IN_SIZE (0x024)
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#define TR_IN_PITCH0 (0x030)
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#define TR_IN_PITCH1 (0x034)
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#define TR_IN_PITCH2 (0x038)
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#define TR_IN_LADDR0 (0x040)
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#define TR_IN_LADDR1 (0x048)
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#define TR_IN_LADDR2 (0x050)
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#define TR_IN_HADDR0 (0x044)
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#define TR_IN_HADDR1 (0x04c)
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#define TR_IN_HADDR2 (0x054)
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#define TR_OUT_FMT (0x080)
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#define TR_OUT_SIZE (0x084)
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#define TR_OUT_PITCH0 (0x090)
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#define TR_OUT_PITCH1 (0x094)
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#define TR_OUT_PITCH2 (0x098)
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#define TR_OUT_LADDR0 (0x0a0)
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#define TR_OUT_LADDR1 (0x0a8)
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#define TR_OUT_LADDR2 (0x0b0)
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#define TR_OUT_HADDR0 (0x0a4)
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#define TR_OUT_HADDR1 (0x0ac)
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#define TR_OUT_HADDR2 (0x0b4)
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static uintptr_t tr_base;
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#define tr_writel(val, addr) writel(val, (void __iomem *)(addr))
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#define tr_readl(addr) readl((void __iomem *)(addr))
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int de_tr_set_base(uintptr_t reg_base)
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{
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tr_base = reg_base + TR_OFFSET;
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return 0;
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}
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int de_tr_irq_enable(void)
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{
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tr_writel(1<<16, tr_base + TR_IRQ);
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return 0;
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}
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int de_tr_irq_disable(void)
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{
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tr_writel(0, tr_base + TR_IRQ);
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return 0;
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}
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/* */
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int de_tr_irq_query(void)
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{
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unsigned int irq_flag;
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unsigned reg_val = 0;
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reg_val = tr_readl(tr_base + TR_IRQ);
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irq_flag = reg_val&0x1;
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if(0x1 == irq_flag) {
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tr_writel(reg_val, tr_base + TR_IRQ);
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return 0;
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}
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return -1;
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}
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static int de_tr_clk_enable(void)
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{
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uintptr_t base = tr_base - TR_OFFSET;
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unsigned int reg_val = 0;
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unsigned int offset = 3;//bit 3
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/* clk div */
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reg_val = tr_readl(base + 0xc);
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reg_val &= ~(0xf << 12);
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reg_val |= (0x0 << 12);
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tr_writel(reg_val, base + 0xc);
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/* reset */
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reg_val = tr_readl(base + 0x8);
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reg_val |= (1<<offset);
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tr_writel(reg_val, base + 0x8);
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/* bus */
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reg_val = tr_readl(base + 0x4);
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reg_val |= (1<<offset);
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tr_writel(reg_val, base + 0x4);
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/* module */
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reg_val = tr_readl(base + 0x0);
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reg_val |= (1<<offset);
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tr_writel(reg_val, base + 0x0);
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return 0;
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}
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static int de_tr_clk_disable(void)
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{
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uintptr_t base = tr_base - TR_OFFSET;
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unsigned int reg_val = 0;
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unsigned int offset = 3;//bit 3
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/* module */
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reg_val = tr_readl(base + 0x0);
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reg_val &= ~(1<<offset);
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tr_writel(reg_val, base + 0x0);
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/* bus */
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reg_val = tr_readl(base + 0x4);
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reg_val &= ~(1<<offset);
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tr_writel(reg_val, base + 0x4);
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/* reset */
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reg_val = tr_readl(base + 0x8);
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reg_val &= ~(1<<offset);
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tr_writel(reg_val, base + 0x8);
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return 0;
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}
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static int de_tr_set_enable(void)
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{
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unsigned int tmp;
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tmp = tr_readl(tr_base + TR_CTL);
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tr_writel((1<<31)|tmp,tr_base + TR_CTL);
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return 0;
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}
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static int de_tr_set_disable(void)
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{
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//when rst need read de top register
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tr_readl(tr_base - TR_OFFSET);
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de_tr_irq_disable();
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return 0;
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}
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int de_tr_init(void)
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{
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return de_tr_clk_enable();
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}
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int de_tr_exit(void)
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{
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de_tr_set_disable();
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de_tr_clk_disable();
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return 0;
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}
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int de_tr_reset(void)
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{
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uintptr_t base = tr_base - TR_OFFSET;
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unsigned int reg_val = 0;
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unsigned int offset = 3;//bit 3
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tr_readl(tr_base - TR_OFFSET);
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reg_val = tr_readl(tr_base + TR_CTL);
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reg_val |= 0x1;//enable bit
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tr_writel(reg_val,tr_base + TR_CTL);
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/* assert */
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reg_val = tr_readl(base + 0x8);
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reg_val &= ~(1<<offset);
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tr_writel(reg_val, base + 0x8);
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udelay(10);//wait for reset finish
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/* de-assert */
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reg_val = tr_readl(base + 0x8);
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reg_val |= (1<<offset);
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tr_writel(reg_val, base + 0x8);
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return 0;
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}
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int de_tr_exception(void)
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{
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mdelay(100);//wait to finish
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return 0;
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}
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int de_tr_set_cfg(tr_info *info)
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{
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int x0,x1,y0,y1;
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unsigned char haddr[3],degree,hflip_en,vflip_en,burst;
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unsigned int w,h,fmt,ycnt = 4,ucnt = 0,tmp,pitch[3];
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long long addr[3];
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de_tr_reset();
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//global
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burst = 0x7;
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degree = hflip_en = vflip_en = 0x0;
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if (info->mode<=TR_ROT_270)
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{
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degree = info->mode;
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}
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else if ((info->mode == TR_HFLIP) || (info->mode == TR_HFLIP_ROT_90))
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{
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hflip_en = 0x1;
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}
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else if ((info->mode == TR_VFLIP) || (info->mode == TR_VFLIP_ROT_90))
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{
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vflip_en = 0x1;
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}
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if ((info->mode == TR_HFLIP_ROT_90) || (info->mode == TR_VFLIP_ROT_90))
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{
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degree = 0x1;
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}
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if((info->mode == TR_ROT_0) || (info->mode == TR_ROT_180) || (info->mode == TR_HFLIP) || (info->mode == TR_VFLIP))
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{
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burst = 0x3f;
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}
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tmp = (burst<<16)|(hflip_en<<7)|(vflip_en<<6)|(degree<<4)|(1<<0);
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tr_writel(tmp,tr_base + TR_CTL);
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x0 = x1 = info->src_rect.x;
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y0 = y1 = info->src_rect.y;
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w = info->src_rect.w;
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h = info->src_rect.h;
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fmt = info->src_frame.fmt;
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if (fmt<=TR_FORMAT_BGRX_8888) {ycnt = 4;}
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else if (fmt<=TR_FORMAT_BGR_888) {ycnt = 3;}
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else if (fmt<=TR_FORMAT_BGRA_5551) {ycnt = 2;}
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else if (fmt<=TR_FORMAT_YUV422_I_VYUY) {ycnt = 2;ucnt=0;}
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else if (fmt==TR_FORMAT_YUV422_P) {ycnt = 1;ucnt=1; x1=x0/2;y1=y0;} //YUV422
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else if (fmt==TR_FORMAT_YUV420_P) {ycnt = 1;ucnt=1; x1=x0/2;y1=y0/2;}//YUV420
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else if (fmt==TR_FORMAT_YUV411_P) {ycnt = 1;ucnt=1; x1=x0/4;y1=y0;} //YUV411
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else if (fmt<=TR_FORMAT_YUV422_SP_VUVU){ycnt = 1;ucnt=2; x1=x0/2;y1=y0;}
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else if (fmt<=TR_FORMAT_YUV420_SP_VUVU){ycnt = 1;ucnt=2; x1=x0/2;y1=y0/2;}
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else if (fmt<=TR_FORMAT_YUV411_SP_VUVU){ycnt = 1;ucnt=2; x1=x0/4;y1=y0;}
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else {ycnt = 4;}
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pitch[0] = info->src_frame.pitch[0] * ycnt;
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pitch[1] = info->src_frame.pitch[1] * ucnt;
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pitch[2] = info->src_frame.pitch[2] * ucnt;
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if((0 != x0) ||(0 != y0)){
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pr_warn("In buffer coordinate is not original point[%d,%d].\n", x0, y0);
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return -1;
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}
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if((pitch[0]&0xf) ||(pitch[1]&0xf)||(pitch[2]&0xf)){
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pr_warn("In buffer pitch is not 16 byte align[%x,%x,%x].\n",
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pitch[0],pitch[1],pitch[2]);
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return -1;
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}
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addr[0] = info->src_frame.laddr[0]+pitch[0]*y0+x0*ycnt;//Y/ARGB
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addr[1] = info->src_frame.laddr[1]+pitch[1]*y1+x1*ucnt;//UV/U
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addr[2] = info->src_frame.laddr[2]+pitch[2]*y1+x1*ucnt;//V
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haddr[0] = ((addr[0]>>32)&0xff) + info->src_frame.haddr[0];
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haddr[1] = ((addr[1]>>32)&0xff) + info->src_frame.haddr[1];
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haddr[2] = ((addr[2]>>32)&0xff) + info->src_frame.haddr[2];
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if(fmt >= TR_FORMAT_YUV444_I_AYUV) {
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if((addr[0]&0xf) ||(addr[1]&0xf)||(addr[2]&0xf)){
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pr_warn("Input address is not 16 byte align.\n");
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return -1;
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}
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}
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w = w==0?0:w-1;
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h = h==0?0:h-1;
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tr_writel((h<<16)|w,tr_base + TR_IN_SIZE);
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tr_writel(pitch[0],tr_base + TR_IN_PITCH0);
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tr_writel(pitch[1],tr_base + TR_IN_PITCH1);
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tr_writel(pitch[2],tr_base + TR_IN_PITCH2);
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tr_writel(addr[0]&0xffffffff,tr_base + TR_IN_LADDR0);
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tr_writel(addr[1]&0xffffffff,tr_base + TR_IN_LADDR1);
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tr_writel(addr[2]&0xffffffff,tr_base + TR_IN_LADDR2);
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tr_writel(haddr[0],tr_base + TR_IN_HADDR0);
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tr_writel(haddr[1],tr_base + TR_IN_HADDR1);
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tr_writel(haddr[2],tr_base + TR_IN_HADDR2);
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//dst
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x0 = info->dst_rect.x;
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y0 = info->dst_rect.y;
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w = info->dst_rect.w;
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h = info->dst_rect.h;
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//for ycbcr format output only support yv12
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if(fmt >= TR_FORMAT_YUV444_I_AYUV) {
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ycnt = 1;ucnt=1; x1=x0/2;y1=y0/2;
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}
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pitch[0] = info->dst_frame.pitch[0] * ycnt;
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pitch[1] = info->dst_frame.pitch[1] * ucnt;
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pitch[2] = info->dst_frame.pitch[2] * ucnt;
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if(fmt >= TR_FORMAT_YUV444_I_AYUV) {
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if((pitch[0]&0xf) ||(pitch[1]&0xf)||(pitch[2]&0xf)){
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pr_warn("Out buffer pitch is not 16 byte align[%x,%x,%x].\n",
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pitch[0],pitch[1],pitch[2]);
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return -1;
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}
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}
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if((0 != x0) ||(0 != y0)){
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pr_warn("Out buffer coordinate is not original point[%d,%d].\n", x0, y0);
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return -1;
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}
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addr[0] = info->dst_frame.laddr[0]+pitch[0]*y0+x0*ycnt;//Y/ARGB
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addr[1] = info->dst_frame.laddr[1]+pitch[1]*y1+x1*ucnt;//UV/U
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addr[2] = info->dst_frame.laddr[2]+pitch[2]*y1+x1*ucnt;//V
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haddr[0] = ((addr[0]>>32)&0xff) + info->dst_frame.haddr[0];
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haddr[1] = ((addr[1]>>32)&0xff) + info->dst_frame.haddr[1];
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haddr[2] = ((addr[2]>>32)&0xff) + info->dst_frame.haddr[2];
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if(fmt >= TR_FORMAT_YUV444_I_AYUV) {
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if((addr[0]&0x1f) ||(addr[1]&0x1f)||(addr[2]&0x1f)){
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pr_warn("Output address is not 32 byte align.\n");
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return -1;
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}
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}
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w = w==0?0:w-1;
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h = h==0?0:h-1;
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tr_writel((h<<16)|w,tr_base + TR_OUT_SIZE);
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tr_writel(pitch[0],tr_base + TR_OUT_PITCH0);
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tr_writel(pitch[1],tr_base + TR_OUT_PITCH1);
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tr_writel(pitch[2],tr_base + TR_OUT_PITCH2);
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tr_writel(addr[0]&0xffffffff,tr_base + TR_OUT_LADDR0);
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tr_writel(addr[1]&0xffffffff,tr_base + TR_OUT_LADDR1);
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tr_writel(addr[2]&0xffffffff,tr_base + TR_OUT_LADDR2);
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tr_writel(haddr[0],tr_base + TR_OUT_HADDR0);
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tr_writel(haddr[1],tr_base + TR_OUT_HADDR1);
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tr_writel(haddr[2],tr_base + TR_OUT_HADDR2);
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//src
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if (TR_FORMAT_YUV422_I_VYUY == info->src_frame.fmt){fmt = 0x20;}
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else if (TR_FORMAT_YUV422_I_YVYU == info->src_frame.fmt){fmt = 0x21;}
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else if (TR_FORMAT_YUV422_I_UYVY == info->src_frame.fmt){fmt = 0x22;}
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else if (TR_FORMAT_YUV422_I_YUYV == info->src_frame.fmt){fmt = 0x23;}
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else if (TR_FORMAT_YUV422_SP_UVUV == info->src_frame.fmt){fmt = 0x24;}
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else if (TR_FORMAT_YUV422_SP_VUVU == info->src_frame.fmt){fmt = 0x25;}
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else if (TR_FORMAT_YUV422_P == info->src_frame.fmt){fmt = 0x26;}
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else if (TR_FORMAT_YUV420_SP_UVUV == info->src_frame.fmt){fmt = 0x28;}
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else if (TR_FORMAT_YUV420_SP_VUVU == info->src_frame.fmt){fmt = 0x29;}
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else if (TR_FORMAT_YUV420_P == info->src_frame.fmt){fmt = 0x2a;}
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else if (TR_FORMAT_YUV411_SP_UVUV == info->src_frame.fmt){fmt = 0x2c;}
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else if (TR_FORMAT_YUV411_SP_VUVU == info->src_frame.fmt){fmt = 0x2d;}
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else if (TR_FORMAT_YUV411_P == info->src_frame.fmt){fmt = 0x2e;}
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else {fmt = info->src_frame.fmt;}
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// else {fmt = 0x0;}
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tr_writel(fmt,tr_base + TR_IN_FMT);
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de_tr_irq_enable();
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de_tr_set_enable();
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return 0;
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}
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