115 lines
2.9 KiB
C
115 lines
2.9 KiB
C
/*
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* Copyright (c) 2011-2020 yanggq.young@allwinnertech.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include "pm_types.h"
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#include "pm_i.h"
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static void *pio_pbase;
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static u32 pio_len;
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/*
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*********************************************************************************************************
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* MEM gpio INITIALISE
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*
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* Description: mem gpio initialise.
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*
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* Arguments : none.
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*
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* Returns : 0/-1;
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*********************************************************************************************************
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*/
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__s32 mem_gpio_init(void)
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{
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u32 *base = 0;
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pm_get_dev_info("pio", 0, &base, &pio_len);
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pio_pbase = base;
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return 0;
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}
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/*
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*********************************************************************************************************
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* MEM gpio INITIALISE
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*
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* Description: mem gpio initialise.
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*
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* Arguments : none.
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*
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* Returns : 0/-1;
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*********************************************************************************************************
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*/
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__s32 mem_gpio_save(struct gpio_state *pgpio_state)
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{
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int i = 0;
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/*save all the gpio reg */
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for (i = 0; i < (GPIO_REG_LENGTH); i++) {
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pgpio_state->gpio_reg_back[i] =
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*(volatile __u32 *)((pio_pbase) + i * 0x04);
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}
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return 0;
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}
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/*
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*********************************************************************************************************
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* MEM gpio INITIALISE
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*
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* Description: mem gpio initialise.
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*
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* Arguments : none.
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*
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* Returns : 0/-1;
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*********************************************************************************************************
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*/
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__s32 mem_gpio_restore(struct gpio_state *pgpio_state)
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{
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int i = 0;
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/*restore all the gpio reg */
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for (i = 0; i < (GPIO_REG_LENGTH); i++) {
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*(volatile __u32 *)((pio_pbase) + i * 0x04) =
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pgpio_state->gpio_reg_back[i];
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}
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#ifdef CONFIG_ARCH_SUN8IW1P1
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/* restore watch-dog registers, to avoid IC's bug */
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*(volatile __u32 *)IO_ADDRESS(0x1C20CD8) = 0;
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*(volatile __u32 *)IO_ADDRESS(0x1C20CF8) = 0;
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*(volatile __u32 *)IO_ADDRESS(0x1C20D18) = 0;
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#endif
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return 0;
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}
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#if defined(CONFIG_ARCH_SUN9IW1P1) || defined(CONFIG_ARCH_SUN8IW6P1) || defined(CONFIG_ARCH_SUN8IW8P1)
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void config_gpio_clk(__u32 mmu_flag)
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{
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static __u32 gpio_clk_inited;
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__u32 gpio_apb0_gating_reg = 0;
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if (0 == gpio_clk_inited) {
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if (mmu_flag) {
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gpio_apb0_gating_reg =
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(__u32) (IO_ADDRESS
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(AW_CCM_MOD_BASE +
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AW_CCM_PIO_BUS_GATE_REG_OFFSET));
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} else {
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gpio_apb0_gating_reg =
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(__u32) ((AW_CCM_MOD_BASE +
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AW_CCM_PIO_BUS_GATE_REG_OFFSET));
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}
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/*first: release gpio gating, then u can opererate gpio. */
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writel(readl(gpio_apb0_gating_reg) | (0x1 << 5),
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gpio_apb0_gating_reg);
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gpio_clk_inited = 1;
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}
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return;
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}
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#endif
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