1.V1.0ֻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>FPGA coe<6F><65>IC<49><43><EFBFBD><EFBFBD><EFBFBD>ṩ<EFBFBD><E1B9A9>
2.<2E><><EFBFBD><EFBFBD>ˢ<EFBFBD>½ӿ<C2BD>dram_power_save_process
3.<2E><><EFBFBD><EFBFBD>ˢ<EFBFBD>½ӿ<C2BD>dram_power_up_process
4.<2E><><EFBFBD>ṩextern dram_para_t *dram_para;
extern dram_data_t dram_data;
<0A><><EFBFBD>粻<EFBFBD><E7B2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰstandby<62><79>Ա<EFBFBD><D4B1>
5.<2E><><EFBFBD>ṩus<75><73>timer<65><72><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD>udelay();