15 lines
383 B
Text
15 lines
383 B
Text
Calxeda Highbank L2 cache ECC
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Properties:
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- compatible : Should be "calxeda,hb-sregs-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt.
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Example:
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sregs@fff3c200 {
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compatible = "calxeda,hb-sregs-l2-ecc";
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reg = <0xfff3c200 0x100>;
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interrupts = <0 71 4 0 72 4>;
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};
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