209 lines
5 KiB
C
209 lines
5 KiB
C
/*
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* Device Tree support for Allwinner A1X SoCs
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/i2c.h>
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#include <linux/i2c/pcf857x.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include <linux/sys_config.h>
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#include <linux/pinctrl/pinconf-sunxi.h>
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#include <linux/of_gpio.h>
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#include "sunxi.h"
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static void __iomem *wdt_base;
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static void sun3i_restart(char mode, const char *cmd)
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{
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#define SUN3I_WATCHDOG_CTRL_REG 0x10
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#define SUN3I_WATCHDOG_CTRL_RESTART ((1 << 0) | 0xA57)
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#define SUN3I_WATCHDOG_CONFIG_REG 0x14
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#define SUN3I_WATCHDOG_CONFIG_WHOLE_SYS (1 << 0)
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#define SUN3I_WATCHDOG_MODE_REG 0x18
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#define SUN3I_WATCHDOG_MODE_ENABLE (1 << 0)
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if (!wdt_base)
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return;
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pr_debug("func:%s,para: mode=%s,cmd=%s\n", __func__, &mode, cmd);
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/* config watchdog reset whole system.*/
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writel(SUN3I_WATCHDOG_CONFIG_WHOLE_SYS,
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wdt_base + SUN3I_WATCHDOG_CONFIG_REG);
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/*
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* start the watchdog. The default (and lowest) interval
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* value for the watchdog is 0.5s.
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*/
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writel(SUN3I_WATCHDOG_MODE_ENABLE, wdt_base + SUN3I_WATCHDOG_MODE_REG);
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}
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static struct of_device_id sunxi_restart_ids[] = {
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{ .compatible = "allwinner,sun3i-wdt", .data = sun3i_restart },
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{ /*sentinel*/ }
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};
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static void sunxi_setup_restart(void)
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{
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const struct of_device_id *of_id;
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struct device_node *np;
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np = of_find_matching_node(NULL, sunxi_restart_ids);
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if (WARN(!np, "unable to setup watchdog restart"))
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return;
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wdt_base = of_iomap(np, 0);
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WARN(!wdt_base, "failed to map watchdog base address");
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of_id = of_match_node(sunxi_restart_ids, np);
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WARN(!of_id, "restart function not available");
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arm_pm_restart = of_id->data;
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}
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static struct map_desc sunxi_io_desc[] __initdata = {
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{
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.virtual = (unsigned long) IO_ADDRESS(SUNXI_IO_PBASE),
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.pfn = __phys_to_pfn(SUNXI_IO_PBASE),
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.length = SUNXI_IO_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init sunxi_map_io(void)
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{
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iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
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}
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static void __init sunxi_timer_init(void)
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{
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of_clk_init(NULL);
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#ifdef CONFIG_COMMON_CLK_ENABLE_SYNCBOOT_EARLY
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clk_syncboot();
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#endif
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clocksource_of_init();
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}
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#if defined(CONFIG_GPIO_PCF857X) || defined(CONFIG_GPIO_PCF857X_MODULE)
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static struct pcf857x_platform_data pcf857x_data[] = {
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{
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.gpio_base = IO_EXP_PIN_BASE,
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}, {
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}
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};
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static struct i2c_board_info sunxi_i2c0_devices[] = {
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{
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I2C_BOARD_INFO("pcf8574a", 0x20),
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.platform_data = &pcf857x_data[0],
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}, {
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},
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};
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#endif
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static void sunxi_power_off(void)
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{
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struct device_node *node = NULL;
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struct gpio_config config;
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char pin_name[128] = {0};
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int cfg_val = 0;
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int gpio = 0;
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int ret = -1;
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node = of_find_node_by_type(NULL, "power_ctrl");
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if (NULL == node) {
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pr_err("%s: fail to find power_ctrl node\n", __func__);
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return;
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}
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gpio = of_get_named_gpio_flags(node, "power_on",
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0, (enum of_gpio_flags *)&config);
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if (!gpio_is_valid(gpio))
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return;
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ret = gpio_request(config.gpio, NULL);
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if (0 != ret) {
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pr_err("%s: reques gpio=%d fail, ret=%d\n",
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__func__, config.gpio, ret);
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return;
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}
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sunxi_gpio_to_name(config.gpio, pin_name);
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cfg_val = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, config.mul_sel);
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pin_config_set(SUNXI_PINCTRL, pin_name, cfg_val);
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if (config.pull != GPIO_PULL_DEFAULT) {
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cfg_val = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, config.pull);
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pin_config_set(SUNXI_PINCTRL, pin_name, cfg_val);
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}
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if (config.drv_level != GPIO_DRVLVL_DEFAULT) {
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cfg_val = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV,
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config.drv_level);
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pin_config_set(SUNXI_PINCTRL, pin_name, cfg_val);
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}
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if (config.data != GPIO_DATA_DEFAULT) {
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cfg_val = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, config.data);
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pin_config_set(SUNXI_PINCTRL, pin_name, cfg_val);
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}
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gpio_free(config.gpio);
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return;
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}
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static void sunxi_power_off_prepare(void)
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{
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return;
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}
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static void __init sunxi_dt_init(void)
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{
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sunxi_setup_restart();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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#if defined(CONFIG_GPIO_PCF857X) || defined(CONFIG_GPIO_PCF857X_MODULE)
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/*add platform data to system*/
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i2c_register_board_info(0, sunxi_i2c0_devices,
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ARRAY_SIZE(sunxi_i2c0_devices));
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#endif
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if (!pm_power_off)
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pm_power_off = sunxi_power_off;
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if (!pm_power_off_prepare)
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pm_power_off_prepare = sunxi_power_off_prepare;
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}
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static const char * const sunxi_board_dt_compat[] = {
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"arm,sun3iw1p1",
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NULL,
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};
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DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
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.init_machine = sunxi_dt_init,
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.map_io = sunxi_map_io,
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.init_irq = irqchip_init,
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.init_time = sunxi_timer_init,
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.dt_compat = sunxi_board_dt_compat,
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MACHINE_END
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