528 lines
12 KiB
C
528 lines
12 KiB
C
/*
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* drivers/input/sensor/sunxi_gpadc.c
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*
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* Copyright (C) 2016 Allwinner.
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* fuzhaoke <fuzhaoke@allwinnertech.com>
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*
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* SUNXI GPADC Controller Driver
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <linux/timer.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/pm.h>
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#include "sunxi_gpadc.h"
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static struct sunxi_gpadc *p_sunxi_gpadc;
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/* clk_in: source clock, round_clk: sample rate */
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void sunxi_gpadc_sample_rate_set(void __iomem *reg_base, u32 clk_in, u32 round_clk)
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{
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u32 div, reg_val;
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if (round_clk > clk_in)
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pr_err("%s, invalid round clk!\n", __func__);
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div = clk_in / round_clk - 1 ;
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reg_val = readl(reg_base + GP_SR_REG);
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reg_val &= ~GP_SR_CON;
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reg_val |= (div << 16);
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writel(reg_val, reg_base + GP_SR_REG);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_sample_rate_set);
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void sunxi_gpadc_ctrl_set(void __iomem *reg_base, u32 ctrl_para)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_base + GP_CTRL_REG);
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reg_val |= ctrl_para;
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writel(reg_val, reg_base + GP_CTRL_REG);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_ctrl_set);
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static u32 __gpadc_ch_select(void __iomem *reg_base, enum gp_channel_id id)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_base + GP_CTRL_REG);
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switch (id) {
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case GP_CH_0:
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reg_val |= GP_CH0_SELECT;
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break;
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case GP_CH_1:
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reg_val |= GP_CH1_SELECT;
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break;
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case GP_CH_2:
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reg_val |= GP_CH2_SELECT;
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break;
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case GP_CH_3:
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reg_val |= GP_CH3_SELECT;
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break;
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default:
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pr_err("%s, invalid channel id!", __func__);
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return -EINVAL;
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}
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writel(reg_val, reg_base + GP_CTRL_REG);
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return 0;
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}
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u32 sunxi_gpadc_ch_select(struct sunxi_gpadc *p_sunxi_gpadc, enum gp_channel_id id)
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{
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int ret = 0;
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if (id >= GP_CH_MAX)
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return -EINVAL;
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spin_lock_irq(&p_sunxi_gpadc->gpadc_lock);
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if (!__gpadc_ch_select(p_sunxi_gpadc->reg_base, id))
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p_sunxi_gpadc->ch_open_cnt[id]++;
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else
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ret = -EINVAL;
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spin_unlock_irq(&p_sunxi_gpadc->gpadc_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_ch_select);
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static u32 __gpadc_ch_deselect(void __iomem *reg_base, enum gp_channel_id id)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_base + GP_CTRL_REG);
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switch (id) {
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case GP_CH_0:
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reg_val &= ~GP_CH0_SELECT;
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break;
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case GP_CH_1:
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reg_val &= ~GP_CH1_SELECT;
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break;
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case GP_CH_2:
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reg_val &= ~GP_CH2_SELECT;
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break;
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case GP_CH_3:
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reg_val &= ~GP_CH3_SELECT;
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break;
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default:
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pr_err("%s, invalid channel id!", __func__);
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return -EINVAL;
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}
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writel(reg_val, reg_base + GP_CTRL_REG);
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return 0;
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}
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u32 sunxi_gpadc_ch_deselect(struct sunxi_gpadc *p_sunxi_gpadc, enum gp_channel_id id)
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{
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if (id >= GP_CH_MAX)
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return -EINVAL;
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spin_lock_irq(&p_sunxi_gpadc->gpadc_lock);
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if (0 == --(p_sunxi_gpadc->ch_open_cnt[id]))
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__gpadc_ch_deselect(p_sunxi_gpadc->reg_base, id);
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spin_unlock_irq(&p_sunxi_gpadc->gpadc_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_ch_deselect);
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u32 sunxi_gpadc_ch_cmp(void __iomem *reg_base, enum gp_channel_id id, u32 low_uv, u32 hig_uv)
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{
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u32 reg_val = 0, low = 0, hig = 0, unit = 0;
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if ((low_uv > hig_uv) || (hig_uv > VOL_RANGE)) {
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pr_err("%s, invalid compare value!", __func__);
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return -EINVAL;
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}
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/* anolog voltage range 0~2.3v, 12bits sample rate, unit=2.3v/(2^12)=561uv */
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unit = VOL_RANGE / 4096; /* 12bits sample rate */
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low = low_uv / unit;
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hig = hig_uv / unit;
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reg_val = low + (hig << 16);
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switch (id) {
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case GP_CH_0:
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writel(reg_val, reg_base + GP_CH0_CMP_DATA_REG);
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break;
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case GP_CH_1:
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writel(reg_val, reg_base + GP_CH1_CMP_DATA_REG);
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break;
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case GP_CH_2:
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writel(reg_val, reg_base + GP_CH2_CMP_DATA_REG);
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break;
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case GP_CH_3:
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writel(reg_val, reg_base + GP_CH3_CMP_DATA_REG);
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break;
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default:
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pr_err("%s, invalid channel id!", __func__);
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return -EINVAL;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_ch_cmp);
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u32 __gpadc_cmp_select(void __iomem *reg_base, enum gp_channel_id id)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_base + GP_CTRL_REG);
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switch (id) {
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case GP_CH_0:
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reg_val |= GP_CH0_CMP_EN;
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break;
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case GP_CH_1:
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reg_val |= GP_CH1_CMP_EN;
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break;
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case GP_CH_2:
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reg_val |= GP_CH2_CMP_EN;
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break;
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case GP_CH_3:
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reg_val |= GP_CH3_CMP_EN;
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break;
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default:
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pr_err("%s, invalid value!", __func__);
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return -EINVAL;
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}
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writel(reg_val, reg_base + GP_CTRL_REG);
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return 0;
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}
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u32 sunxi_gpadc_cmp_select(struct sunxi_gpadc *p_sunxi_gpadc, enum gp_channel_id id)
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{
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int ret = 0;
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if (id >= GP_CH_MAX)
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return -EINVAL;
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spin_lock_irq(&p_sunxi_gpadc->gpadc_lock);
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if (!__gpadc_cmp_select(p_sunxi_gpadc->reg_base, id))
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p_sunxi_gpadc->ch_cmp_cnt[id]++;
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else
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ret = -EINVAL;
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spin_unlock_irq(&p_sunxi_gpadc->gpadc_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_cmp_select);
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u32 __gpadc_cmp_deselect(void __iomem *reg_base, enum gp_channel_id id)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_base + GP_CTRL_REG);
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switch (id) {
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case GP_CH_0:
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reg_val &= ~GP_CH0_CMP_EN;
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break;
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case GP_CH_1:
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reg_val &= ~GP_CH1_CMP_EN;
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break;
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case GP_CH_2:
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reg_val &= ~GP_CH2_CMP_EN;
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break;
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case GP_CH_3:
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reg_val &= ~GP_CH3_CMP_EN;
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break;
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default:
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pr_err("%s, invalid value!", __func__);
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return -EINVAL;
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}
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writel(reg_val, reg_base + GP_CTRL_REG);
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return 0;
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}
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u32 sunxi_gpadc_cmp_deselect(struct sunxi_gpadc *p_sunxi_gpadc, enum gp_channel_id id)
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{
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if (id >= GP_CH_MAX)
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return -EINVAL;
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spin_lock_irq(&p_sunxi_gpadc->gpadc_lock);
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if (0 == --(p_sunxi_gpadc->ch_cmp_cnt[id]))
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__gpadc_cmp_deselect(p_sunxi_gpadc->reg_base, id);
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spin_unlock_irq(&p_sunxi_gpadc->gpadc_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_cmp_deselect);
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u32 sunxi_gpadc_mode_select(void __iomem *reg_base, enum gp_select_mode mode)
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{
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u32 reg_val = 0;
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if (mode >= GP_NUM_MAX) {
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pr_err("%s invalid mode!\n", __func__);
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return -EINVAL;
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}
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reg_val = readl(reg_base + GP_CTRL_REG);
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reg_val &= ~GP_MODE_SELECT;
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reg_val |= (mode << 8);
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writel(reg_val, reg_base + GP_CTRL_REG);
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return 0;
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_mode_select);
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/* enable gpadc function, true:enable, false:disable */
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static void __gpadc_en(void __iomem *reg_base, bool onoff)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_base + GP_CTRL_REG);
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if (true == onoff)
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reg_val |= GP_ADC_EN;
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else
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reg_val &= ~GP_ADC_EN;
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writel(reg_val, reg_base + GP_CTRL_REG);
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}
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void sunxi_gpadc_en(struct sunxi_gpadc *p_sunxi_gpadc, bool onoff)
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{
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spin_lock_irq(&p_sunxi_gpadc->gpadc_lock);
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if (true == onoff) {
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__gpadc_en(p_sunxi_gpadc->reg_base, true);
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p_sunxi_gpadc->gpadc_en_cnt++;
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} else {
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if (0 == --(p_sunxi_gpadc->gpadc_en_cnt))
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__gpadc_en(p_sunxi_gpadc->reg_base, false);
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}
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spin_unlock_irq(&p_sunxi_gpadc->gpadc_lock);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_en);
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u32 sunxi_gpadc_int_cfg(void __iomem *reg_base)
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{
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return readl(reg_base + GP_INTC_REG);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_int_cfg);
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void sunxi_gpadc_int_set(void __iomem *reg_base, u32 int_para)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_base + GP_INTC_REG);
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reg_val |= int_para;
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writel(reg_val, reg_base + GP_INTC_REG);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_int_set);
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void sunxi_gpadc_int_clr(void __iomem *reg_base, u32 int_para)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_base + GP_INTC_REG);
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reg_val &= ~int_para;
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writel(reg_val, reg_base + GP_INTC_REG);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_int_clr);
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u32 sunxi_gpadc_read_ints(void __iomem *reg_base)
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{
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return readl(reg_base + GP_INTS_REG);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_read_ints);
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void sunxi_gpadc_clr_ints(void __iomem *reg_base, u32 int_para)
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{
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writel(int_para, reg_base + GP_INTS_REG);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_clr_ints);
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u32 sunxi_gpadc_read_data(void __iomem *reg_base, enum gp_channel_id id)
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{
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switch (id) {
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case GP_CH_0:
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return readl(reg_base + GP_CH0_DATA_REG) & GP_CH0_DATA_MASK;
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case GP_CH_1:
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return readl(reg_base + GP_CH1_DATA_REG) & GP_CH1_DATA_MASK;
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case GP_CH_2:
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return readl(reg_base + GP_CH2_DATA_REG) & GP_CH2_DATA_MASK;
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case GP_CH_3:
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return readl(reg_base + GP_CH3_DATA_REG) & GP_CH3_DATA_MASK;
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default:
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pr_err("%s, invalid channel id!", __func__);
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return -EINVAL;
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}
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_read_data);
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/* only low 12bit valid */
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void sunxi_gpadc_set_calibration(void __iomem *reg_base, u16 cali_val)
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{
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writel(cali_val & 0xfff, reg_base + GP_CB_DATA_REG);
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_set_calibration);
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struct sunxi_gpadc *sunxi_gpadc_get_handler(void)
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{
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return p_sunxi_gpadc;
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}
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EXPORT_SYMBOL_GPL(sunxi_gpadc_get_handler);
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int sunxi_gpadc_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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int ret = 0;
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if (!of_device_is_available(np)) {
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pr_err("%s: sunxi gpadc is disable\n", __func__);
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return -EPERM;
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}
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p_sunxi_gpadc = kzalloc(sizeof(struct sunxi_gpadc), GFP_KERNEL);
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if (IS_ERR_OR_NULL(p_sunxi_gpadc)) {
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pr_err("not enough memory for sunxi_gpadc\n");
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return -ENOMEM;
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}
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p_sunxi_gpadc->reg_base = of_iomap(np, 0);
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if (NULL == p_sunxi_gpadc->reg_base) {
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pr_err("sunxi_gpadc iomap fail\n");
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ret = -EBUSY;
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goto eiomap;
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}
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p_sunxi_gpadc->irq_num = irq_of_parse_and_map(np, 0);
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if (0 == p_sunxi_gpadc->irq_num) {
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pr_err("sunxi_gpadc fail to map irq\n");
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ret = -EBUSY;
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goto eirq;
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}
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p_sunxi_gpadc->mclk = of_clk_get(np, 0);
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if (IS_ERR_OR_NULL(p_sunxi_gpadc->mclk)) {
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pr_err("sunxi_gpadc has no clk\n");
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ret = -EINVAL;
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goto eclk;
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} else{
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if (clk_prepare_enable(p_sunxi_gpadc->mclk)) {
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pr_err("enable sunxi_gpadc clock failed!\n");
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ret = -EINVAL;
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goto eclk;
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}
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}
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platform_set_drvdata(pdev, p_sunxi_gpadc);
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spin_lock_init(&p_sunxi_gpadc->gpadc_lock);
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return 0;
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eclk:
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free_irq(p_sunxi_gpadc->irq_num, p_sunxi_gpadc);
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eirq:
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iounmap(p_sunxi_gpadc->reg_base);
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eiomap:
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kfree(p_sunxi_gpadc);
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return ret;
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}
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int sunxi_gpadc_remove(struct platform_device *pdev)
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{
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struct sunxi_gpadc *p_sunxi_gpadc = platform_get_drvdata(pdev);
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sunxi_gpadc_en(p_sunxi_gpadc->reg_base, false);
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free_irq(p_sunxi_gpadc->irq_num, p_sunxi_gpadc);
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clk_disable_unprepare(p_sunxi_gpadc->mclk);
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iounmap(p_sunxi_gpadc->reg_base);
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kfree(p_sunxi_gpadc);
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return 0;
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}
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#ifdef CONFIG_PM
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static int sunxi_gpadc_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct sunxi_gpadc *p_sunxi_gpadc = platform_get_drvdata(pdev);
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disable_irq_nosync(p_sunxi_gpadc->irq_num);
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sunxi_gpadc_en(p_sunxi_gpadc->reg_base, false);
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clk_disable_unprepare(p_sunxi_gpadc->mclk);
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return 0;
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}
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static int sunxi_gpadc_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct sunxi_gpadc *p_sunxi_gpadc = platform_get_drvdata(pdev);
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enable_irq(p_sunxi_gpadc->irq_num);
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sunxi_gpadc_en(p_sunxi_gpadc->reg_base, true);
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clk_prepare_enable(p_sunxi_gpadc->mclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops sunxi_gpadc_dev_pm_ops = {
|
|
.suspend = sunxi_gpadc_suspend,
|
|
.resume = sunxi_gpadc_resume,
|
|
};
|
|
|
|
#define SUNXI_GPADC_DEV_PM_OPS (&sunxi_gpadc_dev_pm_ops)
|
|
#else
|
|
#define SUNXI_GPADC_DEV_PM_OPS NULL
|
|
#endif
|
|
|
|
static struct of_device_id sunxi_gpadc_of_match[] = {
|
|
{ .compatible = "allwinner,sunxi-gpadc"},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sunxi_gpadc_of_match);
|
|
|
|
static struct platform_driver sunxi_gpadc_driver = {
|
|
.probe = sunxi_gpadc_probe,
|
|
.remove = sunxi_gpadc_remove,
|
|
.driver = {
|
|
.name = "sunxi-gpadc",
|
|
.owner = THIS_MODULE,
|
|
.pm = SUNXI_GPADC_DEV_PM_OPS,
|
|
.of_match_table = of_match_ptr(sunxi_gpadc_of_match),
|
|
},
|
|
};
|
|
module_platform_driver(sunxi_gpadc_driver);
|
|
|
|
MODULE_AUTHOR("Fuzhaoke");
|
|
MODULE_DESCRIPTION("sunxi-gpadc driver");
|
|
MODULE_LICENSE("GPL");
|