136 lines
4.5 KiB
C
136 lines
4.5 KiB
C
/*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef SUNXI_IR_RX_H
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#define SUNXI_IR_RX_H
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#define CONFIG_FPGA_V4_PLATFORM
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/* Registers */
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#define IR_REG(x) (x)
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#define IR_CTRL_REG IR_REG(0x00) /* IR Control */
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#define IR_RXCFG_REG IR_REG(0x10) /* Rx Config */
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#define IR_RXDAT_REG IR_REG(0x20) /* Rx Data */
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#define IR_RXINTE_REG IR_REG(0x2C) /* Rx Interrupt Enable */
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#define IR_RXINTS_REG IR_REG(0x30) /* Rx Interrupt Status */
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#define IR_SPLCFG_REG IR_REG(0x34) /* IR Sample Config */
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#define IR_FIFO_SIZE (64) /* 64Bytes */
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#if (defined CONFIG_FPGA_V4_PLATFORM) || (defined CONFIG_FPGA_V7_PLATFORM)
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#define CIR_FPGA
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#endif
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#ifdef CIR_FPGA
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#define IR_SIMPLE_UNIT (21333) /* simple in ns */
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#define IR_CLK (24000000) /* fpga clk output is fixed */
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#define IR_CIR_MODE (0x3 << 4) /* CIR mode enable */
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#define IR_ENTIRE_ENABLE (0x3 << 0) /* IR entire enable */
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#define IR_SAMPLE_DEV (0x3 << 0) /* 24MHz/512 =46875Hz (21333ns) */
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#define IR_FIFO_32 (((IR_FIFO_SIZE >> 1) - 1) << 8)
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#define IR_IRQ_STATUS ((0x1 << 4) | 0x3)
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#else
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#define IR_SIMPLE_UNIT (32000) /* simple in ns */
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#define IR_CLK (8000000)
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#define IR_CIR_MODE (0x3 << 4) /* CIR mode enable */
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#define IR_ENTIRE_ENABLE (0x3 << 0) /* IR entire enable */
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#define IR_SAMPLE_DEV (0x2 << 0) /* 4MHz/256 =31250Hz (32000ns) */
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#define IR_FIFO_32 (((IR_FIFO_SIZE >> 1) - 1) << 8)
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#define IR_IRQ_STATUS ((0x1 << 4) | 0x3)
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#endif
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//Bit Definition of IR_RXINTS_REG Register
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#define IR_RXINTS_RXOF (0x1 << 0) /* Rx FIFO Overflow */
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#define IR_RXINTS_RXPE (0x1 << 1) /* Rx Packet End */
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#define IR_RXINTS_RXDA (0x1 << 4) /* Rx FIFO Data Available */
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#ifdef CIR_FPGA
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#define IR_RXIDLE_VAL (((5) & 0xff) << 8) /* Filter Threshold = 16*21.3 = ~341us < 500us */
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#define IR_ACTIVE_T_SAMPLE ((16 & 0xff) << 16) /* Active Threshold (0+1)*128clock*21us = 2.6ms */
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#define IR_RXFILT_VAL_RC5 (((0x16) & 0x3f) << 2) /* Filter Threshold = 22*21us = 336us < 500us */
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#define IR_RXFILT_VAL (((16) & 0x3f) << 2) /* Filter Threshold = 16*21.3 = ~341us < 500us */
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#define IR_ACTIVE_T ((0 & 0xff) << 16) /* Active Threshold */
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#define IR_ACTIVE_T_C ((1 & 0xff) << 23) /* Active Threshold */
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#else
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#define IR_RXFILT_VAL (((12) & 0x3f) << 2) /* Filter Threshold = 12*32 = ~384us < 500us */
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#define IR_RXIDLE_VAL (((2) & 0xff) << 8) /* Idle Threshold = (2+1)*128*32 = ~23.8ms > 9ms */
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#define IR_ACTIVE_T ((99 & 0xff) << 16) /* Active Threshold */
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#define IR_ACTIVE_T_C ((0 & 0xff) << 23) /* Active Threshold */
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#define IR_ACTIVE_T_SAMPLE ((16 & 0xff) << 16) /* Active Threshold (0+1)*128clock*21us = 2.6ms */
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#define IR_RXFILT_VAL_RC5 (((0x16) & 0x3f) << 2) /* Filter Threshold = 22*21us = 336us < 500us */
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#endif
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#define IR_ERROR_CODE (0xffffffff)
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#define IR_REPEAT_CODE (0x00000000)
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#define DRV_VERSION "1.00"
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#define MAX_ADDR_NUM (64)
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#define RC_MAP_SUNXI "rc_map_sunxi"
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#define IR_BOTH_PULSE (0x1 << 6)
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#define IR_LOW_PULSE (0x2 << 6)
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#define IR_HIGH_PULSE (0x3 << 6)
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enum {
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DEBUG_INIT = 1U << 0,
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DEBUG_INT = 1U << 1,
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DEBUG_DATA_INFO = 1U << 2,
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DEBUG_SUSPEND = 1U << 3,
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DEBUG_ERR = 1U << 4,
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};
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enum ir_mode {
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CIR_MODE_ENABLE,
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IR_MODULE_ENABLE,
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IR_BOTH_PULSE_MODE, /* new feature to avoid noisy */
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IR_LOW_PULSE_MODE,
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IR_HIGH_PULSE_MODE,
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};
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enum ir_sample_config {
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IR_SAMPLE_REG_CLEAR,
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IR_CLK_SAMPLE,
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IR_FILTER_TH_NEC,
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IR_FILTER_TH_RC5,
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IR_IDLE_TH,
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IR_ACTIVE_TH,
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IR_ACTIVE_TH_SAMPLE,
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};
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enum ir_irq_config {
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IR_IRQ_STATUS_CLEAR,
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IR_IRQ_ENABLE,
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IR_IRQ_FIFO_SIZE,
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};
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enum {
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IR_SUPLY_DISABLE = 0,
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IR_SUPLY_ENABLE,
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};
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struct sunxi_ir_data{
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void __iomem *reg_base;
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struct platform_device *pdev;
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struct clk *mclk;
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struct clk *pclk;
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struct rc_dev *rcdev;
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struct regulator *suply;
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u32 suply_vol;
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int irq_num;
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u32 ir_addr_cnt;
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u32 ir_addr[MAX_ADDR_NUM];
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u32 ir_powerkey[MAX_ADDR_NUM];
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u32 ir_protocol_used;
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};
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int init_rc_map_sunxi(u32 *addr, u32 addr_num);
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void exit_rc_map_sunxi(void);
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#endif /* SUNXI_IR_RX_H */
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