635 lines
16 KiB
C
635 lines
16 KiB
C
/*
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* Driver for sunxi SD/MMC host controllers
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* (C) Copyright 2012-2017 lixiang <lixiang@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifdef CONFIG_ARCH_SUN8IW10P1
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#include <linux/clk.h>
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#include <linux/clk-private.h>
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#include <linux/clk/sunxi.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/reset.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/slot-gpio.h>
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#include "sunxi-smhc.h"
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#include "sunxi-mmc-v5px.h"
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#define SMHC_DS_DLY (0x230)
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#define SMHC_THLD (0x20c)
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#define SMHC_SAMP_DL_SW_MASK (0x0000003F)
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#define SMHC_DS_DL_SW_MASK (0x0000003F)
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#define SMHC_DS_DL_SW_EN (1u<<7)
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#define SMHC_CARD_RD_TH_SZ 0x000007FF
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#define SMHC_CARD_RD_TH_MASK 0x000007FF
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#define SMHC_CARD_RD_TH_SHIFT 0
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#define SMHC_CARD_WR_TH_SZ 0x000007FF
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#define SMHC_CARD_WR_TH_MASK (0x000007FF<<16)
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#define SMHC_CARD_WR_TH_SHIFT 16
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#define SMHC_DES_NUM_SHIFT_V5PX (15)
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#define SMHC_DES_BUFFER_MAX_LEN_V5PX (1U << SMHC_DES_NUM_SHIFT)
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enum sunxi_mmc_speed_mode{
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SM0_DS26_SDR12 = 0,
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SM1_HSSDR52_SDR25,
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SM2_HSDDR52_DDR50,
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SM3_HS200_SDR104,
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SM4_HS400,
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SM_NUM,
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};
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struct sunxi_mmc_clk_dly {
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enum sunxi_mmc_speed_mode spm;
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char *mod_str;
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char *raw_tm_sm_str[2];
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u32 raw_tm_sm[2];
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u32 raw_tm_sm_def[2];
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};
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struct sunxi_mmc_ver_priv {
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/*struct sunxi_mmc_spec_regs bak_spec_regs;*/
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struct sunxi_mmc_clk_dly mmc_clk_dly[SM_NUM];
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};
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static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *host , int clk , int bus_width , int timing)
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{
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struct mmc_host *mmc = host->mmc;
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enum sunxi_mmc_speed_mode speed_mod = SM0_DS26_SDR12;
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char *raw_sm_str = NULL;
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char *m_str = NULL;
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struct device_node *np = NULL;
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u32 *raw_sm = 0;
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u32 *raw_sm_def = 0;
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u32 rval = 0;
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int frq_index = 0;
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u32 cmd_drv_ph = 1;
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u32 dat_drv_ph = 0;
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u32 sam_dly = 0;
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u32 ds_dly = 0;
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struct sunxi_mmc_clk_dly *mmc_clk_dly =
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((struct sunxi_mmc_ver_priv *)host->version_priv_dat)->mmc_clk_dly;
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if (!mmc->parent || !mmc->parent->of_node) {
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dev_err(mmc_dev(host->mmc), "no dts to parse clk dly,use default\n");
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return ;
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}
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np = mmc->parent->of_node;
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switch (timing) {
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case MMC_TIMING_LEGACY:
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case MMC_TIMING_UHS_SDR12:
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speed_mod = SM0_DS26_SDR12;
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break;
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_UHS_SDR25:
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speed_mod = SM1_HSSDR52_SDR25;
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break;
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case MMC_TIMING_UHS_DDR50:
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speed_mod = SM2_HSDDR52_DDR50;
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break;
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case MMC_TIMING_UHS_SDR50:
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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speed_mod = SM3_HS200_SDR104;
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break;
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case MMC_TIMING_MMC_HS400:
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speed_mod = SM4_HS400;
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break;
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default:
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dev_err(mmc_dev(mmc) , "Wrong timing input\n");
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return;
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}
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if (clk <= 400*1000) {
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frq_index = 0;
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} else if (clk <= 25*1000*1000) {
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frq_index = 1;
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} else if (clk <= 50*1000*1000) {
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frq_index = 2;
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} else if (clk <= 100*1000*1000) {
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frq_index = 3;
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} else if (clk <= 150*1000*1000) {
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frq_index = 4;
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} else if (clk <= 200*1000*1000) {
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frq_index = 5;
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} else if (clk <= 250*1000*1000) {
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frq_index = 6;
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} else if (clk <= 300*1000*1000) {
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frq_index = 7;
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} else {
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dev_err(mmc_dev(mmc) , "clk is over 300mhz\n");
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return;
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}
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BUG_ON(frq_index/4 > 2);
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dev_dbg(mmc_dev(host->mmc) , "freq %d frq index %d,frq/4 %x\n" , clk , frq_index , frq_index/4);
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raw_sm_str = mmc_clk_dly[speed_mod].raw_tm_sm_str[frq_index/4];
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raw_sm = &mmc_clk_dly[speed_mod].raw_tm_sm[frq_index/4];
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raw_sm_def = &mmc_clk_dly[speed_mod].raw_tm_sm_def[frq_index/4];
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m_str = mmc_clk_dly[speed_mod].mod_str;
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rval = of_property_read_u32(np, raw_sm_str, raw_sm);
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if (rval) {
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dev_info(mmc_dev(host->mmc) , "faild to get %s used default\n" , m_str);
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} else {
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u32 sm_shift = (frq_index%4)*8;
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rval = ((*raw_sm)>>sm_shift)&0xff;
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if (rval != 0xff) {
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if (timing == MMC_TIMING_MMC_HS400) {
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u32 raw_sm_hs200 = 0;
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ds_dly = rval;
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raw_sm_hs200 = mmc_clk_dly[SM3_HS200_SDR104].raw_tm_sm[frq_index/4];
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sam_dly = ((raw_sm_hs200)>>sm_shift)&0xff;
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} else {
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sam_dly = rval;
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}
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dev_dbg(mmc_dev(host->mmc) , "Get speed mode %s clk dly %s ok\n" , m_str , raw_sm_str);
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} else {
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u32 sm_shift = (frq_index%4)*8;
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dev_dbg(mmc_dev(host->mmc) , "%s use default value\n" , m_str);
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rval = ((*raw_sm_def)>>sm_shift)&0xff;
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if (timing == MMC_TIMING_MMC_HS400) {
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u32 raw_sm_hs200 = 0;
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ds_dly = rval;
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raw_sm_hs200 = mmc_clk_dly[SM3_HS200_SDR104].raw_tm_sm_def[frq_index/4];
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sam_dly = ((raw_sm_hs200)>>sm_shift)&0xff;
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} else {
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sam_dly = rval;
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}
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}
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}
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dev_dbg(mmc_dev(host->mmc) , "Try set %s clk dly ok\n" , m_str);
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dev_dbg(mmc_dev(host->mmc) , "cmd_drv_ph %d\n" , cmd_drv_ph);
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dev_dbg(mmc_dev(host->mmc) , "dat_drv_ph %d\n" , dat_drv_ph);
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dev_dbg(mmc_dev(host->mmc) , "sam_dly %d\n" , sam_dly);
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dev_dbg(mmc_dev(host->mmc) , "ds_dly %d\n" , ds_dly);
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/*
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rval = mmc_readl(host,REG_DRV_DL);
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if(cmd_drv_ph){
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rval |= SDXC_CMD_DRV_PH_SEL;//180 phase
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}else{
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rval &= ~SDXC_CMD_DRV_PH_SEL;//90 phase
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}
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if(dat_drv_ph){
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rval |= SDXC_DAT_DRV_PH_SEL;//180 phase
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}else{
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rval &= ~SDXC_DAT_DRV_PH_SEL;//90 phase
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}
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mmc_writel(host,REG_DRV_DL,rval);
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rval = mmc_readl(host,REG_SAMP_DL);
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rval &= ~SDXC_SAMP_DL_SW_MASK;
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rval |= sam_dly & SDXC_SAMP_DL_SW_MASK;
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rval |= SDXC_SAMP_DL_SW_EN;
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mmc_writel(host,REG_SAMP_DL,rval);
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*/
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rval = smhc_readl(host , SMHC_DS_DLY);
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rval &= ~SMHC_DS_DL_SW_MASK;
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rval |= ds_dly & SMHC_DS_DL_SW_MASK;
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rval |= SMHC_DS_DL_SW_EN;
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smhc_writel(host , SMHC_DS_DLY , rval);
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dev_dbg(mmc_dev(host->mmc) , " SMHC_DS_DLY %08x\n" , smhc_readl(host , SMHC_DS_DLY));
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}
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void sunxi_mmc_dump_dly2(struct sunxi_mmc_host *host)
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{
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dev_dbg(mmc_dev(host->mmc) , "no imple %s %d\n" , __FUNCTION__ , __LINE__);
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}
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static int __sunxi_mmc_do_oclk_onoff(struct sunxi_mmc_host *host , u32 oclk_en , u32 pwr_save , u32 ignore_dat0)
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{
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u32 tmp = 0;
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tmp = smhc_readl(host , SMHC_RST_CLK_CTRL);
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if (oclk_en) {
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tmp |= SdclkEn;
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} else {
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tmp &= ~SdclkEn;
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}
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smhc_writel(host , SMHC_RST_CLK_CTRL , tmp);
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tmp = smhc_readl(host , SMHC_CTRL3);
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if (pwr_save) {
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tmp |= SdclkIdleCtrl;
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} else {
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tmp &= ~SdclkIdleCtrl;
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}
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smhc_writel(host , SMHC_CTRL3 , tmp);
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return 0;
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}
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int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
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{
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struct device_node *np = NULL;
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struct mmc_host *mmc = host->mmc;
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int pwr_save = 0;
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int len = 0;
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if (!mmc->parent || !mmc->parent->of_node) {
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dev_err(mmc_dev(host->mmc), "no dts to parse power save mode\n");
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return -EIO; ;
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}
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np = mmc->parent->of_node;
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if (of_find_property(np, "sunxi-power-save-mode", &len))
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pwr_save = 1;
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return __sunxi_mmc_do_oclk_onoff(host , oclk_en , pwr_save , 1);
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}
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int sunxi_mmc_clk_set_rate_v5px(struct sunxi_mmc_host *host,
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struct mmc_ios *ios)
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{
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u32 mod_clk = 0;
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u32 src_clk = 0;
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u32 rval = 0;
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s32 err = 0;
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u32 rate = 0;
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char *sclk_name = NULL;
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struct clk *mclk = host->clk_mmc;
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struct clk *sclk = NULL;
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struct device *dev = mmc_dev(host->mmc);
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if (ios->clock == 0) {
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__sunxi_mmc_do_oclk_onoff(host , 0 , 0 , 1);
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return 0;
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}
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if (ios->timing == MMC_TIMING_UHS_DDR50) {
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mod_clk = ios->clock<<3;
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} else{
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mod_clk = ios->clock<<2;
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}
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if (ios->clock <= 400000) {
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/*sclk = of_clk_get(np, 0);*/
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sclk = clk_get(dev , "osc24m");
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sclk_name = "osc24m";
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} else {
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/*sclk = clk_get(np, 1);*/
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sclk = clk_get(dev , "pll_periph");
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sclk_name = "pll_periph";
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}
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if (IS_ERR(sclk)) {
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dev_err(mmc_dev(host->mmc), "Error to get source clock %s\n" , sclk_name);
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return -1;
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}
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sunxi_mmc_oclk_onoff(host, 0);
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err = clk_set_parent(mclk, sclk);
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if (err) {
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dev_err(mmc_dev(host->mmc), "set parent failed\n");
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clk_put(sclk);
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return -1;
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}
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rate = clk_round_rate(mclk, mod_clk);
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dev_dbg(mmc_dev(host->mmc) , "get round rate %d\n" , rate);
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clk_disable_unprepare(host->clk_mmc);
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err = clk_set_rate(mclk, rate);
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if (err) {
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dev_err(mmc_dev(host->mmc) , "set mclk rate error, rate %dHz\n" , rate);
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clk_put(sclk);
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return -1;
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}
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rval = clk_prepare_enable(host->clk_mmc);
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if (rval) {
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dev_err(mmc_dev(host->mmc), "Enable mmc clk err %d\n", rval);
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return -1;
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}
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src_clk = clk_get_rate(sclk);
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clk_put(sclk);
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dev_dbg(mmc_dev(host->mmc) , "set round clock %d, soure clk is %d\n" , rate , src_clk);
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/*sunxi_of_parse_clk_dly(host);*/
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if (ios->timing == MMC_TIMING_UHS_DDR50) {
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ios->clock = rate>>3;
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} else {
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ios->clock = rate>>2;
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}
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sunxi_mmc_set_clk_dly(host , ios->clock , ios->bus_width , ios->timing);
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return sunxi_mmc_oclk_onoff(host , 1);
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}
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void sunxi_mmc_thld_ctl_v5px(struct sunxi_mmc_host *host,
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struct mmc_ios *ios, struct mmc_data *data)
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{
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u32 bsz = data->blksz;
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u32 rval = 0;
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if ((data->flags & MMC_DATA_WRITE)
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&& (bsz <= SMHC_CARD_WR_TH_SZ)) {
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rval = smhc_readl(host, SMHC_THLD);
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rval &= ~SMHC_CARD_WR_TH_MASK;
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rval |= data->blksz << SMHC_CARD_WR_TH_SHIFT;
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/*rval |= SDXC_CARD_WR_THLD_ENB;*/
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smhc_writel(host, SMHC_THLD, rval);
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} else {
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/*
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rval = mmc_readl(host, REG_THLD);
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rval &= ~SDXC_CARD_WR_THLD_ENB;
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mmc_writel(host, REG_THLD, rval);
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*/
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}
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if ((data->flags & MMC_DATA_READ)
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&& (bsz <= SMHC_CARD_RD_TH_SZ)
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&& ((ios->timing == MMC_TIMING_MMC_HS200)
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|| (ios->timing == MMC_TIMING_MMC_HS400)
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|| (ios->timing == MMC_TIMING_UHS_SDR50)
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|| (ios->timing == MMC_TIMING_UHS_SDR104))) {
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rval = smhc_readl(host, SMHC_THLD);
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rval &= ~SMHC_CARD_RD_TH_MASK;
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rval |= data->blksz << SMHC_CARD_RD_TH_SHIFT;
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/*rval |= SDXC_CARD_RD_THLD_ENB;*/
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smhc_writel(host, SMHC_THLD, rval);
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} else {
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/*
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rval = mmc_readl(host, REG_THLD);
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rval &= ~SDXC_CARD_RD_THLD_ENB;
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mmc_writel(host, REG_THLD, rval);
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*/
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}
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dev_dbg(mmc_dev(host->mmc), "--SDXC_REG_THLD: 0x%08x \n",
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smhc_readl(host, SMHC_THLD));
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}
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void sunxi_mmc_save_spec_reg_v5px(struct sunxi_mmc_host *host)
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{
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dev_dbg(mmc_dev(host->mmc) , "no imple %s %d\n" , __FUNCTION__ , __LINE__);
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}
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void sunxi_mmc_restore_spec_reg_v5px(struct sunxi_mmc_host *host)
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{
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dev_dbg(mmc_dev(host->mmc) , "no imple %s %d\n" , __FUNCTION__ , __LINE__);
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}
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int mmc_card_sleep(struct mmc_host *host);
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int mmc_deselect_cards(struct mmc_host *host);
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void mmc_power_off(struct mmc_host *host);
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int mmc_card_sleepawake(struct mmc_host *host, int sleep);
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static int sunxi_mmc_can_poweroff_notify(const struct mmc_card *card)
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{
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return card &&
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mmc_card_mmc(card) &&
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(card->ext_csd.power_off_notification == EXT_CSD_POWER_ON);
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}
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static int sunxi_mmc_poweroff_notify(struct mmc_card *card, unsigned int notify_type)
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{
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unsigned int timeout = card->ext_csd.generic_cmd6_time;
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int err;
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/* Use EXT_CSD_POWER_OFF_SHORT as default notification type. */
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if (notify_type == EXT_CSD_POWER_OFF_LONG)
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timeout = card->ext_csd.power_off_longtime;
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err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_POWER_OFF_NOTIFICATION,
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notify_type, timeout, true, false, false);
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if (err)
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pr_err("%s: Power Off Notification timed out, %u\n",
|
|
mmc_hostname(card->host), timeout);
|
|
|
|
/* Disable the power off notification after the switch operation. */
|
|
card->ext_csd.power_off_notification = EXT_CSD_NO_POWER_NOTIFICATION;
|
|
|
|
return err;
|
|
}
|
|
|
|
|
|
static int sunxi_mmc_sleep(struct mmc_host *host)
|
|
{
|
|
struct mmc_card *card = host->card;
|
|
int err = -ENOSYS;
|
|
|
|
if (card && card->ext_csd.rev >= 3) {
|
|
err = mmc_card_sleepawake(host, 1);
|
|
if (err < 0)
|
|
pr_debug("%s: Error %d while putting card into sleep",
|
|
mmc_hostname(host), err);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
|
|
|
|
static int sunxi_mmc_suspend(struct mmc_host *host, bool is_suspend)
|
|
{
|
|
int err = 0;
|
|
unsigned int notify_type = is_suspend ? EXT_CSD_POWER_OFF_SHORT :
|
|
EXT_CSD_POWER_OFF_LONG;
|
|
|
|
BUG_ON(!host);
|
|
BUG_ON(!host->card);
|
|
|
|
mmc_claim_host(host);
|
|
|
|
/*
|
|
if (mmc_card_suspended(host->card))
|
|
goto out;
|
|
*/
|
|
|
|
if (mmc_card_doing_bkops(host->card)) {
|
|
err = mmc_stop_bkops(host->card);
|
|
if (err)
|
|
goto out;
|
|
}
|
|
|
|
err = mmc_flush_cache(host->card);
|
|
|
|
if (err)
|
|
goto out;
|
|
|
|
if (sunxi_mmc_can_poweroff_notify(host->card) &&
|
|
((host->caps2 & MMC_CAP2_POWEROFF_NOTIFY) || !is_suspend)) {
|
|
err = sunxi_mmc_poweroff_notify(host->card, notify_type);
|
|
} else if (mmc_card_can_sleep(host)) {
|
|
err = sunxi_mmc_sleep(host);
|
|
} else if (!mmc_host_is_spi(host)) {
|
|
err = mmc_deselect_cards(host);
|
|
}
|
|
|
|
if (!err) {
|
|
pr_info("%s: %s %d\n",
|
|
mmc_hostname(host) , __FUNCTION__ , __LINE__);
|
|
mmc_power_off(host);
|
|
/* mmc_card_set_suspended(host->card);*/
|
|
}
|
|
|
|
out:
|
|
mmc_release_host(host);
|
|
return err;
|
|
}
|
|
|
|
|
|
|
|
void sunxi_mmc_do_shutdown_v5px(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
u32 shutdown_notify_type = 0;
|
|
u32 rval = of_property_read_u32(mmc->parent->of_node, "shutdown_notify_type", &shutdown_notify_type);
|
|
if (!rval) {
|
|
sunxi_mmc_suspend(mmc , shutdown_notify_type);
|
|
} else {
|
|
sunxi_mmc_suspend(mmc , false);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
void sunxi_mmc_init_priv_v5px(struct sunxi_mmc_host *host,
|
|
struct platform_device *pdev, int phy_index)
|
|
{
|
|
struct sunxi_mmc_ver_priv *ver_priv =
|
|
devm_kzalloc(&pdev->dev, sizeof(struct sunxi_mmc_ver_priv),
|
|
GFP_KERNEL);
|
|
host->version_priv_dat = ver_priv;
|
|
|
|
ver_priv->mmc_clk_dly[SM0_DS26_SDR12].spm = SM0_DS26_SDR12;
|
|
ver_priv->mmc_clk_dly[SM0_DS26_SDR12].mod_str = "DS26_SDR12";
|
|
ver_priv->mmc_clk_dly[SM0_DS26_SDR12].raw_tm_sm_str[0] =
|
|
"sdc_tm4_sm0_freq0";
|
|
ver_priv->mmc_clk_dly[SM0_DS26_SDR12].raw_tm_sm_str[1] =
|
|
"sdc_tm4_sm0_freq1";
|
|
ver_priv->mmc_clk_dly[SM0_DS26_SDR12].raw_tm_sm[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM0_DS26_SDR12].raw_tm_sm[1] = 0;
|
|
ver_priv->mmc_clk_dly[SM0_DS26_SDR12].raw_tm_sm_def[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM0_DS26_SDR12].raw_tm_sm_def[1] = 0;
|
|
|
|
ver_priv->mmc_clk_dly[SM1_HSSDR52_SDR25].spm = SM1_HSSDR52_SDR25;
|
|
ver_priv->mmc_clk_dly[SM1_HSSDR52_SDR25].mod_str = "HSSDR52_SDR25";
|
|
ver_priv->mmc_clk_dly[SM1_HSSDR52_SDR25].raw_tm_sm_str[0] =
|
|
"sdc_tm4_sm1_freq0";
|
|
ver_priv->mmc_clk_dly[SM1_HSSDR52_SDR25].raw_tm_sm_str[1] =
|
|
"sdc_tm4_sm1_freq1";
|
|
ver_priv->mmc_clk_dly[SM1_HSSDR52_SDR25].raw_tm_sm[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM1_HSSDR52_SDR25].raw_tm_sm[1] = 0;
|
|
ver_priv->mmc_clk_dly[SM1_HSSDR52_SDR25].raw_tm_sm_def[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM1_HSSDR52_SDR25].raw_tm_sm_def[1] = 0;
|
|
|
|
ver_priv->mmc_clk_dly[SM2_HSDDR52_DDR50].spm = SM2_HSDDR52_DDR50;
|
|
ver_priv->mmc_clk_dly[SM2_HSDDR52_DDR50].mod_str = "HSDDR52_DDR50";
|
|
ver_priv->mmc_clk_dly[SM2_HSDDR52_DDR50].raw_tm_sm_str[0] =
|
|
"sdc_tm4_sm2_freq0";
|
|
ver_priv->mmc_clk_dly[SM2_HSDDR52_DDR50].raw_tm_sm_str[1] =
|
|
"sdc_tm4_sm2_freq1";
|
|
ver_priv->mmc_clk_dly[SM2_HSDDR52_DDR50].raw_tm_sm[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM2_HSDDR52_DDR50].raw_tm_sm[1] = 0;
|
|
ver_priv->mmc_clk_dly[SM2_HSDDR52_DDR50].raw_tm_sm_def[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM2_HSDDR52_DDR50].raw_tm_sm_def[1] = 0;
|
|
|
|
ver_priv->mmc_clk_dly[SM3_HS200_SDR104].spm = SM3_HS200_SDR104;
|
|
ver_priv->mmc_clk_dly[SM3_HS200_SDR104].mod_str = "HS200_SDR104";
|
|
ver_priv->mmc_clk_dly[SM3_HS200_SDR104].raw_tm_sm_str[0] =
|
|
"sdc_tm4_sm3_freq0";
|
|
ver_priv->mmc_clk_dly[SM3_HS200_SDR104].raw_tm_sm_str[1] =
|
|
"sdc_tm4_sm3_freq1";
|
|
ver_priv->mmc_clk_dly[SM3_HS200_SDR104].raw_tm_sm[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM3_HS200_SDR104].raw_tm_sm[1] = 0;
|
|
ver_priv->mmc_clk_dly[SM3_HS200_SDR104].raw_tm_sm_def[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM3_HS200_SDR104].raw_tm_sm_def[1] = 0x00000405;
|
|
|
|
ver_priv->mmc_clk_dly[SM4_HS400].spm = SM4_HS400;
|
|
ver_priv->mmc_clk_dly[SM4_HS400].mod_str = "HS400";
|
|
ver_priv->mmc_clk_dly[SM4_HS400].raw_tm_sm_str[0] = "sdc_tm4_sm4_freq0";
|
|
ver_priv->mmc_clk_dly[SM4_HS400].raw_tm_sm_str[1] = "sdc_tm4_sm4_freq1";
|
|
ver_priv->mmc_clk_dly[SM4_HS400].raw_tm_sm[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM4_HS400].raw_tm_sm[1] = 0x00000608;
|
|
ver_priv->mmc_clk_dly[SM4_HS400].raw_tm_sm_def[0] = 0;
|
|
ver_priv->mmc_clk_dly[SM4_HS400].raw_tm_sm_def[1] = 0x00000408;
|
|
|
|
host->sunxi_mmc_clk_set_rate = sunxi_mmc_clk_set_rate_v5px;
|
|
/*host->idma_des_size_bits = 15; */
|
|
host->idma_des_size_bits = SMHC_DES_NUM_SHIFT_V5PX;
|
|
host->sunxi_mmc_thld_ctl = sunxi_mmc_thld_ctl_v5px;
|
|
host->sunxi_mmc_save_spec_reg = sunxi_mmc_save_spec_reg_v5px;
|
|
host->sunxi_mmc_restore_spec_reg = sunxi_mmc_restore_spec_reg_v5px;
|
|
/*sunxi_mmc_reg_ex_res_inter(host, phy_index);
|
|
host->sunxi_mmc_set_acmda = sunxi_mmc_set_a12a;
|
|
*/
|
|
host->sunxi_mmc_dump_dly_table = sunxi_mmc_dump_dly2;
|
|
host->phy_index = phy_index;
|
|
host->sunxi_mmc_shutdown = sunxi_mmc_do_shutdown_v5px;
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|