889 lines
29 KiB
C
889 lines
29 KiB
C
/*
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* arch/arm/mach-sunxi/pm/ccmu-sun9iw1p1.h
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*
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* Copyright 2012 (c) njubietech.
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* gq.yang (yanggq@njubietech.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __MEM_CCMU_SUN9IW1P1_H__
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#define __MEM_CCMU_SUN9IW1P1_H__
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/**/
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/* Register Offset*/
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/**/
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#define PLL_C0_CFG_REG_OFF 0x0000
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#define PLL_C1_CFG_REG_OFF 0x0004
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#define PLL_AUDIO_CFG_REG_OFF 0x0008
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#define PLL_PERIPH1_CFG_REG_OFF 0x000C
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#define PLL_VE_CFG_REG_OFF 0x0010
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#define PLL_DDR_CFG_REG_OFF 0x0014
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#define PLL_VIDEO1_CFG_REG_OFF 0x0018
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#define PLL_VIDEO2_CFG_REG_OFF 0x001C
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#define PLL_GPU_CFG_REG_OFF 0x0020
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#define PLL_DE_CFG_REG_OFF 0x0024
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#define PLL_ISP_CFG_REG_OFF 0x0028
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#define PLL_PERIPH2_CFG_REG_OFF 0x002C
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#define CPU_CLK_SRC_REG_OFF 0x0050
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#define AXI0_CFG_REG_OFF 0x0054
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#define AXI1_CFG_REG_OFF 0x0058
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#define GTCLK_CFG_REG_OFF 0x005C
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#define AHB0_CFG_REG_OFF 0x0060
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#define AHB1_CFG_REG_OFF 0x0064
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#define AHB2_CFG_REG_OFF 0x0068
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#define APB0_CFG_REG_OFF 0x0070
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#define APB1_CFG_REG_OFF 0x0074
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#define CCI400_CFG_REG_OFF 0x0078
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#define ATS_CLK_REG_OFF 0x0080
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#define TRACE_CLK_REG_OFF 0x0084
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#define PLL_LOCK_CFG_REG0_OFF 0x0090
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#define PLL_LOCK_CFG_REG1_OFF 0x0094
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#define PLL_LOCK_STATUS_REG_OFF 0x009C
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#define PLL_C0_BIAS_REG_OFF 0x00A0
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#define PLL_C1_BIAS_REG_OFF 0x00A4
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#define PLL_AUDIO_BIAS_REG_OFF 0x00A8
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#define PLL_PERIPH1_BIAS_REG_OFF 0x00AC
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#define PLL_VE_BIAS_REG_OFF 0x00B0
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#define PLL_DDR_BIAS_REG_OFF 0x00B4
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#define PLL_VIDEO1_BIAS_REG_OFF 0x00B8
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#define PLL_VIDEO2_BIAS_REG_OFF 0x00BC
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#define PLL_GPU_BIAS_REG_OFF 0x00C0
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#define PLL_DE_BIAS_REG_OFF 0x00C4
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#define PLL_ISP_BIAS_REG_OFF 0x00C8
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#define PLL_PERIPH2_BIAS_REG_OFF 0x00CC
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#define PLL_C0_TUN_REG_OFF 0x00E0
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#define PLL_C1_TUN_REG_OFF 0x00E4
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#define PLL_AUDIO_PAT_CFG_REG_OFF 0x0108
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#define PLL_PERIPH1_PAT_CFG_REG_OFF 0x010C
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#define PLL_VE_PAT_CFG_REG_OFF 0x0110
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#define PLL_DDR_PAT_CFG_REG_OFF 0x0114
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#define PLL_VIDEO1_PAT_CFG_REG_OFF 0x0118
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#define PLL_VIDEO2_PAT_CFG_REG_OFF 0x011C
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#define PLL_GPU_PAT_CFG_REG_OFF 0x0120
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#define PLL_DE_PAT_CFG_REG_OFF 0x0124
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#define PLL_ISP_PAT_CFG_REG_OFF 0x0128
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#define PLL_PERIPH2_PAT_CFG_REG_OFF 0x012C
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#define CLK_OUTA_REG_OFF 0x0180
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#define CLK_OUTB_REG_OFF 0x0184
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/**/
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/* Register Address*/
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/**/
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#define PLL_C0_CFG_REG_ADDR (CCM_VBASE + PLL_C0_CFG_REG_OFF) /**/
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#define PLL_C1_CFG_REG_ADDR (CCM_VBASE + PLL_C1_CFG_REG_OFF) /**/
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#define PLL_AUDIO_CFG_REG_ADDR (CCM_VBASE + PLL_AUDIO_CFG_REG_OFF) /**/
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#define PLL_PERIPH1_CFG_REG_ADDR (CCM_VBASE + PLL_PERIPH1_CFG_REG_OFF) /**/
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#define PLL_VE_CFG_REG_ADDR (CCM_VBASE + PLL_VE_CFG_REG_OFF) /**/
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#define PLL_DDR_CFG_REG_ADDR (CCM_VBASE + PLL_DDR_CFG_REG_OFF) /**/
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#define PLL_VIDEO1_CFG_REG_ADDR (CCM_VBASE + PLL_VIDEO1_CFG_REG_OFF) /**/
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#define PLL_VIDEO2_CFG_REG_ADDR (CCM_VBASE + PLL_VIDEO2_CFG_REG_OFF) /**/
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#define PLL_GPU_CFG_REG_ADDR (CCM_VBASE + PLL_GPU_CFG_REG_OFF) /**/
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#define PLL_DE_CFG_REG_ADDR (CCM_VBASE + PLL_DE_CFG_REG_OFF) /**/
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#define PLL_ISP_CFG_REG_ADDR (CCM_VBASE + PLL_ISP_CFG_REG_OFF) /**/
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#define PLL_PERIPH2_CFG_REG_ADDR (CCM_VBASE + PLL_PERIPH2_CFG_REG_OFF) /**/
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#define CPU_CLK_SRC_REG_ADDR (CCM_VBASE + CPU_CLK_SRC_REG_OFF) /* CPU CLK ratio register */
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#define AXI0_CFG_REG_ADDR (CCM_VBASE + AXI0_CFG_REG_OFF) /* AXI0 CLK ratio register */
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#define AXI1_CFG_REG_ADDR (CCM_VBASE + AXI1_CFG_REG_OFF) /* AXI1 CLK ratio register */
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#define GTCLK_CFG_REG_ADDR (CCM_VBASE + GTCLK_CFG_REG_OFF) /* GTBUS CLK control register */
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#define AHB0_CFG_REG_ADDR (CCM_VBASE + AHB0_CFG_REG_OFF) /* AHB0 CLK ratio register */
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#define AHB1_CFG_REG_ADDR (CCM_VBASE + AHB1_CFG_REG_OFF) /* AHB1 CLK ratio register */
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#define AHB2_CFG_REG_ADDR (CCM_VBASE + AHB2_CFG_REG_OFF) /* AHB2 CLK ratio register */
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#define APB0_CFG_REG_ADDR (CCM_VBASE + APB0_CFG_REG_OFF) /* APB0 clock divider register */
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#define APB1_CFG_REG_ADDR (CCM_VBASE + APB1_CFG_REG_OFF) /* APB1 clock divider register */
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#define CCI400_CFG_REG_ADDR (CCM_VBASE + CCI400_CFG_REG_OFF) /* CCI-400 clock divider register */
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#define ATS_CLK_REG_ADDR (CCM_VBASE + ATS_CLK_REG_OFF) /* ATS CLK ratio register */
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#define TRACE_CLK_REG_ADDR (CCM_VBASE + TRACE_CLK_REG_OFF) /* TRACE CLK ratio register */
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#define PLL_LOCK_CFG_REG0_ADDR (CCM_VBASE + PLL_LOCK_CFG_REG0_OFF) /* PLL(except PLLC0/C1) lock time control register */
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#define PLL_LOCK_CFG_REG1_ADDR (CCM_VBASE + PLL_LOCK_CFG_REG1_OFF) /* PLLC0 and PLLC1 lock time control register */
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#define PLL_LOCK_STATUS_REG_ADDR (CCM_VBASE + PLL_LOCK_STATUS_REG_OFF) /* PLL lock status register */
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#define PLL_C0_BIAS_REG_ADDR (CCM_VBASE + PLL_C0_BIAS_REG_OFF) /* PLLC0 Bias register */
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#define PLL_C1_BIAS_REG_ADDR (CCM_VBASE + PLL_C1_BIAS_REG_OFF) /* PLLC1 Bias register */
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#define PLL_AUDIO_BIAS_REG_ADDR (CCM_VBASE + PLL_AUDIO_BIAS_REG_OFF) /* PLL_AUDIO Bias register */
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#define PLL_PERIPH1_BIAS_REG_ADDR (CCM_VBASE + PLL_PERIPH1_BIAS_REG_OFF) /* PLL_PERIPH1 Bias register */
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#define PLL_VE_BIAS_REG_ADDR (CCM_VBASE + PLL_VE_BIAS_REG_OFF) /* PLL_VE Bias register */
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#define PLL_DDR_BIAS_REG_ADDR (CCM_VBASE + PLL_DDR_BIAS_REG_OFF) /* PLL_DDR Bias register */
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#define PLL_VIDEO1_BIAS_REG_ADDR (CCM_VBASE + PLL_VIDEO1_BIAS_REG_OFF) /* PLL_VIDEO1 Bias register */
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#define PLL_VIDEO2_BIAS_REG_ADDR (CCM_VBASE + PLL_VIDEO2_BIAS_REG_OFF) /* PLL_VIDEO2 Bias register */
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#define PLL_GPU_BIAS_REG_ADDR (CCM_VBASE + PLL_GPU_BIAS_REG_OFF) /* PLL_GPU Bias register */
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#define PLL_DE_BIAS_REG_ADDR (CCM_VBASE + PLL_DE_BIAS_REG_OFF) /* PLL_DE Bias register */
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#define PLL_ISP_BIAS_REG_ADDR (CCM_VBASE + PLL_ISP_BIAS_REG_OFF) /* PLL_ISP Bias register */
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#define PLL_PERIPH2_BIAS_REG_ADDR (CCM_VBASE + PLL_PERIPH2_BIAS_REG_OFF) /* PLL_PERIPH2 Bias register */
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#define PLL_C0_TUN_REG_ADDR (CCM_VBASE + PLL_C0_TUN_REG_OFF) /* PLL-C0 tuning register */
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#define PLL_C1_TUN_REG_ADDR (CCM_VBASE + PLL_C1_TUN_REG_OFF) /* PLL-C1 tuning register */
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#define PLL_AUDIO_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_AUDIO_PAT_CFG_REG_OFF) /* PLL_AUDIO-PATTERN Control Register */
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#define PLL_PERIPH1_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_PERIPH1_PAT_CFG_REG_OFF) /* PLL_PERIPH1-PATTERN Control Register */
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#define PLL_VE_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_VE_PAT_CFG_REG_OFF) /* PLL_VE-PATTERN Control Register */
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#define PLL_DDR_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_DDR_PAT_CFG_REG_OFF) /* PLL_DDR-PATTERN Control Register */
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#define PLL_VIDEO1_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_VIDEO1_PAT_CFG_REG_OFF) /* PLL_VIDEO1-PATTERN Control Register */
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#define PLL_VIDEO2_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_VIDEO2_PAT_CFG_REG_OFF) /* PLL_VIDEO2-PATTERN Control Register */
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#define PLL_GPU_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_GPU_PAT_CFG_REG_OFF) /* PLL_GPU-PATTERN Control Register */
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#define PLL_DE_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_DE_PAT_CFG_REG_OFF) /* PLL_DE-PATTERN Control Register */
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#define PLL_ISP_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_ISP_PAT_CFG_REG_OFF) /* PLL_ISP-PATTERN Control Register */
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#define PLL_PERIPH2_PAT_CFG_REG_ADDR (CCM_VBASE + PLL_PERIPH2_PAT_CFG_REG_OFF) /* PLL_PERIPH2-PATTERN Control Register */
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#define CLK_OUTA_REG_ADDR (CCM_VBASE + CLK_OUTA_REG_OFF) /* CLK OUTA Control Register */
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#define CLK_OUTB_REG_ADDR (CCM_VBASE + CLK_OUTB_REG_OFF) /* CLK OUTB Control Register */
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/**/
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/* Detail information of registers*/
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/**/ typedef union {
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__u32 dwval;
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struct {
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__u32 pll_postdiv_m:2; /* Default: 0x0; */
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__u32 res0:6; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x11; */
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__u32 pll_out_ext_divp:1; /* Default: 0x0; */
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__u32 res1:7; /* Default: ; */
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__u32 pll_lock_time:3; /* Default: 0x2; */
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__u32 res2:4; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_C0_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 pll_postdiv_m:2; /* Default: 0x0; */
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__u32 res0:6; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x11; */
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__u32 pll_out_ext_divp:1; /* Default: 0x0; */
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__u32 res1:7; /* Default: ; */
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__u32 pll_lock_time:3; /* Default: 0x2; */
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__u32 res2:4; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_C1_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 pll_postdiv_p:6; /* Default: 0x14; */
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__u32 res0:2; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x2B; */
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__u32 pll_div1:1; /* Default: 0x0; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x1; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_AUDIO_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 res0:8; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x28; */
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__u32 pll_div1:1; /* Default: 0x0; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x0; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_PERIPH1_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 res0:8; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x24; */
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__u32 pll_div1:1; /* Default: 0x0; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x1; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_VE_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 res0:8; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x24; */
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__u32 pll_div1:1; /* Default: 0x0; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x1; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:5; /* Default: ; */
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__u32 sdrpll_upd:1; /* Default: 0x0; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_DDR_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 res0:8; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x63; */
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__u32 pll_div:1; /* Default: 0x1; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x0; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_VIDEO1_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 pll_out_ext_divp:2; /* Default: 0x0; */
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__u32 res0:6; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x63; */
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__u32 pll_div:1; /* Default: 0x1; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x0; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_VIDEO2_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 res0:8; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x24; */
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__u32 pll_div1:1; /* Default: 0x0; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x1; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_GPU_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 res0:8; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x24; */
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__u32 pll_div1:1; /* Default: 0x0; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x1; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_DE_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 res0:8; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x24; */
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__u32 pll_div1:1; /* Default: 0x0; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x1; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_ISP_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 res0:8; /* Default: ; */
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__u32 pll_factor_n:8; /* Default: 0x24; */
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__u32 pll_div1:1; /* Default: 0x0; */
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__u32 res1:1; /* Default: ; */
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__u32 pll_div2:1; /* Default: 0x1; */
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__u32 res2:5; /* Default: ; */
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__u32 pll_sdm_en:1; /* Default: 0x0; */
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__u32 res3:6; /* Default: ; */
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__u32 pll_enable:1; /* Default: 0x0; */
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} bits;
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} PLL_PERIPH2_CFG_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 cpu_c0_clk_src_sel:1; /* Default: 0x0; */
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__u32 res0:7; /* Default: ; */
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__u32 cpu_c1_clk_src_sel:1; /* Default: 0x0; */
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__u32 res1:23; /* Default: ; */
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} bits;
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} CPU_CLK_SRC_REG_t;
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typedef union {
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__u32 dwval;
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struct {
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__u32 axi0_clk_div_ratio:3; /* Default: 0x0; */
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__u32 res0:5; /* Default: ; */
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__u32 atb0_apb_clk_div:2; /* Default: 0x1; */
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__u32 res1:6; /* Default: ; */
|
|
} bits;
|
|
} AXI0_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 axi1_clk_div_ratio:3; /* Default: 0x0; */
|
|
__u32 res0:5; /* Default: ; */
|
|
__u32 atb1_apb_clk_div:2; /* Default: 0x1; */
|
|
__u32 res1:6; /* Default: ; */
|
|
} bits;
|
|
} AXI1_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 gtclk_clk_div_ratio:2; /* Default: 0x0; */
|
|
__u32 res0:22; /* Default: ; */
|
|
__u32 gtclk_src_sel:2; /* Default: 0x0; */
|
|
__u32 res1:6; /* Default: ; */
|
|
} bits;
|
|
} GTCLK_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 ahb0_clk_div_ratio:2; /* Default: 0x0; */
|
|
__u32 res0:22; /* Default: ; */
|
|
__u32 ahb0_clk_src_sel:2; /* Default: 0x0; */
|
|
__u32 res1:6; /* Default: ; */
|
|
} bits;
|
|
} AHB0_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 ahb1_clk_div_ratio:2; /* Default: 0x0; */
|
|
__u32 res0:22; /* Default: ; */
|
|
__u32 ahb1_clk_src_sel:2; /* Default: 0x0; */
|
|
__u32 res1:6; /* Default: ; */
|
|
} bits;
|
|
} AHB1_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 ahb2_clk_div_ratio:2; /* Default: 0x0; */
|
|
__u32 res0:22; /* Default: ; */
|
|
__u32 ahb2_clk_src_sel:2; /* Default: 0x0; */
|
|
__u32 res1:6; /* Default: ; */
|
|
} bits;
|
|
} AHB2_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 apb0_clk_div_ratio:2; /* Default: 0x0; */
|
|
__u32 res0:22; /* Default: ; */
|
|
__u32 apb0_clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 res1:7; /* Default: ; */
|
|
} bits;
|
|
} APB0_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 clk_rat_m:5; /* Default: 0x0; */
|
|
__u32 res0:11; /* Default: ; */
|
|
__u32 clk_rat_n:2; /* Default: 0x0; */
|
|
__u32 res1:6; /* Default: ; */
|
|
__u32 apb1_clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 res2:7; /* Default: ; */
|
|
} bits;
|
|
} APB1_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 cci400_clk_div_ratio:2; /* Default: 0x0; */
|
|
__u32 res0:22; /* Default: ; */
|
|
__u32 cci400_clk_src_sel:2; /* Default: 0x0; */
|
|
__u32 res1:6; /* Default: ; */
|
|
} bits;
|
|
} CCI400_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 clk_div_ratio_m:3; /* Default: 0x0; */
|
|
__u32 res0:21; /* Default: ; */
|
|
__u32 clk_src_sel:2; /* Default: 0x0; */
|
|
__u32 res1:5; /* Default: ; */
|
|
__u32 sclk_gating:1; /* Default: 0x1; */
|
|
} bits;
|
|
} ATS_CLK_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 clk_div_ratio_m:3; /* Default: 0x0; */
|
|
__u32 res0:21; /* Default: ; */
|
|
__u32 clk_src_sel:2; /* Default: 0x0; */
|
|
__u32 res1:5; /* Default: ; */
|
|
__u32 sclk_gating:1; /* Default: 0x1; */
|
|
} bits;
|
|
} TRACE_CLK_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 pll_lock_time:16; /* Default: 0x00FF; */
|
|
__u32 res0:16; /* Default: ; */
|
|
} bits;
|
|
} PLL_LOCK_CFG_REG0_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 pll_lock_time:16; /* Default: 0x00FF; */
|
|
__u32 res0:16; /* Default: ; */
|
|
} bits;
|
|
} PLL_LOCK_CFG_REG1_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
} PLL_LOCK_STATUS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_cur:5; /* Default: 0x10; */
|
|
__u32 res1:10; /* Default: ; */
|
|
__u32 vco_rst:1; /* Default: 0x1; */
|
|
} bits;
|
|
} PLL_C0_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_cur:5; /* Default: 0x10; */
|
|
__u32 res1:10; /* Default: ; */
|
|
__u32 vco_rst:1; /* Default: 0x1; */
|
|
} bits;
|
|
} PLL_C1_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x8; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_AUDIO_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x8; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_PERIPH1_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x8; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_VE_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_cp_ctrl:5; /* Default: 0x8; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_DDR_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x10; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_VIDEO1_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x10; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_VIDEO2_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x8; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_GPU_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x8; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_DE_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x8; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_ISP_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:16; /* Default: ; */
|
|
__u32 pll_bias_ctrl:5; /* Default: 0x8; */
|
|
__u32 res1:11; /* Default: ; */
|
|
} bits;
|
|
} PLL_PERIPH2_BIAS_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 c_b_out:7; /* Default: 0x0; */
|
|
__u32 c_od1:1; /* Default: 0x0; */
|
|
__u32 c_b_in:7; /* Default: 0x40; */
|
|
__u32 c_od:1; /* Default: 0x0; */
|
|
__u32 cnt_int_ctrl:7; /* Default: 0x40; */
|
|
__u32 res0:1; /* Default: ; */
|
|
__u32 vco_gain_ctrl:3; /* Default: 0x4; */
|
|
__u32 res1:1; /* Default: ; */
|
|
__u32 vco_rng_ctrl:3; /* Default: 0x4; */
|
|
__u32 res2:1; /* Default: ; */
|
|
} bits;
|
|
} PLL_C0_TUN_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 c_b_out:7; /* Default: 0x0; */
|
|
__u32 c_od1:1; /* Default: 0x0; */
|
|
__u32 c_b_in:7; /* Default: 0x40; */
|
|
__u32 c_od:1; /* Default: 0x0; */
|
|
__u32 cnt_int_ctrl:7; /* Default: 0x40; */
|
|
__u32 res0:1; /* Default: ; */
|
|
__u32 vco_gain_ctrl:3; /* Default: 0x4; */
|
|
__u32 res1:1; /* Default: ; */
|
|
__u32 vco_rng_ctrl:3; /* Default: 0x4; */
|
|
__u32 res2:1; /* Default: ; */
|
|
} bits;
|
|
} PLL_C1_TUN_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_AUDIO_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_PERIPH1_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_VE_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_DDR_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_VIDEO1_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_VIDEO2_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_GPU_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_DE_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_ISP_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 wave_bot:17; /* Default: 0x0; */
|
|
__u32 freq:2; /* Default: 0x0; */
|
|
__u32 clk_src_sel:1; /* Default: 0x0; */
|
|
__u32 wave_step:9; /* Default: 0x0; */
|
|
__u32 spr_freq_mode:2; /* Default: 0x0; */
|
|
__u32 sig_delt_pat_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} PLL_PERIPH2_PAT_CFG_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:8; /* Default: ; */
|
|
__u32 divider_m:5; /* Default: 0x0; */
|
|
__u32 res1:7; /* Default: ; */
|
|
__u32 divider_n:2; /* Default: 0x0; */
|
|
__u32 res2:2; /* Default: ; */
|
|
__u32 clk_out_src_sel:2; /* Default: 0x0; */
|
|
__u32 res3:5; /* Default: ; */
|
|
__u32 clk_out_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} CLK_OUTA_REG_t;
|
|
|
|
typedef union {
|
|
__u32 dwval;
|
|
struct {
|
|
__u32 res0:8; /* Default: ; */
|
|
__u32 divider_m:5; /* Default: 0x0; */
|
|
__u32 res1:7; /* Default: ; */
|
|
__u32 divider_n:2; /* Default: 0x0; */
|
|
__u32 res2:2; /* Default: ; */
|
|
__u32 clk_out_src_sel:2; /* Default: 0x0; */
|
|
__u32 res3:5; /* Default: ; */
|
|
__u32 clk_out_en:1; /* Default: 0x0; */
|
|
} bits;
|
|
} CLK_OUTB_REG_t;
|
|
|
|
typedef struct __CCMU_REG_LIST {
|
|
/*pll1 - pll12 */
|
|
volatile PLL_C0_CFG_REG_t Pll_C0_Cfg; /*0x0000 */
|
|
volatile PLL_C1_CFG_REG_t Pll_C1_Cfg; /*0x0004 */
|
|
volatile PLL_AUDIO_CFG_REG_t Pll_Audio_Cfg; /*0x0008 */
|
|
volatile PLL_PERIPH1_CFG_REG_t Pll_Periph1_Cfg; /*0x000c */
|
|
volatile PLL_VE_CFG_REG_t Pll_Ve_Cfg; /*0x0010 */
|
|
volatile PLL_DDR_CFG_REG_t Pll_Ddr_Cfg; /*0x0014 */
|
|
volatile PLL_VIDEO1_CFG_REG_t Pll_Video1_Cfg; /*0x0018 */
|
|
volatile PLL_VIDEO2_CFG_REG_t Pll_Video2_Cfg; /*0x001c */
|
|
volatile PLL_GPU_CFG_REG_t Pll_Gpu_Cfg; /*0x0020 */
|
|
volatile PLL_DE_CFG_REG_t Pll_De_Cfg; /*0x0024 */
|
|
volatile PLL_ISP_CFG_REG_t Pll_Isp_Cfg; /*0x0028 */
|
|
volatile PLL_PERIPH2_CFG_REG_t Pll_Periph2_Cfg; /*0x002c */
|
|
/**/ volatile __u32 reserved0[8]; /*0x30-0x4c, reserved */
|
|
volatile CPU_CLK_SRC_REG_t Cpu_Clk_Src; /*0x0050 */
|
|
volatile AXI0_CFG_REG_t Axi0_Cfg; /*0x0054 */
|
|
volatile AXI1_CFG_REG_t Axi1_Cfg; /*0x0058 */
|
|
volatile GTCLK_CFG_REG_t Gtclk_Cfg; /*0x005c */
|
|
volatile AHB0_CFG_REG_t Ahb0_Cfg; /*0x0060 */
|
|
volatile AHB1_CFG_REG_t Ahb1_Cfg; /*0x0064 */
|
|
volatile AHB2_CFG_REG_t Ahb2_Cfg; /*0x0068 */
|
|
volatile __u32 reserved1; /*0x6c */
|
|
volatile APB0_CFG_REG_t Apb0_Cfg; /*0x0070 */
|
|
volatile APB1_CFG_REG_t Apb1_Cfg; /*0x0074 */
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volatile CCI400_CFG_REG_t Cci400_Cfg; /*0x0078 */
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volatile __u32 reserved2; /*0x7c */
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volatile ATS_CLK_REG_t Ats_Clk; /*0x0080 */
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volatile TRACE_CLK_REG_t Trace_Clk; /*0x0084 */
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volatile __u32 reserved3[2]; /*0x88-0x8c */
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volatile PLL_LOCK_CFG_REG0_t Pll_Lock_Cfg; /*0x0090 */
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volatile PLL_LOCK_CFG_REG1_t Pll_Lock_Cfg_1; /*0x0094 */
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volatile __u32 reserved4; /*0x98 */
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volatile PLL_LOCK_STATUS_REG_t Pll_Lock_Status; /*0x009c */
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/**/ volatile PLL_C0_BIAS_REG_t Pll_C0_Bias; /*0x00a0 */
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volatile PLL_C1_BIAS_REG_t Pll_C1_Bias; /*0x00a4 */
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volatile PLL_AUDIO_BIAS_REG_t Pll_Audio_Bias; /*0x00a8 */
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volatile PLL_PERIPH1_BIAS_REG_t Pll_Periph1_Bias; /*0x00ac */
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volatile PLL_VE_BIAS_REG_t Pll_Ve_Bias; /*0x00b0 */
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volatile PLL_DDR_BIAS_REG_t Pll_Ddr_Bias; /*0x00b4 */
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volatile PLL_VIDEO1_BIAS_REG_t Pll_Vedio1_Bias; /*0x00b8 */
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volatile PLL_VIDEO2_BIAS_REG_t Pll_Vedio2_Bias; /*0x00bc */
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volatile PLL_GPU_BIAS_REG_t Pll_Gpu_Bias; /*0x00c0 */
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volatile PLL_DE_BIAS_REG_t Pll_De_Bias; /*0x00c4 */
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volatile PLL_ISP_BIAS_REG_t Pll_Isp_Bias; /*0x00c8 */
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volatile PLL_PERIPH2_BIAS_REG_t Pll_Periph2_Bias; /*0x00cc */
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volatile __u32 reserved5[4]; /*0xd0-0xdc */
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volatile PLL_C0_TUN_REG_t Pll_C0_Tun; /*0x00e0 */
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volatile PLL_C1_TUN_REG_t Pll_C1_Tun; /*0x00e4 */
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volatile __u32 reserved6[7]; /*0xe8-0x104 */
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volatile PLL_AUDIO_PAT_CFG_REG_t Pll_Audio_Pat_Cfg; /*0x0108 */
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volatile PLL_PERIPH1_PAT_CFG_REG_t Pll_Periph1_Pat_Cfg; /*0x010c */
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volatile PLL_VE_PAT_CFG_REG_t Pll_Ve_Pat_Cfg; /*0x0110 */
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volatile PLL_DDR_PAT_CFG_REG_t Pll_Ddr_Pat_Cfg; /*0x0114 */
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volatile PLL_VIDEO1_PAT_CFG_REG_t Pll_Video1_Pat_Cfg; /*0x0118 */
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volatile PLL_VIDEO2_PAT_CFG_REG_t Pll_Video2_Pat_Cfg; /*0x011c */
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volatile PLL_GPU_PAT_CFG_REG_t Pll_Gpu_Pat_Cfg; /*0x0120 */
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volatile PLL_DE_PAT_CFG_REG_t Pll_De_Pat_Cfg; /*0x0124 */
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volatile PLL_ISP_PAT_CFG_REG_t Pll_Isp_Pat_Cfg; /*0x0128 */
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volatile PLL_PERIPH2_PAT_CFG_REG_t Pll_Periph2_Pat_Cfg; /*0x012c */
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volatile __u32 reserved7[20]; /*0x130-0x17c */
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volatile CLK_OUTA_REG_t Clk_Outa; /*0x0180 */
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volatile CLK_OUTB_REG_t Clk_Outb; /*0x0184 */
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} __ccmu_reg_list_t;
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/**/
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/* Detail information of registers*/
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/**/ typedef struct __CCMU_MOD_REG_LIST {
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volatile __u32 nand0_sclk0_cfg; /*0x0000 */
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volatile __u32 nand0_sclk1_cfg; /*0x0004 */
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volatile __u32 nand1_sclk0_cfg; /*0x0008 */
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volatile __u32 nand1_sclk1_cfg; /*0x000C */
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volatile __u32 sd0_clk; /*0x0010 */
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volatile __u32 sd1_clk; /*0x0014 */
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volatile __u32 sd2_clk; /*0x0018 */
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volatile __u32 sd3_clk; /*0x001C */
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volatile __u32 reserved0[2]; /*0x0020-0x24 */
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volatile __u32 ts_clk; /*0x0028 */
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volatile __u32 ss_clk; /*0x002C */
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volatile __u32 spi0_clk; /*0x0030 */
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volatile __u32 spi1_clk; /*0x0034 */
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volatile __u32 spi2_clk; /*0x0038 */
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volatile __u32 spi3_clk; /*0x003C */
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volatile __u32 daudio0_clk; /*0x0040 */
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volatile __u32 daudio1_clk; /*0x0044 */
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volatile __u32 reserved1; /*0x0048, reserved */
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volatile __u32 spdif_clk; /*0x004C */
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volatile __u32 usbphy0_cfg; /*0x0050 */
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volatile __u32 reserved2[11]; /*0x0054-0x7c, reserved */
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volatile __u32 mdfs_clk; /*0x0080 */
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volatile __u32 dram_cfg; /*0x0084 */
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volatile __u32 reserved3[2]; /*0x0088-0x8c, reserved */
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volatile __u32 de_sclk_cfg; /*0x0090 */
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volatile __u32 edp_sclk_cfg; /*0x0094 */
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volatile __u32 mp_clk; /*0x0098 */
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volatile __u32 lcd0_clk; /*0x009c */
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volatile __u32 lcd1_clk; /*0x00a0 */
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volatile __u32 reserved4; /*0x00a4, reserved */
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volatile __u32 mipi_dsi_clk0; /*0x00A8 */
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volatile __u32 mipi_dsi_clk1; /*0x00AC */
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volatile __u32 hdmi_sclk; /*0x00B0 */
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volatile __u32 hdmi_slow_clk0; /*0x00B4 */
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volatile __u32 reserved5; /*0x00b8, reserved */
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volatile __u32 mipi_csi_cfg; /*0x00BC */
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volatile __u32 csi_isp_clk; /*0x00C0 */
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volatile __u32 csi0_mclk; /*0x00C4 */
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volatile __u32 csi1_mclk; /*0x00C8 */
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volatile __u32 fd_clk; /*0x00CC */
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volatile __u32 ve_clk; /*0x00D0 */
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volatile __u32 avs_clk; /*0x00D4 */
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volatile __u32 reserved6[6]; /*0x00d8 - 0xec, reserved */
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volatile __u32 gpu_core_clk; /*0x00F0 */
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volatile __u32 gpu_mem_clk; /*0x00F4 */
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volatile __u32 gpu_axi_clk; /*0x00F8 */
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volatile __u32 reserved7; /*0x00fc, reserved */
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volatile __u32 sata_clk; /*0x0100 */
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volatile __u32 ac97_clk; /*0x0104 */
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volatile __u32 mipi_hsi_clk; /*0x0108 */
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volatile __u32 gp_adc; /*0x010C */
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volatile __u32 cir_tx_clk; /*0x0110 */
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volatile __u32 reserved8[27]; /*0x0114-0x17c, reserved */
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volatile __u32 ahb0_gating; /*0x0180 */
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volatile __u32 ahb1_gating; /*0x0184 */
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volatile __u32 ahb2_gating; /*0x0188 */
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volatile __u32 reserved9; /*0x018c, reserved */
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volatile __u32 apb0_gating; /*0x0190 */
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volatile __u32 apb1_gating; /*0x0194 */
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volatile __u32 reserved10[2]; /*0x0198, 0x19c, reserved */
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volatile __u32 ahb0_rst; /*0x01A0 */
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volatile __u32 ahb1_rst; /*0x01A4 */
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volatile __u32 ahb2_rst; /*0x01A8 */
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volatile __u32 reserved11; /*0x01ac, reserved */
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volatile __u32 apb0_rst; /*0x01B0 */
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volatile __u32 apb1_rst; /*0x01B4 */
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} __ccmu_mod_reg_list_t;
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#endif /* #ifndef __MEM_CCMU_SUN9IW1P1_H__ */
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