162 lines
4.5 KiB
C
162 lines
4.5 KiB
C
/*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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*********************************************************************************************************
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* LINUX-KERNEL
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* AllWinner Linux Platform Develop Kits
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* Kernel Module
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*
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* (c) Copyright 2011-2015, gq.yang China
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* All Rights Reserved
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*
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* File : mem_clk.h
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* By : gq.yang
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* Version : v1.0
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* Date : 2012-11-31 15:23
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* Descript:
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* Update : date auther ver notes
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*********************************************************************************************************
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*/
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#ifndef __MEM_CLK_H__
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#define __MEM_CLK_H__
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#include "pm.h"
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#if defined(CONFIG_ARCH_SUN8I) || \
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defined(CONFIG_ARCH_SUN50IW1P1) || \
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defined(CONFIG_ARCH_SUN50IW2P1) || \
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defined(CONFIG_ARCH_SUN50IW3P1) || \
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defined(CONFIG_ARCH_SUN50IW6P1)
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struct clk_div_t {
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__u32 axi_div; /* division of axi clock, divide cpu clock */
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__u32 ahb_apb_div; /* ahb1/apb1 clock divide ratio */
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};
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struct clk_misc_t {
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__u32 pll1_bias; /*0x220 */
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__u32 pll6_bias; /*0x234, not need restore. */
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__u32 pll1_tun; /*0x250 */
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#if defined(CONFIG_ARCH_SUN8IW5P1) || \
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defined(CONFIG_ARCH_SUN50IW1P1) || \
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defined(CONFIG_ARCH_SUN50IW2P1) || \
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defined(CONFIG_ARCH_SUN50IW3P1) || \
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defined(CONFIG_ARCH_SUN50IW6P1)
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__u32 Pll3Ctl; /*0x10, vedio */
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__u32 Pll4Ctl; /*0x18, ve */
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__u32 PllVedioBias; /*0x228, pll vedio bias reg */
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__u32 PllVeBias; /*0x22c, pll ve bias reg */
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__u32 PllVedioPattern; /*0x288, pll vedio pattern reg */
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__u32 PllVePattern; /*0x28c, pll ve pattern reg */
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#endif
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#ifdef CONFIG_ARCH_SUN8IW6P1
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__u32 Pll_C1_Bias; /*0x0238 */
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__u32 PllC1Tun; /*0x0254 */
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__u32 PllC1Ctl; /*0x0004 */
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__u32 Pll3Ctl; /*0x10, video */
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__u32 Pll4Ctl; /*0x18, ve */
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__u32 Pll6Ctl; /*0x28, periph */
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__u32 PllVideo0Bias; /*0x228, pll video0 bias reg */
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__u32 PllVeBias; /*0x22c, pll ve bias reg */
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__u32 PllPeriphBias; /*0x234, pll periph bias reg */
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__u32 PllVideo0Reg0Pattern; /*0x288, pll video0 pattern reg */
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__u32 PllVideo0Reg1Pattern; /*0x288, pll video0 pattern reg */
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__u32 Apb2Div; /*0x58, apb2 clk divide ratio */
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#endif
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};
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struct pll_factor_t {
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__u8 FactorN;
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__u8 FactorK;
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__u8 FactorM;
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__u8 FactorP;
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__u32 Pll;
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};
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struct clk_state {
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__ccmu_reg_list_t *CmuReg;
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__u32 ccu_reg_back[15];
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};
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#elif defined(CONFIG_ARCH_SUN9IW1P1)
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struct clk_div_t {
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__u32 Axi0_Cfg;
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__u32 Axi1_Cfg;
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};
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struct clk_misc_t {
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__u32 Pll_C0_Bias;
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__u32 Pll_Periph1_Bias;
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__u32 Pll_Periph2_Bias;
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__u32 Pll_C0_Tun;
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__u32 Pll_C1_Bias; /*0x00a4 */
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__u32 Pll_Vedio1_Bias; /*0x00b8 */
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__u32 Pll_Vedio2_Bias; /*0x00bc */
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__u32 Pll_C1_Tun; /*0x00e4 */
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__u32 Pll_Video1_Pat_Cfg; /*0x0118 */
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__u32 Pll_Video2_Pat_Cfg; /*0x011c */
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__u32 Pll_C0_Cfg; /*0x0000 */
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__u32 Pll_C1_Cfg; /*0x0004 */
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__u32 Pll_Video1_Cfg; /*0x0018 */
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__u32 Pll_Video2_Cfg; /*0x001c */
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};
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struct pll_factor_t {
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__u8 FactorN;
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__u8 FactorK;
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__u8 FactorM;
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__u8 FactorP;
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__u32 Pll;
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};
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struct clk_state {
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__ccmu_reg_list_t *ccm_reg;
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__ccmu_reg_list_t ccm_reg_backup;
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__ccmu_mod_reg_list_t *ccm_mod_reg;
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__ccmu_mod_reg_list_t ccm_mod_reg_backup;
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};
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#endif
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__s32 mem_clk_save(struct clk_state *pclk_state);
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__s32 mem_clk_restore(struct clk_state *pclk_state);
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__ccmu_reg_list_t *mem_clk_init(__u32 mmu_flag);
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__ccmu_reg_list_t *mem_get_ba(void);
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__s32 mem_clk_setdiv(struct clk_div_t *clk_div);
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__s32 mem_clk_getdiv(struct clk_div_t *clk_div);
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__s32 mem_clk_set_pll_factor(struct pll_factor_t *pll_factor);
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__s32 mem_clk_get_pll_factor(struct pll_factor_t *pll_factor);
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__s32 mem_clk_get_misc(struct clk_misc_t *clk_misc);
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__s32 mem_clk_set_misc(struct clk_misc_t *clk_misc);
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#ifdef CONFIG_ARCH_SUN8IW8P1
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void mem_pio_clk_src_init(void);
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void mem_pio_clk_src_exit(void);
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#else
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static inline void mem_pio_clk_src_init(void)
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{
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return;
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}
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static inline void mem_pio_clk_src_exit(void)
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{
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return;
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}
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#endif
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__u32 mem_clk_get_cpu_freq(void);
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#endif /*__MEM_CLK_H__*/
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