562 lines
17 KiB
ArmAsm
562 lines
17 KiB
ArmAsm
#include "./pm_assembler_i.h"
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/*save_sp*/
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/*save_sp_nommu*/
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/*restore_sp*/
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/*get_sp*/
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.text
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.globl save_sp
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save_sp:
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mov r0, r13
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ldr r13, =SP_IN_SRAM
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mov pc, lr
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.text
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.globl save_sp_nommu
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save_sp_nommu:
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mov r0, r13
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ldr r13, =SP_IN_SRAM_PA
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mov pc, lr
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.text
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.globl restore_sp
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restore_sp:
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mov r13, r0
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mov pc, lr
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.text
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.globl get_sp
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get_sp:
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mov r0, r13
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mov pc, lr
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.align 4
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.globl get_cur_cluster_id
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get_cur_cluster_id:
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mrc p15, 0, r0, c0, c0, 5 ;/*Read CPU ID register*/
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ubfx r0, r0, #8, #4 ;/* if r0 = 1, then mean cluster1*/
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/* return*/
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mov pc, lr
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/*--------------------------------cache related api: ----------------------------------------------- */
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/*invalidate_dcache*/
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/*invalidate_icache*/
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/*flush_dcache*/
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/*flush_icache*/
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/*disable_cache*/
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/*disable_dcache*/
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/*disable_icache*/
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/*disable_l2cache*/
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/*enable_cache*/
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/*enable_icache*/
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.align 4
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.text
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.globl invalidate_dcache /*can not use push and pop, because inval will discard the data in the stack*/
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invalidate_dcache:
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/* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) */
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dmb /* ensure ordering with previous memory accesses */
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MRC p15, 1, r0, c0, c0, 1 /*read clidr */
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ANDS r3, r0, #0x7000000 /*extract loc from clidr */
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MOV r3, r3, lsr #23 /*left align loc bit field */
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BEQ inv_finished /*if loc is 0, then no need to clean */
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mov r10, #0 /*start clean at cache level 0 */
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inv_loop1:
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ADD r2, r10, r10, lsr #1 /*work out 3x current cache level */
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MOV r1, r0, lsr r2 /*extract cache type bits from clidr */
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AND r1, r1, #7 /*mask of the bits for current cache only */
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CMP r1, #2 /*see what cache we have at this level */
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BLT inv_skip /*skip if no cache, or just i-cache */
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MCR p15, 2, r10, c0, c0, 0 /*select current cache level in cssr */
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ISB /*isb to sych the new cssr & csidr */
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MRC p15, 1, r1, c0, c0, 0 /*read the new csidr */
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AND r2, r1, #7 /*extract the length of the cache lines */
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ADD r2, r2, #4 /*add 4 (line length offset) */
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LDR r4, =0x3ff
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ANDS r4, r4, r1, lsr #3 /*find maximum number on the way size */
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CLZ r5, r4 /*find bit position of way size increment */
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LDR r7, =0x7fff
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ANDS r7, r7, r1, lsr #13 /*extract max number of the index size */
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inv_loop2:
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MOV r9, r4 /*create working copy of max way size */
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inv_loop3:
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ORR r11, r10, r9, lsl r5 /*factor way and cache number into r11 */
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ORR r11, r11, r7, lsl r2 /*factor index number into r11 */
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MCR p15, 0, r11, c7, c6, 2 /*invalidate by set/way */
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SUBS r9, r9, #1 /*decrement the way */
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BGE inv_loop3 /* */
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SUBS r7, r7, #1 /*decrement the index */
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BGE inv_loop2 /* */
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inv_skip: /* */
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ADD r10, r10, #2 /*increment cache number */
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CMP r3, r10 /* */
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BGT inv_loop1 /* */
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inv_finished: /* */
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MOV r10, #0 /*swith back to cache level 0 */
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MCR p15, 2, r10, c0, c0, 0 /*select current cache level in cssr */
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dsb
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ISB /* */
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MOV pc, lr /* */
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.text
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.globl invalidate_icache
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invalidate_icache:
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mov r0, #0
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mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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dsb
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ISB
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mov pc, lr
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.text
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.globl flush_dcache
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flush_dcache:
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push {r0-r12}
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dmb /* ensure ordering with previous memory accesses */
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MRC p15, 1, r0, c0, c0, 1 /*read clidr */
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ANDS r3, r0, #0x7000000 /*extract loc from clidr */
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MOV r3, r3, lsr #23 /*left align loc bit field */
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BEQ finished /*if loc is 0, then no need to clean */
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mov r10, #0 /*start clean at cache level 0 */
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loop1:
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ADD r2, r10, r10, lsr #1 /*work out 3x current cache level */
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MOV r1, r0, lsr r2 /*extract cache type bits from clidr */
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AND r1, r1, #7 /*mask of the bits for current cache only */
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CMP r1, #2 /*see what cache we have at this level */
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BLT skip /*skip if no cache, or just i-cache */
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MCR p15, 2, r10, c0, c0, 0 /*select current cache level in cssr */
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ISB /*isb to sych the new cssr & csidr */
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MRC p15, 1, r1, c0, c0, 0 /*read the new csidr */
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AND r2, r1, #7 /*extract the length of the cache lines */
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ADD r2, r2, #4 /*add 4 (line length offset) */
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LDR r4, =0x3ff
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ANDS r4, r4, r1, lsr #3 /*find maximum number on the way size */
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CLZ r5, r4 /*find bit position of way size increment */
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LDR r7, =0x7fff
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ANDS r7, r7, r1, lsr #13 /*extract max number of the index size */
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loop2:
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MOV r9, r4 /*create working copy of max way size */
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loop3:
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ORR r11, r10, r9, lsl r5 /*factor way and cache number into r11 */
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ORR r11, r11, r7, lsl r2 /*factor index number into r11 */
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MCR p15, 0, r11, c7, c14, 2 /*clean & invalidate by set/way */
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SUBS r9, r9, #1 /*decrement the way */
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BGE loop3 /* */
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SUBS r7, r7, #1 /*decrement the index */
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BGE loop2 /* */
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skip: /* */
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ADD r10, r10, #2 /*increment cache number */
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CMP r3, r10 /* */
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BGT loop1 /* */
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finished: /* */
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MOV r10, #0 /*swith back to cache level 0 */
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MCR p15, 2, r10, c0, c0, 0 /*select current cache level in cssr */
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dsb
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ISB /* */
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pop {r0-r12}
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MOV pc, lr /* */
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.text
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.globl flush_icache
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flush_icache:
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push {r0-r3}
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MOV r0, #0
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MCR p15, 0, r0, c7, c5, 0 /*Instruction cache invalidate all to PoU */
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MCR p15, 0, r0, c7, c1, 0 /*Instruction cache invalidate all to PoUa Inner Shareable*/
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MCR p15, 0, r0, c7, c1, 6 /*Branch predictor invalidate all Inner Shareable*/
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ISB
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dsb
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pop {r0-r3}
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MOV pc, lr
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.text
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.globl disable_cache
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disable_cache:
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push {r0-r3}
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MRC p15, 0, r0, c1, c0, 0 /*read cr */
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BIC r0, r0, #0x1 << 12
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BIC r0, r0, #0x1 << 2
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MCR p15, 0, r0, c1, c0, 0 /*disable cache */
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ISB
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pop {r0-r3}
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MOV pc, lr
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.text
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.globl disable_dcache
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disable_dcache:
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push {r0-r3}
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MRC p15, 0, r0, c1, c0, 0 /*read cr */
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BIC r0, r0, #(0x1 << 2)
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MCR p15, 0, r0, c1, c0, 0 /*disable dcache */
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ISB
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pop {r0-r3}
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MOV pc, lr
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.text
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.globl disable_icache
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disable_icache:
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push {r0-r3}
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MRC p15, 0, r0, c1, c0, 0 /*read cr */
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BIC r0, r0, #(0x1 << 12)
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MCR p15, 0, r0, c1, c0, 0 /*disable icache */
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ISB
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pop {r0-r3}
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MOV pc, lr
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.text
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.globl disable_l2cache
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disable_l2cache:
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push {r0-r3}
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MRC p15, 0, r0, c1, c0, 1 /*read acr */
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BIC r0, r0, #0x1 << 1
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MCR p15, 0, r0, c1, c0, 1 /*disable l2cache */
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ISB
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pop {r0-r3}
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MOV pc, lr
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.text
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.globl enable_cache
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enable_cache:
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push {r0-r3}
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MRC p15, 0, r0, c1, c0, 0 /*read cr */
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ORR r0, r0, #0x1 << 12
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ORR r0, r0, #0x1 << 2
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MCR p15, 0, r0, c1, c0, 0 /*enable cache */
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ISB
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pop {r0-r3}
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MOV pc, lr
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.text
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.globl enable_icache
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enable_icache:
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push {r0-r3}
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MRC p15, 0, r0, c1, c0, 0 /*read cr */
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ORR r0, r0, #(0x1 << 12)
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MCR p15, 0, r0, c1, c0, 0 /*disable dcache */
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ISB
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pop {r0-r3}
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MOV pc, lr
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/*--------------------------------------prediction----------------------------------------*/
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/*invalidate_branch_predictor*/
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/*disable_program_flow_prediction*/
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/*enable_program_flow_prediction*/
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.text
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.globl invalidate_branch_predictor
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invalidate_branch_predictor:
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push {r0-r3}
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MOV r0, #0
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MCR p15, 0, r0, c7, c5, 6 /*(invalidate entire branch predictor array)*/
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ISB
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pop {r0-r3}
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MOV pc, lr
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.text
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.globl disable_program_flow_prediction
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disable_program_flow_prediction:
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push {r0-r3}
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MRC p15, 0, r0, c1, c0, 0 /*read cr */
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BIC r0, r0, #0x800
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MCR p15, 0, r0, c1, c0, 0 /*disable program_flow_prediction */
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ISB
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pop {r0-r3}
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MOV pc, lr
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.text
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.globl enable_program_flow_prediction
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enable_program_flow_prediction:
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push {r0-r3}
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MRC p15, 0, r0, c1, c0, 0 /*read cr */
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ORR r0, r0, #0x800
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MCR p15, 0, r0, c1, c0, 0 /*disable program_flow_prediction */
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ISB
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pop {r0-r3}
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MOV pc, lr
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/*-------------------------------------tlb related api:----------------------------------------*/
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/*mem_flush_tlb*/
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/*mem_preload_tlb*/
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.text
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.globl mem_flush_tlb
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mem_flush_tlb:
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push {r0-r3}
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MOV r0, #0
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/*instruction entire instruction tlb*/
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mcr p15, 0, r0, c8, c5, 0
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/* invalid entire data tlb */
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mcr p15, 0, r0, c8, c6, 0
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/*invalidate entire unified TLB inner shareable*/
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mcr p15, 0, r0, c8, c3, 0
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dsb
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ISB
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pop {r0-r3}
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mov pc, lr
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.text
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.globl mem_preload_tlb
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mem_preload_tlb:
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push {r0-r3}
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#if defined(CONFIG_ARCH_SUN8IW10P1)
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/*32k*/
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mov r2, #0xc000
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mov r3, #0xf0000000
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preload_continue:
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movt r2, #0xf000
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ldr r1, [r3], #0x400
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cmp r3, r2
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bne preload_continue
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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/*48k*/
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ldr r0, =IO_ADDRESS(AW_SRAM_A1_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A1_BASE + 0x1000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A1_BASE + 0x2000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A1_BASE + 0x3000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x1000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x2000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x3000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A3_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A3_BASE + 0x1000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A3_BASE + 0x2000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A3_BASE + 0x3000) /*<EFBFBD><EFBFBD><EFBFBD><EFBFBD>SRAM_A4 3K*/
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ldr r1, [r0]
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#elif defined(CONFIG_ARCH_SUN50IW1P1) || defined(CONFIG_ARCH_SUN50IW2P1) || \
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defined(CONFIG_ARCH_SUN50IW3P1) || defined(CONFIG_ARCH_SUN50IW6P1)
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/*80k*/
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x1000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x2000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x3000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x4000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x5000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x6000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x7000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x8000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x9000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0xa000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0xb000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0xc000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0xd000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0xe000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0xf000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x10000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x11000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x12000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SRAM_A2_BASE + 0x13000)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_MSGBOX_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_SPINLOCK_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_R_PRCM_BASE)
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ldr r1, [r0]
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#endif
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ldr r0, =IO_ADDRESS(AW_PIO_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_UART0_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_RTC_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_CCM_BASE)
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ldr r1, [r0]
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ldr r0, =IO_ADDRESS(AW_TWI0_BASE)
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ldr r1, [r0]
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dsb
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isb
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pop {r0-r3}
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mov pc, lr
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/*--------------------------------------mmu----------------------------------------*/
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/*disable_mmu*/
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/*enable_mmu*/
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.text
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.globl disable_mmu
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disable_mmu:
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/*read cr*/
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MRC p15, 0, r1, c1, c0, 0
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BIC r1, #0x1000
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BIC r1, #0x0005
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b __turn_mmu_off
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.align 5
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.type __turn_mmu_off, %function
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__turn_mmu_off:
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/*write cr: disable cache and mmu*/
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MCR p15, 0, r1, c1, c0, 0
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/*read id reg*/
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mrc p15, 0, r3, c0, c0, 0
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mov r3, r3
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mov r3, r3
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/*return*/
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mov pc, lr
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.text
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.globl enable_mmu
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enable_mmu:
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/*read cr*/
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MRC p15, 0, r1, c1, c0, 0
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ORR r1, #0x1000
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ORR r1, #0x0005
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b __turn_mmu_on
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.align 5
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||
.type __turn_mmu_on, %function
|
||
__turn_mmu_on:
|
||
/*write cr: enable cache and mmu*/
|
||
MCR p15, 0, r1, c1, c0, 0
|
||
/*read id reg*/
|
||
mrc p15, 0, r3, c0, c0, 0
|
||
mov r3, r3
|
||
mov r3, r3
|
||
/*return*/
|
||
mov pc, lr
|
||
|
||
/*----------------------------------------pc related api:---------------------------------------*/
|
||
/*jump_to_suspend*/
|
||
/*jump_to_resume*/
|
||
/*jump_to_resume0*/
|
||
/*jump_to_resume0_nommu*/
|
||
|
||
.text
|
||
.globl jump_to_suspend
|
||
jump_to_suspend:
|
||
/*enable 0x0000 <--> 0x0000 mapping */
|
||
/*write ttbr0*/
|
||
mcr p15, 0, r0, c2, c0, 0
|
||
dsb
|
||
isb
|
||
|
||
mov pc, r1
|
||
|
||
.align 4
|
||
.text
|
||
.globl jump_to_resume
|
||
jump_to_resume:
|
||
/*before jump to resume:
|
||
* 1st: invalidate the data
|
||
* 2nd: restore r0-r13.
|
||
* 3rd: jump (para 1).
|
||
*/
|
||
/* Set the return pointer */
|
||
mov r12, r0
|
||
mov r8, r1
|
||
bl invalidate_dcache
|
||
mov r1, r8
|
||
mov lr, r12
|
||
ldmia r1, {r0 - r13}
|
||
mov pc, lr
|
||
|
||
.align 4
|
||
.globl jump_to_resume0
|
||
jump_to_resume0:
|
||
/* Set the return pointer */
|
||
mov lr, r0
|
||
mov pc, lr
|
||
|
||
.align 4
|
||
|
||
.globl jump_to_resume0_nommu
|
||
jump_to_resume0_nommu:
|
||
/*read cr*/
|
||
MRC p15, 0, r1, c1, c0, 0
|
||
BIC r1, #0x1000
|
||
BIC r1, #0x0007
|
||
/*write cr: disable cache and mmu*/
|
||
MCR p15, 0, r1, c1, c0, 0
|
||
/*read id reg*/
|
||
mrc p15, 0, r3, c0, c0, 0
|
||
mov r3, r3
|
||
mov r3, r3
|
||
/* Set the return pointer */
|
||
mov lr, r0
|
||
isb
|
||
|
||
mov pc, lr
|
||
|
||
.align 4
|
||
.global disable_prefetch
|
||
disable_prefetch:
|
||
/*
|
||
* Disable all forms of branch prediction.
|
||
* actually, we do not need this ops, because it is always enabled when the MMU is enabled.
|
||
* so we mask the code below.
|
||
*
|
||
* mrc p15, 0, r1, c1, c0, 0
|
||
* bic r1, r1, #(0x1 << 11)
|
||
* mcr p15, 0, r1, c1, c0, 0
|
||
*/
|
||
|
||
/*
|
||
* disable data prefetch
|
||
* including:
|
||
* Disable optimized data memory barrier behavior. Disable Lx data cache read-allocate mode.
|
||
* disable data prefetch.
|
||
* Disable Distributed Virtual memory transaction.
|
||
* Disable dual issue.
|
||
*/
|
||
mrc p15, 0, r1, c1, c0, 1
|
||
mov r0, r1
|
||
orr r1, r1, #(0x7 << 10)
|
||
bic r1, r1, #(0x3 << 13)
|
||
orr r1, r1, #(0x1 << 15)
|
||
orr r1, r1, #(0xE << 28)
|
||
mcr p15, 0, r1, c1, c0, 1
|
||
|
||
/* return*/
|
||
mov pc, lr
|
||
|
||
|
||
.align 4
|
||
.global restore_prefetch
|
||
restore_prefetch:
|
||
/*
|
||
* revert disable_prefetch ops.
|
||
*/
|
||
mcr p15, 0, r0, c1, c0, 1
|
||
|
||
/* return*/
|
||
mov pc, lr
|