476 lines
12 KiB
C
476 lines
12 KiB
C
/*
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* Copyright (c) 2011-2020 yanggq.young@allwinnertech.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include "pm_o.h"
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static struct clk_state saved_clk_state;
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static struct gpio_state saved_gpio_state;
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static struct ccm_state saved_ccm_state;
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static struct sram_state saved_sram_state;
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static void mem_enable_nmi(void);
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#define SUNXI_IRQ_NMI_ADDR (0xf1c00038)
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static void mem_enable_nmi(void)
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{
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u32 tmp = 0;
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tmp = readl((volatile void *)SUNXI_IRQ_NMI_ADDR);
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tmp |= ((0x0000001));
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writel(tmp, (volatile void *)SUNXI_IRQ_NMI_ADDR);
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return;
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}
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void init_wakeup_src(unsigned int event, unsigned int gpio_enable_bitmap, unsigned int cpux_gpiog_bitmap)
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{
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/* config int src. */
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/* initialise standby modules */
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY)) {
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/* don't need init serial ,depend kernel?
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*serial_init(0);
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*/
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pr_info("final standby wakeup src config = 0x%x.\n", event);
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}
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/* init some system wake source */
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if (event & CPU0_WAKEUP_MSGBOX) {
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY)) {
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/* for tips info */
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pr_info("enable CPU0_WAKEUP_MSGBOX.\n");
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}
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mem_enable_int(INT_SOURCE_MSG_BOX);
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}
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if (event & CPU0_WAKEUP_EXINT) {
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY))
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pr_info("enable CPU0_WAKEUP_EXINT.\n");
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mem_enable_int(INT_SOURCE_EXTNMI);
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mem_enable_nmi();
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}
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if (event & CPU0_WAKEUP_TIMEOUT) {
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY))
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pr_info("enable CPU0_WAKEUP_TIMEOUT.\n");
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/* set timer for power off */
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if (standby_info.standby_para.timeout) {
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pr_info("wakeup sys in %d sec later.\n",
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standby_info.standby_para.timeout);
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mem_tmr_set(standby_info.standby_para.timeout);
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mem_enable_int(INT_SOURCE_TIMER0);
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}
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}
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if (event & CPU0_WAKEUP_ALARM) {
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY))
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pr_info("enable CPU0_WAKEUP_ALARM.\n");
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mem_enable_int(INT_SOURCE_ALARM);
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}
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if (event & CPU0_WAKEUP_KEY) {
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY))
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pr_info("enable CPU0_WAKEUP_KEY.\n");
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mem_key_init();
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mem_enable_int(INT_SOURCE_LRADC);
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}
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if (event & CPU0_WAKEUP_IR) {
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY))
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pr_info("enable CPU0_WAKEUP_IR.\n");
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mem_ir_init();
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mem_enable_int(INT_SOURCE_IR0);
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mem_enable_int(INT_SOURCE_IR1);
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}
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if (event & CPUS_WAKEUP_USBMOUSE) {
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY))
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pr_info("enable CPUS_WAKEUP_USBMOUSE.\n");
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mem_usb_init();
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mem_enable_int(INT_SOURCE_USBOTG);
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mem_enable_int(INT_SOURCE_USBEHCI0);
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mem_enable_int(INT_SOURCE_USBEHCI1);
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mem_enable_int(INT_SOURCE_USBEHCI2);
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mem_enable_int(INT_SOURCE_USBOHCI0);
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mem_enable_int(INT_SOURCE_USBOHCI1);
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mem_enable_int(INT_SOURCE_USBOHCI2);
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}
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if (event & CPUS_WAKEUP_GPIO) {
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY))
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pr_info("enable CPUS_WAKEUP_GPIO.\n");
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('A')))
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mem_enable_int(INT_SOURCE_GPIOA);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('B')))
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mem_enable_int(INT_SOURCE_GPIOB);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('C')))
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mem_enable_int(INT_SOURCE_GPIOC);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('D')))
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mem_enable_int(INT_SOURCE_GPIOD);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('E')))
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mem_enable_int(INT_SOURCE_GPIOE);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('F')))
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mem_enable_int(INT_SOURCE_GPIOF);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('G')))
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mem_enable_int(INT_SOURCE_GPIOG);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('H')))
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mem_enable_int(INT_SOURCE_GPIOH);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('I')))
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mem_enable_int(INT_SOURCE_GPIOI);
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if (cpux_gpiog_bitmap & (WAKEUP_GPIO_GROUP('J')))
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mem_enable_int(INT_SOURCE_GPIOJ);
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mem_pio_clk_src_init();
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}
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return;
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}
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void exit_wakeup_src(unsigned int event, unsigned int gpio_enable_bitmap, unsigned int cpux_gpiog_bitmap)
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{
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/* exit standby module */
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if (event & CPUS_WAKEUP_GPIO)
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mem_pio_clk_src_exit();
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if (event & CPU0_WAKEUP_USB)
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mem_usb_exit();
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if (event & CPU0_WAKEUP_IR)
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mem_ir_exit();
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if (event & CPU0_WAKEUP_ALARM)
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;
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if (event & CPU0_WAKEUP_KEY)
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mem_key_exit();
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/* exit standby module */
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if (unlikely(debug_mask & PM_STANDBY_PRINT_STANDBY)) {
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/* restore serial clk & gpio config.
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* serial_exit();
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*/
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}
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return;
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}
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void mem_device_init(void)
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{
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mem_tmr_init();
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mem_gpio_init();
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mem_sram_init();
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mem_int_init();
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mem_clk_init(1);
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return;
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}
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void mem_device_save(void)
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{
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/* backup device state */
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mem_twi_save(0);
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mem_ccu_save(&(saved_ccm_state));
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mem_clk_save(&(saved_clk_state));
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mem_tmr_save(&(saved_tmr_state));
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mem_gpio_save(&(saved_gpio_state));
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mem_sram_save(&(saved_sram_state));
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mem_int_save();
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#ifdef CONFIG_AW_AXP
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/* axp_mem_save();*/
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#endif
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return;
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}
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void mem_device_restore(void)
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{
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#ifdef CONFIG_AW_AXP
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/* axp_mem_restore();*/
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#endif
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mem_sram_restore(&(saved_sram_state));
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mem_gpio_restore(&(saved_gpio_state));
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mem_tmr_restore(&(saved_tmr_state));
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mem_clk_restore(&(saved_clk_state));
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mem_ccu_restore(&(saved_ccm_state));
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mem_int_restore();
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mem_tmr_exit();
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mem_twi_restore();
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return;
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}
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/**
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* aw_standby_enter() - Enter the system sleep state
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*
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* @state: suspend state
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* @return: return 0 is process successed
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* @note: the core function for platform sleep
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*/
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int aw_standby_enter(unsigned long arg)
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{
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struct aw_pm_info *para = (struct aw_pm_info *)(arg);
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int ret = -1;
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int (*standby) (struct aw_pm_info *arg);
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/* clean d cache to the point of unification.
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* __cpuc_coherent_kern_range(0xc0000000, 0xffffffff-1);
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*/
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/* move standby code to sram */
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memcpy((void *)SRAM_FUNC_START, (void *)&standby_bin_start,
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(unsigned int)&standby_bin_end -
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(unsigned int)&standby_bin_start);
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dmac_flush_range((void *)SRAM_FUNC_START,
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(void *)(SRAM_FUNC_START + ((unsigned int)&standby_bin_end - (unsigned int)&standby_bin_start)));
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/* flush cache data to the memory.
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* dmac_flush_range((void *)0xc0000000, (void *)(0xdfffffff-1));
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*/
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/* clean & invalidate dcache, icache. */
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flush_cache_all();
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standby = (int (*)(struct aw_pm_info *arg))SRAM_FUNC_START;
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ret = standby(para);
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if (0 == ret)
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soft_restart(virt_to_phys(cpu_resume));
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return ret;
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}
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void query_wakeup_source(struct aw_pm_info *arg)
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{
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arg->standby_para.event = 0;
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arg->standby_para.event |=
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((mem_query_int(INT_SOURCE_EXTNMI)) ? 0 : CPU0_WAKEUP_EXINT);
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arg->standby_para.event |=
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(mem_query_int(INT_SOURCE_USBOTG) ? 0 : CPU0_WAKEUP_USB);
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arg->standby_para.event |=
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(mem_query_int(INT_SOURCE_USBEHCI0) ? 0 : CPU0_WAKEUP_USB);
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arg->standby_para.event |=
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(mem_query_int(INT_SOURCE_USBEHCI1) ? 0 : CPU0_WAKEUP_USB);
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arg->standby_para.event |=
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(mem_query_int(INT_SOURCE_USBEHCI2) ? 0 : CPU0_WAKEUP_USB);
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arg->standby_para.event |=
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(mem_query_int(INT_SOURCE_USBOHCI0) ? 0 : CPU0_WAKEUP_USB);
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arg->standby_para.event |=
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(mem_query_int(INT_SOURCE_USBOHCI1) ? 0 : CPU0_WAKEUP_USB);
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arg->standby_para.event |=
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(mem_query_int(INT_SOURCE_USBOHCI2) ? 0 : CPU0_WAKEUP_USB);
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_LRADC) ? 0 : CPU0_WAKEUP_KEY;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_IR0) ? 0 : CPU0_WAKEUP_IR;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_ALARM) ? 0 : CPU0_WAKEUP_ALARM;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_TIMER0) ? 0 : CPU0_WAKEUP_TIMEOUT;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOA) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOB) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOC) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOD) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOE) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOF) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOG) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOH) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOI) ? 0 : CPUS_WAKEUP_GPIO;
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arg->standby_para.event |=
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mem_query_int(INT_SOURCE_GPIOJ) ? 0 : CPUS_WAKEUP_GPIO;
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}
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int fetch_and_save_dram_para(dram_para_t *pstandby_dram_para)
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{
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struct device_node *np;
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s32 ret = -EINVAL;
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np = of_find_compatible_node(NULL, NULL, "allwinner,dram");
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if (IS_ERR(np)) {
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pr_err("get [allwinner, dram] device node error\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_clk",
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&pstandby_dram_para->dram_clk);
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if (ret) {
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pr_err("standby :get dram_clk err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_type",
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&pstandby_dram_para->dram_type);
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if (ret) {
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pr_err("standby :get dram_type err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_zq", &pstandby_dram_para->dram_zq);
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if (ret) {
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pr_err("standby :get dram_zq err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_odt_en",
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&pstandby_dram_para->dram_odt_en);
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if (ret) {
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pr_err("standby :get dram_odt_en err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_para1",
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&pstandby_dram_para->dram_para1);
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if (ret) {
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pr_err("standby :get dram_para1 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_para2",
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&pstandby_dram_para->dram_para2);
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if (ret) {
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pr_err("standby :get dram_para2 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_mr0",
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&pstandby_dram_para->dram_mr0);
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if (ret) {
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pr_err("standby :get dram_mr0 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_mr1",
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&pstandby_dram_para->dram_mr1);
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if (ret) {
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pr_err("standby :get dram_mr1 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_mr2",
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&pstandby_dram_para->dram_mr2);
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if (ret) {
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pr_err("standby :get dram_mr2 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_mr3",
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&pstandby_dram_para->dram_mr3);
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if (ret) {
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pr_err("standby :get dram_mr3 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr0",
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&pstandby_dram_para->dram_tpr0);
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if (ret) {
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pr_err("standby :get dram_tpr0 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr1",
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&pstandby_dram_para->dram_tpr1);
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if (ret) {
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pr_err("standby :get dram_tpr1 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr2",
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&pstandby_dram_para->dram_tpr2);
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if (ret) {
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pr_err("standby :get dram_tpr2 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr3",
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&pstandby_dram_para->dram_tpr3);
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if (ret) {
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pr_err("standby :get dram_tpr3 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr4",
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&pstandby_dram_para->dram_tpr4);
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if (ret) {
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pr_err("standby :get dram_tpr4 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr5",
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&pstandby_dram_para->dram_tpr5);
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if (ret) {
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pr_err("standby :get dram_tpr5 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr6",
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&pstandby_dram_para->dram_tpr6);
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if (ret) {
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pr_err("standby :get dram_tpr6 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr7",
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&pstandby_dram_para->dram_tpr7);
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if (ret) {
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pr_err("standby :get dram_tpr7 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr8",
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&pstandby_dram_para->dram_tpr8);
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if (ret) {
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pr_err("standby :get dram_tpr8 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr9",
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&pstandby_dram_para->dram_tpr9);
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if (ret) {
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pr_err("standby :get dram_tpr9 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr9",
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&pstandby_dram_para->dram_tpr9);
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if (ret) {
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pr_err("standby :get dram_tpr9 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr10",
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&pstandby_dram_para->dram_tpr10);
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if (ret) {
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pr_err("standby :get dram_tpr10 err.\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dram_tpr11",
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&pstandby_dram_para->dram_tpr11);
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if (ret) {
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pr_err("standby :get dram_tpr11 err.\n");
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return -EINVAL;
|
|
}
|
|
|
|
ret = of_property_read_u32(np, "dram_tpr12",
|
|
&pstandby_dram_para->dram_tpr12);
|
|
if (ret) {
|
|
pr_err("standby :get dram_tpr12 err.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = of_property_read_u32(np, "dram_tpr13",
|
|
&pstandby_dram_para->dram_tpr13);
|
|
if (ret) {
|
|
pr_err("standby :get dram_tpr13 err.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|