255 lines
6.8 KiB
C
255 lines
6.8 KiB
C
/*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/* arch/arm/mach-sunxi/pm/pm_debug_secure.c
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* Copyright (C) 2013-2014 allwinner.
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*
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* By : huangshr
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* Date : 2014-10-20
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*/
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#include <linux/ctype.h>
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#include <linux/module.h>
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#include "pm_debug.h"
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#include "mem_hwspinlock.h"
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#if defined(CONFIG_ARCH_SUN8IW6P1) || defined(CONFIG_ARCH_SUN9IW1P1)
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static volatile __r_prcm_pio_pad_hold *pm_secure_status_reg;
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static volatile __r_prcm_pio_pad_hold *pm_secure_status_reg_pa;
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#ifndef CONFIG_SUNXI_TRUSTZONE
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static __r_prcm_pio_pad_hold pm_secure_status_reg_tmp;
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static __r_prcm_pio_pad_hold pm_secure_status_reg_pa_tmp;
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#endif /*for define status reg tmp */
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void pm_secure_mem_status_init(void)
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{
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pm_secure_status_reg =
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(volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG);
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pm_secure_status_reg_pa =
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(volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG_PA);
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hwspinlock_init(1);
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}
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void pm_secure_mem_status_init_nommu(void)
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{
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pm_secure_status_reg =
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(volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG);
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pm_secure_status_reg_pa =
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(volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG_PA);
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hwspinlock_init(0);
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}
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void pm_secure_mem_status_clear(void)
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{
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#ifndef CONFIG_SUNXI_TRUSTZONE
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int i = 1;
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pm_secure_status_reg_tmp.dwval = (*pm_secure_status_reg).dwval;
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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while (i < STANDBY_STATUS_REG_NUM) {
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pm_secure_status_reg_tmp.bits.reg_sel = i;
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pm_secure_status_reg_tmp.bits.data_wr = 0;
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(*pm_secure_status_reg).dwval =
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pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg).dwval =
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pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 1;
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(*pm_secure_status_reg).dwval =
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pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg).dwval =
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pm_secure_status_reg_tmp.dwval;
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i++;
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}
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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#else
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call_firmware_op(set_standby_status, TEE_SMC_PLAFORM_OPERATION,
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TE_SMC_STANDBY_STATUS_CLEAR,
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(u32) pm_secure_status_reg, 0);
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#endif
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}
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void pm_secure_mem_status_exit(void)
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{
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return;
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}
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void save_pm_secure_mem_status(volatile __u32 val)
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{
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#ifndef CONFIG_SUNXI_TRUSTZONE
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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pm_secure_status_reg_tmp.bits.reg_sel = 1;
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pm_secure_status_reg_tmp.bits.data_wr = val;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 1;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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/* asm volatile ("dsb");*/
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/* asm volatile ("isb");*/
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return;
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#else
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call_firmware_op(set_standby_status, TEE_SMC_PLAFORM_OPERATION,
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TE_SMC_STANDBY_STATUS_SET,
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(u32) pm_secure_status_reg, val);
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return;
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#endif
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}
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__u32 get_pm_secure_mem_status(void)
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{
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int val = 0;
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#ifndef CONFIG_SUNXI_TRUSTZONE
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pm_secure_status_reg_tmp.bits.reg_sel = 1;
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.dwval = (*pm_secure_status_reg).dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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val = pm_secure_status_reg_tmp.bits.data_rd;
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return val;
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#else
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val =
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call_firmware_op(set_standby_status, TEE_SMC_PLAFORM_OPERATION,
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TE_SMC_STANDBY_STATUS_GET,
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(u32) pm_secure_status_reg, 1);
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return val;
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#endif
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}
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void show_pm_secure_mem_status(void)
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{
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int i = 1;
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int val = 0;
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#ifndef CONFIG_SUNXI_TRUSTZONE
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while (i < STANDBY_STATUS_REG_NUM) {
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pm_secure_status_reg_tmp.bits.reg_sel = i;
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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(*pm_secure_status_reg).dwval =
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pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.dwval =
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(*pm_secure_status_reg).dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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val = pm_secure_status_reg_tmp.bits.data_rd;
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printk("addr %x, value = %x. \n", (i), val);
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i++;
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}
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#else
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while (i < STANDBY_STATUS_REG_NUM) {
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val =
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call_firmware_op(set_standby_status,
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TEE_SMC_PLAFORM_OPERATION,
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TE_SMC_STANDBY_STATUS_GET,
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(u32) pm_secure_status_reg, i);
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printk("addr %x, value = %x. \n", (i), val);
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i++;
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}
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#endif
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}
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void save_pm_secure_mem_status_nommu(volatile __u32 val)
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{
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#ifndef CONFIG_SUNXI_TRUSTZONE
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if (!hwspin_lock_timeout_nommu(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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pm_secure_status_reg_pa_tmp.bits.reg_sel = 1;
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pm_secure_status_reg_pa_tmp.bits.data_wr = val;
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(*pm_secure_status_reg_pa).dwval =
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pm_secure_status_reg_pa_tmp.dwval;
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pm_secure_status_reg_pa_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg_pa).dwval =
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pm_secure_status_reg_pa_tmp.dwval;
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pm_secure_status_reg_pa_tmp.bits.wr_pulse = 1;
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(*pm_secure_status_reg_pa).dwval =
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pm_secure_status_reg_pa_tmp.dwval;
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pm_secure_status_reg_pa_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg_pa).dwval =
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pm_secure_status_reg_pa_tmp.dwval;
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hwspin_unlock_nommu(MEM_RTC_REG_HWSPINLOCK);
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}
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return;
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#else
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call_firmware_op(set_standby_status, TEE_SMC_PLAFORM_OPERATION,
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TE_SMC_STANDBY_STATUS_SET,
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(u32) pm_secure_status_reg_pa, val);
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#endif
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}
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#elif defined(CONFIG_ARCH_SUN8IW1P1) || \
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defined(CONFIG_ARCH_SUN8IW3P1) || \
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defined(CONFIG_ARCH_SUN8IW5P1) || \
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defined(CONFIG_ARCH_SUN8IW7P1) || \
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defined(CONFIG_ARCH_SUN8IW8P1) || \
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defined(CONFIG_ARCH_SUN8IW10P1) || \
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defined(CONFIG_ARCH_SUN8IW11P1) || \
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defined(CONFIG_ARCH_SUN8IW17P1) || \
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defined(CONFIG_ARCH_SUN50IW1P1) || \
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defined(CONFIG_ARCH_SUN50IW2P1) || \
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defined(CONFIG_ARCH_SUN50IW3P1) || \
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defined(CONFIG_ARCH_SUN50IW6P1)
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void pm_secure_mem_status_init(char *name)
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{
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mem_status_init(name);
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return;
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}
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void pm_secure_mem_status_init_nommu(void)
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{
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mem_status_init_nommu();
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return;
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}
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void pm_secure_mem_status_clear(void)
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{
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mem_status_clear();
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return;
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}
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void pm_secure_mem_status_exit(void)
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{
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mem_status_exit();
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return;
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}
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void save_pm_secure_mem_status(volatile __u32 val)
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{
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save_mem_status(val);
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return;
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}
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__u32 get_pm_secure_mem_status(void)
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{
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u32 val = 0;
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val = get_mem_status();
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return val;
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}
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void show_pm_secure_mem_status(void)
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{
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show_mem_status();
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}
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#endif
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