141 lines
3.7 KiB
C
141 lines
3.7 KiB
C
/*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "pm_i.h"
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static volatile __r_prcm_pio_pad_hold *status_reg;
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static __r_prcm_pio_pad_hold status_reg_tmp;
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static volatile __r_prcm_pio_pad_hold *status_reg_pa;
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static __r_prcm_pio_pad_hold status_reg_pa_tmp;
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void mem_status_init(void)
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{
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status_reg = (volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG);
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status_reg_pa =
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(volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG_PA);
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/*init spinlock for sync */
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hwspinlock_init(1);
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}
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void mem_status_init_nommu(void)
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{
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status_reg = (volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG);
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status_reg_pa =
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(volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG_PA);
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/*init spinlock for sync */
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hwspinlock_init(0);
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}
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void mem_status_clear(void)
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{
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int i = 1;
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status_reg_tmp.dwval = (*status_reg).dwval;
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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while (i < STANDBY_STATUS_REG_NUM) {
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status_reg_tmp.bits.reg_sel = i;
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status_reg_tmp.bits.data_wr = 0;
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(*status_reg).dwval = status_reg_tmp.dwval;
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status_reg_tmp.bits.wr_pulse = 0;
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(*status_reg).dwval = status_reg_tmp.dwval;
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status_reg_tmp.bits.wr_pulse = 1;
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(*status_reg).dwval = status_reg_tmp.dwval;
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status_reg_tmp.bits.wr_pulse = 0;
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(*status_reg).dwval = status_reg_tmp.dwval;
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i++;
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}
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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}
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void mem_status_exit(void)
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{
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return;
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}
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void save_mem_status(volatile __u32 val)
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{
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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status_reg_tmp.bits.reg_sel = 1;
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status_reg_tmp.bits.data_wr = val;
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(*status_reg).dwval = status_reg_tmp.dwval;
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status_reg_tmp.bits.wr_pulse = 0;
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(*status_reg).dwval = status_reg_tmp.dwval;
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status_reg_tmp.bits.wr_pulse = 1;
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(*status_reg).dwval = status_reg_tmp.dwval;
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status_reg_tmp.bits.wr_pulse = 0;
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(*status_reg).dwval = status_reg_tmp.dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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/* asm volatile ("dsb");*/
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/* asm volatile ("isb");*/
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return;
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}
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__u32 get_mem_status(void)
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{
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int val = 0;
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status_reg_tmp.bits.reg_sel = 1;
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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(*status_reg).dwval = status_reg_tmp.dwval;
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/*read */
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status_reg_tmp.dwval = (*status_reg).dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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val = status_reg_tmp.bits.data_rd;
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return val;
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}
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void show_mem_status(void)
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{
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int i = 1;
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int val = 0;
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while (i < STANDBY_STATUS_REG_NUM) {
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status_reg_tmp.bits.reg_sel = i;
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/*write */
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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(*status_reg).dwval = status_reg_tmp.dwval;
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/*read */
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status_reg_tmp.dwval = (*status_reg).dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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val = status_reg_tmp.bits.data_rd;
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printk("addr %x, value = %x. \n", (i), val);
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i++;
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}
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}
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void save_mem_status_nommu(volatile __u32 val)
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{
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if (!hwspin_lock_timeout_nommu(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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status_reg_pa_tmp.bits.reg_sel = 1;
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status_reg_pa_tmp.bits.data_wr = val;
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(*status_reg_pa).dwval = status_reg_pa_tmp.dwval;
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status_reg_pa_tmp.bits.wr_pulse = 0;
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(*status_reg_pa).dwval = status_reg_pa_tmp.dwval;
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status_reg_pa_tmp.bits.wr_pulse = 1;
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(*status_reg_pa).dwval = status_reg_pa_tmp.dwval;
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status_reg_pa_tmp.bits.wr_pulse = 0;
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(*status_reg_pa).dwval = status_reg_pa_tmp.dwval;
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hwspin_unlock_nommu(MEM_RTC_REG_HWSPINLOCK);
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}
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return;
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}
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