819 lines
20 KiB
C
819 lines
20 KiB
C
/*
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* Copyright (c) 2011-2020 yanggq.young@allwinnertech.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include "standby.h"
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#include "../mem_ccmu.h"
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#include "../pm_config.h"
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#include "standby_clock.h"
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#include "standby_divlib.h"
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static __ccmu_reg_list_t *CmuReg;
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/*==============================================================================*/
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/* CLOCK SET FOR SYSTEM STANDBY*/
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/*==============================================================================*/
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#ifdef CONFIG_ARCH_SUN8I
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static __ccmu_pll1_reg0000_t CmuReg_Pll1Ctl_tmp;
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static __ccmu_sysclk_ratio_reg0050_t CmuReg_SysClkDiv_tmp;
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#define PIO_INT_DEB_REG (AW_GPIO_BASE_PA + 0x258)
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static __u32 pio_int_deb_back;
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static __ccmu_ahb1_ratio_reg0054_t CmuReg_ahb1_tmp;
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static __ccmu_ahb1_ratio_reg0054_t CmuReg_ahb1_backup;
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static __ccmu_apb2_ratio_reg0058_t CmuReg_apb2_tmp;
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static __ccmu_apb2_ratio_reg0058_t CmuReg_apb2_backup;
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#ifdef CONFIG_ARCH_SUN8IW10P1
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static __u32 CmuReg_ee_backup;
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static __u32 CmuReg_de_backup;
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#endif
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/*
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*********************************************************************************************************
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* standby_clk_init
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*
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*Description: ccu init for platform standby
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*
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*Arguments : none
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*
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*Return : result,
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*
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*Notes :
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*
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*********************************************************************************************************
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*/
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__s32 standby_clk_init(void)
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{
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CmuReg = (__ccmu_reg_list_t *) IO_ADDRESS(AW_CCM_BASE);
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_exit
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*
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*Description: ccu exit for platform standby
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*
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*Arguments : none
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*
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*Return : result,
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*
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*Notes :
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*
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*********************************************************************************************************
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*/
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__s32 standby_clk_exit(void)
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{
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_core2losc
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*
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* Description: switch core clock to 32k low osc.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_core2losc(void)
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{
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unsigned int tmp;
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/*CmuReg->SysClkDiv.CpuClkSrc = 0; */
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/* cpu frequency is internal Losc hz */
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tmp = readl(&(CmuReg->SysClkDiv));
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tmp &= (~(0x00030000));
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writel(tmp, &(CmuReg->SysClkDiv));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_core2hosc
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*
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* Description: switch core clock to 24M high osc.
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*
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* Arguments : none
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*
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*********************************************************************************************************
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*/
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__s32 standby_clk_core2hosc(void)
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{
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CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
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CmuReg_SysClkDiv_tmp.bits.CpuClkSrc = AC327_CLKSRC_HOSC; /*26M OSC */
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CmuReg->SysClkDiv.dwval = CmuReg_SysClkDiv_tmp.dwval;
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_core2pll
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*
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* Description: switch core clock to core pll.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_core2pll(void)
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{
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CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
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CmuReg_SysClkDiv_tmp.bits.CpuClkSrc = AC327_CLKSRC_PLL1; /*pll cpu */
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CmuReg->SysClkDiv.dwval = CmuReg_SysClkDiv_tmp.dwval;
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_plldisable
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*
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* Description: disable dram pll.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_plldisable(void)
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{
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unsigned int tmp;
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#if 0 /*use old mode */
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/*pll lock */
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tmp = readl(&(CmuReg->PllLockCtl));
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tmp |= ((0x10000000));
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writel(tmp, &(CmuReg->Pll1Ctl));
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#endif
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/*pll1 */
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tmp = readl(&(CmuReg->Pll1Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll1Ctl));
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/*pll6: for periph0 */
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tmp = readl(&(CmuReg->Pll6Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll6Ctl));
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#ifndef CONFIG_ARCH_SUN8IW11P1
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/*pll9: periph 1 */
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tmp = readl(&(CmuReg->Pll9Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll9Ctl));
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/*pll 24M: */
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tmp = readl(&(CmuReg->Pll24M));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll24M));
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#else
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/* ohci 12M divided from 24M */
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tmp = readl(&(CmuReg->UsbClk));
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tmp = (tmp & (~(0x3 << 20))) | (0x1 << 20);
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tmp = (tmp & (~(0x3 << 22))) | (0x1 << 22);
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tmp = (tmp & (~(0x3 << 24))) | (0x1 << 24);
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writel(tmp, &(CmuReg->UsbClk));
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/*pll9: periph 1 */
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tmp = readl(&(CmuReg->Pll7Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll7Ctl));
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/* pll mipi */
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tmp = readl(&(CmuReg->PllMipi));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->PllMipi));
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#endif
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#if defined CONFIG_ARCH_SUN8IW10P1 || defined CONFIG_ARCH_SUN8IW11P1
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/*pll2: for audio */
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tmp = readl(&(CmuReg->Pll2Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll2Ctl));
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/*pll3: for video */
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tmp = readl(&(CmuReg->Pll3Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll3Ctl));
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/*pll10: for de */
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tmp = readl(&(CmuReg->Pll10Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll10Ctl));
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#else
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/*pll4: for ve */
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tmp = readl(&(CmuReg->Pll4Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll4Ctl));
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/*pll5: for ddr */
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tmp = readl(&(CmuReg->Pll5Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll5Ctl));
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#endif
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_pllenable
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*
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* Description: enable dram pll.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_pllenable(void)
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{
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unsigned int tmp;
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#ifndef CONFIG_ARCH_SUN8IW11P1
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/*pll 24M: */
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tmp = readl(&(CmuReg->Pll24M));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll24M));
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#endif
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/*pll1 */
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tmp = readl(&(CmuReg->Pll1Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll1Ctl));
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/*pll6: for periph0 */
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tmp = readl(&(CmuReg->Pll6Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll6Ctl));
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#ifndef CONFIG_ARCH_SUN8IW11P1
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/*pll9: periph 1 */
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tmp = readl(&(CmuReg->Pll9Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll9Ctl));
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/*pll10: de */
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tmp = readl(&(CmuReg->Pll10Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll10Ctl));
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#else
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/*pll9: periph 1 */
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tmp = readl(&(CmuReg->Pll7Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll7Ctl));
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#endif
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#if 0
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/*pll2: for audio */
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tmp = readl(&(CmuReg->Pll2Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll2Ctl));
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/*pll3: for video */
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tmp = readl(&(CmuReg->Pll3Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll3Ctl));
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/*pll4: for ve */
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tmp = readl(&(CmuReg->Pll4Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll4Ctl));
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/*pll5: for ddr */
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tmp = readl(&(CmuReg->Pll5Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll5Ctl));
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/*pll7: for isp */
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tmp = readl(&(CmuReg->PllIspCtl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->PllIspCtl));
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#endif
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return 0;
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}
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#if 0
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/*
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*********************************************************************************************************
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* standby_clk_pll1enable
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*
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* Description: enable pll1.
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*
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* Arguments : none
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*
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*********************************************************************************************************
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*/
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__s32 standby_clk_pll1enable(void)
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{
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CmuReg_Pll1Ctl_tmp.dwval = CmuReg->Pll1Ctl.dwval;
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CmuReg_Pll1Ctl_tmp.bits.PLLEn = 1;
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CmuReg->Pll1Ctl.dwval = CmuReg_Pll1Ctl_tmp.dwval;
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return 0;
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}
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#endif
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/*
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* standby_clk_set_keyfield
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*
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* Description: set keyfield for modify ldo enable bit.
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*
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* Arguments : none
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*
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* Returns : 0;
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*/
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void standby_clk_set_keyfield(void)
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{
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unsigned int tmp;
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/*keyfield set to: 0xa7 */
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tmp = readl((void *)(0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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tmp |= ((0xa7000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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}
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/*
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* standby_clk_unset_keyfield
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*
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* Description: unset keyfield for disable modify ldo enable bit.
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*
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* Arguments : none
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*
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* Returns : 0;
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*/
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void standby_clk_unset_keyfield(void)
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{
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unsigned int tmp;
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/*keyfield set to: 0 */
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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}
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/*
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*********************************************************************************************************
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* standby_clk_hoscdisable
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*
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* Description: disable HOSC.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_hoscdisable(void)
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{
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unsigned int tmp;
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/*disable dcxo: band gap */
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tmp = readl((0xf1c20328));
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tmp &= (~(0x80000000));
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writel(tmp, (0xf1c20328));
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/*disable dcxo */
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tmp = readl((0xf1c20324));
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tmp &= (~(0x80020000));
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writel(tmp, (0xf1c20324));
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/*0xf1c00000 + 0xf4 (system_ctrl: pll ctrl reg1) */
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/*bit2: hosc; */
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/*bit1: ldo for analog; */
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/*bit0: ldo for digital */
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/*disable hosc */
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0x00000004));
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writel(tmp, (0xf1c00000 + 0xf4));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_hoscenable
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*
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* Description: enable HOSC.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_hoscenable(void)
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{
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unsigned int tmp;
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/*0xf1c00000 + 0xf4 (system_ctrl: pll ctrl reg1) */
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/*bit2: hosc; */
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/*bit1: ldo for analog; */
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/*bit0: ldo for digital */
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/*enable hosc */
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tmp = readl((0xf1c00000 + 0xf4));
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tmp |= ((0x00000004));
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writel(tmp, (0xf1c00000 + 0xf4));
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/*enable dcxo */
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tmp = readl((0xf1c20324));
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tmp |= (0x80020000);
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writel(tmp, (0xf1c20324));
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/*enable dcxo: band gap */
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tmp = readl((0xf1c20328));
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tmp |= (0x80000000);
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writel(tmp, (0xf1c20328));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_ldodisable
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*
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* Description: disable LDO.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_ldodisable(void)
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{
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unsigned int tmp;
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/*0xf1c00000 + 0xf4 (system_ctrl: pll ctrl reg1) */
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/*bit2: hosc; */
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/*bit1: ldo for analog; */
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/*bit0: ldo for digital */
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/*disable ldo */
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0x00000003));
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writel(tmp, (0xf1c00000 + 0xf4));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_ldoenable
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*
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* Description: enable LDO.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_ldoenable(void)
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{
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unsigned int tmp;
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/*0xf1c00000 + 0xf4 (system_ctrl: pll ctrl reg1) */
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/*bit2: hosc; */
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/*bit1: ldo for analog; */
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/*bit0: ldo for digital */
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/*enable ldo */
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tmp = readl((0xf1c00000 + 0xf4));
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tmp |= ((0x00000003));
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writel(tmp, (0xf1c00000 + 0xf4));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_setdiv
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*
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* Description: switch core clock to 32k low osc.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_setdiv(struct standby_clk_div_t *clk_div)
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{
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unsigned int tmp;
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if (!clk_div) {
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return -1;
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}
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/*ahb1 */
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CmuReg_ahb1_tmp.dwval = CmuReg->Ahb1Div.dwval;
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CmuReg_ahb1_tmp.bits.Ahb1Div = clk_div->ahb_div;
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CmuReg_ahb1_tmp.bits.Ahb1PreDiv = clk_div->ahb_pre_div;
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CmuReg_ahb1_tmp.bits.Apb1Div = clk_div->apb_div;
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CmuReg->Ahb1Div.dwval = CmuReg_ahb1_tmp.dwval;
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/*axi */
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CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
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CmuReg_SysClkDiv_tmp.bits.AXIClkDiv = clk_div->axi_div;
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CmuReg->SysClkDiv.dwval = CmuReg_SysClkDiv_tmp.dwval;
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/*apb2 */
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CmuReg_apb2_tmp.dwval = CmuReg->Apb2Div.dwval;
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CmuReg_apb2_tmp.bits.DivM = clk_div->apb2_div;
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CmuReg_apb2_tmp.bits.DivN = clk_div->apb2_pre_div;
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CmuReg->Apb2Div.dwval = CmuReg_apb2_tmp.dwval;
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_getdiv
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*
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* Description: switch core clock to 32k low osc.
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*
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* Arguments : none
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*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_getdiv(struct standby_clk_div_t *clk_div)
|
|
{
|
|
if (!clk_div) {
|
|
return -1;
|
|
}
|
|
|
|
/*axi */
|
|
CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
|
|
clk_div->axi_div = CmuReg_SysClkDiv_tmp.bits.AXIClkDiv;
|
|
|
|
/*ahb1 */
|
|
CmuReg_ahb1_tmp.dwval = CmuReg->Ahb1Div.dwval;
|
|
clk_div->ahb_div = CmuReg_ahb1_tmp.bits.Ahb1Div;
|
|
clk_div->apb_div = CmuReg_ahb1_tmp.bits.Apb1Div;
|
|
clk_div->ahb_pre_div = CmuReg_ahb1_tmp.bits.Ahb1PreDiv;
|
|
|
|
/*apb2 */
|
|
CmuReg_apb2_tmp.dwval = CmuReg->Apb2Div.dwval;
|
|
clk_div->apb2_div = CmuReg_apb2_tmp.bits.DivM;
|
|
clk_div->apb2_pre_div = CmuReg_apb2_tmp.bits.DivN;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_set_pll_factor
|
|
*
|
|
* Description: set pll factor, target cpu freq is 384M hz
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
|
|
__s32 standby_clk_set_pll_factor(struct pll_factor_t *pll_factor)
|
|
{
|
|
__ccmu_pll1_reg0000_t pll1_ctrl;
|
|
|
|
if (!pll_factor) {
|
|
return -1;
|
|
}
|
|
|
|
pll1_ctrl.dwval = readl(&(CmuReg->Pll1Ctl));
|
|
|
|
pll1_ctrl.bits.FactorN = pll_factor->FactorN;
|
|
pll1_ctrl.bits.FactorK = pll_factor->FactorK;
|
|
pll1_ctrl.bits.FactorM = pll_factor->FactorM;
|
|
pll1_ctrl.bits.FactorP = pll_factor->FactorP;
|
|
|
|
writel(pll1_ctrl.dwval, &(CmuReg->Pll1Ctl));
|
|
/*busy_waiting(); */
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_get_pll_factor
|
|
*
|
|
* Description:
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
|
|
__s32 standby_clk_get_pll_factor(struct pll_factor_t *pll_factor)
|
|
{
|
|
__ccmu_pll1_reg0000_t pll1_ctrl;
|
|
|
|
if (!pll_factor) {
|
|
return -1;
|
|
}
|
|
|
|
pll1_ctrl.dwval = readl(&(CmuReg->Pll1Ctl));
|
|
|
|
pll_factor->FactorN = pll1_ctrl.bits.FactorN;
|
|
pll_factor->FactorK = pll1_ctrl.bits.FactorK;
|
|
pll_factor->FactorM = pll1_ctrl.bits.FactorM;
|
|
pll_factor->FactorP = pll1_ctrl.bits.FactorP;
|
|
|
|
/*busy_waiting(); */
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_apb2losc
|
|
*
|
|
* Description: switch apb2 clock to 32k low osc.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_apb2losc(void)
|
|
{
|
|
unsigned int tmp;
|
|
|
|
/*apb2 */
|
|
CmuReg_apb2_tmp.dwval = CmuReg->Apb2Div.dwval;
|
|
CmuReg_apb2_tmp.bits.ClkSrc = APB2_CLKSRC_LOSC;
|
|
CmuReg->Apb2Div.dwval = CmuReg_apb2_tmp.dwval;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_apb2hosc
|
|
*
|
|
* Description: switch apb2 clock to 24M hosc.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_apb2hosc(void)
|
|
{
|
|
unsigned int tmp;
|
|
|
|
/*apb2 */
|
|
CmuReg_apb2_tmp.dwval = CmuReg->Apb2Div.dwval;
|
|
CmuReg_apb2_tmp.bits.ClkSrc = APB2_CLKSRC_HOSC;
|
|
CmuReg->Apb2Div.dwval = CmuReg_apb2_tmp.dwval;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_bus_src_backup
|
|
*
|
|
* Description: switch ahb2->?
|
|
* ahb1->?.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_bus_src_backup(void)
|
|
{
|
|
/*backup bus src cfg */
|
|
/* backup ahb clk src */
|
|
CmuReg_ahb1_backup.dwval = CmuReg->Ahb1Div.dwval;
|
|
/* backup apb clk src */
|
|
CmuReg_apb2_backup.dwval = CmuReg->Apb2Div.dwval;
|
|
|
|
#ifdef CONFIG_ARCH_SUN8IW10P1
|
|
/* backup de/ee clk src */
|
|
CmuReg_de_backup = CmuReg->De0;
|
|
CmuReg_ee_backup = CmuReg->Ee0;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_bus_src_set
|
|
*
|
|
* Description: switch ahb2->ahb1->axi.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
|
|
__s32 standby_clk_bus_src_set(void)
|
|
{
|
|
/* change ahb1 clock to axi */
|
|
CmuReg_ahb1_tmp.dwval = CmuReg->Ahb1Div.dwval;
|
|
CmuReg_ahb1_tmp.bits.Ahb1ClkSrc = AHB1_CLKSRC_AXI;
|
|
CmuReg->Ahb1Div.dwval = CmuReg_ahb1_tmp.dwval;
|
|
/* printk("CmuReg_ahb1_backup, %x!\n", CmuReg_ahb1_backup); */
|
|
|
|
#ifdef CONFIG_ARCH_SUN8IW10P1
|
|
/* switch de clk to ahb */
|
|
CmuReg->De0 = 0x82000000;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_bus_src_restore
|
|
*
|
|
* Description: switch ahb2->?
|
|
* ahb1->?.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_bus_src_restore(void)
|
|
{
|
|
/* restore ahb clk src */
|
|
CmuReg->Ahb1Div.dwval = CmuReg_ahb1_backup.dwval;
|
|
|
|
/* restore apb clk src */
|
|
CmuReg->Apb2Div.dwval = CmuReg_apb2_backup.dwval;
|
|
|
|
#ifdef CONFIG_ARCH_SUN8IW10P1
|
|
/* retore de/ee clk */
|
|
CmuReg->De0 = CmuReg_de_backup;
|
|
CmuReg->Ee0 = CmuReg_ee_backup;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_dramgating
|
|
*
|
|
* Description: gating dram clock.
|
|
*
|
|
* Arguments : onoff dram clock gating on or off;
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
void standby_clk_dramgating(int onoff)
|
|
{
|
|
unsigned int tmp;
|
|
tmp = readl(&(CmuReg->Pll5Ctl));
|
|
|
|
if (onoff) {
|
|
tmp |= (0x80000000);
|
|
} else {
|
|
tmp &= (~0x80000000);
|
|
}
|
|
|
|
writel(tmp, &(CmuReg->Pll5Ctl));
|
|
|
|
return;
|
|
}
|
|
|
|
__u32 standby_clk_get_cpu_freq(void)
|
|
{
|
|
__u32 FactorN = 1;
|
|
__u32 FactorK = 1;
|
|
__u32 FactorM = 1;
|
|
__u32 FactorP = 1;
|
|
__u32 reg_val = 0;
|
|
__u32 cpu_freq = 0;
|
|
|
|
CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
|
|
/*get runtime freq: clk src + divider ratio */
|
|
/*src selection */
|
|
reg_val = CmuReg_SysClkDiv_tmp.bits.CpuClkSrc;
|
|
if (0 == reg_val) {
|
|
/*32khz osc */
|
|
cpu_freq = 32;
|
|
|
|
} else if (1 == reg_val) {
|
|
/*hosc, 24Mhz */
|
|
cpu_freq = 24000; /*unit is khz */
|
|
} else if (2 == reg_val || 3 == reg_val) {
|
|
CmuReg_Pll1Ctl_tmp.dwval = CmuReg->Pll1Ctl.dwval;
|
|
FactorN = CmuReg_Pll1Ctl_tmp.bits.FactorN + 1;
|
|
FactorK = CmuReg_Pll1Ctl_tmp.bits.FactorK + 1;
|
|
FactorM = CmuReg_Pll1Ctl_tmp.bits.FactorM + 1;
|
|
FactorP = 1 << (CmuReg_Pll1Ctl_tmp.bits.FactorP);
|
|
|
|
cpu_freq =
|
|
raw_lib_udiv(24000 * FactorN * FactorK, FactorP * FactorM);
|
|
}
|
|
/*printk("cpu_freq = dec(%d). \n", cpu_freq); */
|
|
/*busy_waiting(); */
|
|
|
|
return cpu_freq;
|
|
}
|
|
#endif
|