386 lines
16 KiB
C
386 lines
16 KiB
C
/*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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*********************************************************************************************************
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* LINUX-KERNEL
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* AllWinner Linux Platform Develop Kits
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* Kernel Module
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*
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* (c) Copyright 2006-2011, kevin.z China
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* All Rights Reserved
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*
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* File : mem_cci400.c
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* By : gq.yang
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* Version : v1.0
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* Date : 2012-11-3 20:13
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* Descript: interrupt for platform mem
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* Update : date auther ver notes
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*********************************************************************************************************
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*/
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#include "pm_i.h"
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#ifdef CONFIG_ARCH_SUN9IW1P1
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/*
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*********************************************************************************************************
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* MEM cci400 SAVE
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*
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* Description: mem cci400_state save.
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*
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* Arguments : none.
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*
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* Returns : 0/-1;
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*********************************************************************************************************
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*/
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__s32 mem_cci400_save(struct cci400_state *cci_state)
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{
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int i = 0;
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cci_state->cci_reg = (cci_reg_list_t *) IO_ADDRESS(SUNXI_CCI400_PBASE);
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cci_state->cci_reg_backup[0] = cci_state->cci_reg->ctrl_override_reg;
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cci_state->cci_reg_backup[1] = cci_state->cci_reg->spec_ctrl_reg;
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cci_state->cci_reg_backup[2] = cci_state->cci_reg->secure_acc_reg;
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cci_state->cci_reg_backup[3] = cci_state->cci_reg->status_reg;
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cci_state->cci_reg_backup[4] = cci_state->cci_reg->imprecise_err_reg;
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cci_state->cci_reg_backup[5] = cci_state->cci_reg->pmcr_reg;
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cci_state->cci_reg_backup[6] =
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cci_state->cci_reg->component_peripheral_reg[0];
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cci_state->cci_reg_backup[7] =
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cci_state->cci_reg->component_peripheral_reg[1];
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cci_state->cci_reg_backup[8] =
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cci_state->cci_reg->component_peripheral_reg[2];
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cci_state->cci_reg_backup[9] =
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cci_state->cci_reg->component_peripheral_reg[3];
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cci_state->cci_reg_backup[10] =
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cci_state->cci_reg->component_peripheral_reg[4];
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cci_state->cci_reg_backup[11] =
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cci_state->cci_reg->component_peripheral_reg[5];
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cci_state->cci_reg_backup[12] =
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cci_state->cci_reg->component_peripheral_reg[6];
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cci_state->cci_reg_backup[13] =
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cci_state->cci_reg->component_peripheral_reg[7];
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cci_state->cci_reg_backup[14] =
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cci_state->cci_reg->component_peripheral_reg[8];
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cci_state->cci_reg_backup[15] =
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cci_state->cci_reg->component_peripheral_reg[9];
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cci_state->cci_reg_backup[16] =
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cci_state->cci_reg->component_peripheral_reg[10];
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cci_state->cci_reg_backup[17] =
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cci_state->cci_reg->component_peripheral_reg[11];
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cci_state->cci_reg_backup[18] =
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cci_state->cci_reg->s_inf[0].snoop_ctrl_reg;
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cci_state->cci_reg_backup[19] =
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cci_state->cci_reg->s_inf[0].share_override_reg;
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cci_state->cci_reg_backup[20] =
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cci_state->cci_reg->s_inf[0].rd_channel_qos_val_reg;
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cci_state->cci_reg_backup[21] =
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cci_state->cci_reg->s_inf[0].wr_channel_qos_val_reg;
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cci_state->cci_reg_backup[22] =
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cci_state->cci_reg->s_inf[0].qos_ctrl_reg;
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cci_state->cci_reg_backup[23] = cci_state->cci_reg->s_inf[0].max_ot_reg;
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cci_state->cci_reg_backup[24] =
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cci_state->cci_reg->s_inf[0].regu_target_reg;
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cci_state->cci_reg_backup[25] =
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cci_state->cci_reg->s_inf[0].qos_regu_scale_factor_reg;
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cci_state->cci_reg_backup[26] =
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cci_state->cci_reg->s_inf[0].qos_range_reg;
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cci_state->cci_reg_backup[27] =
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cci_state->cci_reg->s_inf[1].snoop_ctrl_reg;
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cci_state->cci_reg_backup[28] =
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cci_state->cci_reg->s_inf[1].share_override_reg;
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cci_state->cci_reg_backup[29] =
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cci_state->cci_reg->s_inf[1].rd_channel_qos_val_reg;
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cci_state->cci_reg_backup[30] =
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cci_state->cci_reg->s_inf[1].wr_channel_qos_val_reg;
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cci_state->cci_reg_backup[31] =
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cci_state->cci_reg->s_inf[1].qos_ctrl_reg;
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cci_state->cci_reg_backup[32] = cci_state->cci_reg->s_inf[1].max_ot_reg;
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cci_state->cci_reg_backup[33] =
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cci_state->cci_reg->s_inf[1].regu_target_reg;
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cci_state->cci_reg_backup[34] =
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cci_state->cci_reg->s_inf[1].qos_regu_scale_factor_reg;
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cci_state->cci_reg_backup[35] =
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cci_state->cci_reg->s_inf[1].qos_range_reg;
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cci_state->cci_reg_backup[36] =
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cci_state->cci_reg->s_inf[2].snoop_ctrl_reg;
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cci_state->cci_reg_backup[37] =
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cci_state->cci_reg->s_inf[2].share_override_reg;
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cci_state->cci_reg_backup[38] =
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cci_state->cci_reg->s_inf[2].rd_channel_qos_val_reg;
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cci_state->cci_reg_backup[39] =
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cci_state->cci_reg->s_inf[2].wr_channel_qos_val_reg;
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cci_state->cci_reg_backup[40] =
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cci_state->cci_reg->s_inf[2].qos_ctrl_reg;
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cci_state->cci_reg_backup[41] = cci_state->cci_reg->s_inf[2].max_ot_reg;
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cci_state->cci_reg_backup[42] =
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cci_state->cci_reg->s_inf[2].regu_target_reg;
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cci_state->cci_reg_backup[43] =
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cci_state->cci_reg->s_inf[2].qos_regu_scale_factor_reg;
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cci_state->cci_reg_backup[44] =
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cci_state->cci_reg->s_inf[2].qos_range_reg;
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cci_state->cci_reg_backup[45] =
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cci_state->cci_reg->s_inf[3].snoop_ctrl_reg;
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cci_state->cci_reg_backup[46] =
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cci_state->cci_reg->s_inf[3].share_override_reg;
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cci_state->cci_reg_backup[47] =
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cci_state->cci_reg->s_inf[3].rd_channel_qos_val_reg;
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cci_state->cci_reg_backup[48] =
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cci_state->cci_reg->s_inf[3].wr_channel_qos_val_reg;
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cci_state->cci_reg_backup[49] =
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cci_state->cci_reg->s_inf[3].qos_ctrl_reg;
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cci_state->cci_reg_backup[50] = cci_state->cci_reg->s_inf[3].max_ot_reg;
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cci_state->cci_reg_backup[51] =
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cci_state->cci_reg->s_inf[3].regu_target_reg;
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cci_state->cci_reg_backup[52] =
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cci_state->cci_reg->s_inf[3].qos_regu_scale_factor_reg;
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cci_state->cci_reg_backup[53] =
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cci_state->cci_reg->s_inf[3].qos_range_reg;
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cci_state->cci_reg_backup[54] =
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cci_state->cci_reg->s_inf[4].snoop_ctrl_reg;
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cci_state->cci_reg_backup[55] =
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cci_state->cci_reg->s_inf[4].share_override_reg;
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cci_state->cci_reg_backup[56] =
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cci_state->cci_reg->s_inf[4].rd_channel_qos_val_reg;
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cci_state->cci_reg_backup[57] =
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cci_state->cci_reg->s_inf[4].wr_channel_qos_val_reg;
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cci_state->cci_reg_backup[58] =
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cci_state->cci_reg->s_inf[4].qos_ctrl_reg;
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cci_state->cci_reg_backup[59] = cci_state->cci_reg->s_inf[4].max_ot_reg;
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cci_state->cci_reg_backup[60] =
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cci_state->cci_reg->s_inf[4].regu_target_reg;
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cci_state->cci_reg_backup[61] =
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cci_state->cci_reg->s_inf[4].qos_regu_scale_factor_reg;
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cci_state->cci_reg_backup[62] =
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cci_state->cci_reg->s_inf[4].qos_range_reg;
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cci_state->cci_reg_backup[63] =
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cci_state->cci_reg->c_cnter.cycle_counter_reg;
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cci_state->cci_reg_backup[64] =
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cci_state->cci_reg->c_cnter.count_ctrl_reg;
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cci_state->cci_reg_backup[65] =
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cci_state->cci_reg->c_cnter.overflow_flag_status_reg;
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cci_state->cci_reg_backup[66] =
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cci_state->cci_reg->p_cnter[0].event_select_reg;
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cci_state->cci_reg_backup[67] =
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cci_state->cci_reg->p_cnter[0].event_count_reg;
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cci_state->cci_reg_backup[68] =
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cci_state->cci_reg->p_cnter[0].count_ctrl_reg;
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cci_state->cci_reg_backup[69] =
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cci_state->cci_reg->p_cnter[0].overflow_flag_status;
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cci_state->cci_reg_backup[70] =
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cci_state->cci_reg->p_cnter[1].event_select_reg;
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cci_state->cci_reg_backup[71] =
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cci_state->cci_reg->p_cnter[1].event_count_reg;
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cci_state->cci_reg_backup[72] =
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cci_state->cci_reg->p_cnter[1].count_ctrl_reg;
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cci_state->cci_reg_backup[73] =
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cci_state->cci_reg->p_cnter[1].overflow_flag_status;
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cci_state->cci_reg_backup[74] =
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cci_state->cci_reg->p_cnter[2].event_select_reg;
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cci_state->cci_reg_backup[75] =
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cci_state->cci_reg->p_cnter[2].event_count_reg;
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cci_state->cci_reg_backup[76] =
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cci_state->cci_reg->p_cnter[2].count_ctrl_reg;
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cci_state->cci_reg_backup[77] =
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cci_state->cci_reg->p_cnter[2].overflow_flag_status;
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cci_state->cci_reg_backup[78] =
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cci_state->cci_reg->p_cnter[3].event_select_reg;
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cci_state->cci_reg_backup[79] =
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cci_state->cci_reg->p_cnter[3].event_count_reg;
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cci_state->cci_reg_backup[80] =
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cci_state->cci_reg->p_cnter[3].count_ctrl_reg;
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cci_state->cci_reg_backup[81] =
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cci_state->cci_reg->p_cnter[3].overflow_flag_status;
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if (debug_mask & PM_STANDBY_PRINT_CCI400_REG) {
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for (i = 0; i < CCI_REG_BACKUP_LENGTH; i++) {
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printk("cci_state->cci_reg_backup[%d] = 0x%x .\n", i,
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cci_state->cci_reg_backup[i]);
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}
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}
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return 0;
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}
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/*
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*********************************************************************************************************
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* MEM cci400 restore
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*
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* Description: mem cci400 restore.
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*
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* Arguments : none.
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*
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* Returns : 0/-1;
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*********************************************************************************************************
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*/
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__s32 mem_cci400_restore(struct cci400_state *cci_state)
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{
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cci_state->cci_reg->ctrl_override_reg = cci_state->cci_reg_backup[0];
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cci_state->cci_reg->spec_ctrl_reg = cci_state->cci_reg_backup[1];
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cci_state->cci_reg->secure_acc_reg = cci_state->cci_reg_backup[2];
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/* cci_state->cci_reg->status_reg = cci_state->cci_reg_backup[3 ]; */
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/* cci_state->cci_reg->imprecise_err_reg = cci_state->cci_reg_backup[4 ]; */
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cci_state->cci_reg->pmcr_reg = cci_state->cci_reg_backup[5];
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cci_state->cci_reg->component_peripheral_reg[0] =
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cci_state->cci_reg_backup[6];
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cci_state->cci_reg->component_peripheral_reg[1] =
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cci_state->cci_reg_backup[7];
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cci_state->cci_reg->component_peripheral_reg[2] =
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cci_state->cci_reg_backup[8];
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cci_state->cci_reg->component_peripheral_reg[3] =
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cci_state->cci_reg_backup[9];
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cci_state->cci_reg->component_peripheral_reg[4] =
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cci_state->cci_reg_backup[10];
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cci_state->cci_reg->component_peripheral_reg[5] =
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cci_state->cci_reg_backup[11];
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cci_state->cci_reg->component_peripheral_reg[6] =
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cci_state->cci_reg_backup[12];
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cci_state->cci_reg->component_peripheral_reg[7] =
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cci_state->cci_reg_backup[13];
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cci_state->cci_reg->component_peripheral_reg[8] =
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cci_state->cci_reg_backup[14];
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cci_state->cci_reg->component_peripheral_reg[9] =
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cci_state->cci_reg_backup[15];
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cci_state->cci_reg->component_peripheral_reg[10] =
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cci_state->cci_reg_backup[16];
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cci_state->cci_reg->component_peripheral_reg[11] =
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cci_state->cci_reg_backup[17];
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cci_state->cci_reg->s_inf[0].snoop_ctrl_reg =
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cci_state->cci_reg_backup[18];
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cci_state->cci_reg->s_inf[0].share_override_reg =
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cci_state->cci_reg_backup[19];
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cci_state->cci_reg->s_inf[0].rd_channel_qos_val_reg =
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cci_state->cci_reg_backup[20];
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cci_state->cci_reg->s_inf[0].wr_channel_qos_val_reg =
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cci_state->cci_reg_backup[21];
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cci_state->cci_reg->s_inf[0].qos_ctrl_reg =
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cci_state->cci_reg_backup[22];
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cci_state->cci_reg->s_inf[0].max_ot_reg = cci_state->cci_reg_backup[23];
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cci_state->cci_reg->s_inf[0].regu_target_reg =
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cci_state->cci_reg_backup[24];
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cci_state->cci_reg->s_inf[0].qos_regu_scale_factor_reg =
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cci_state->cci_reg_backup[25];
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cci_state->cci_reg->s_inf[0].qos_range_reg =
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cci_state->cci_reg_backup[26];
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cci_state->cci_reg->s_inf[1].snoop_ctrl_reg =
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cci_state->cci_reg_backup[27];
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cci_state->cci_reg->s_inf[1].share_override_reg =
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cci_state->cci_reg_backup[28];
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cci_state->cci_reg->s_inf[1].rd_channel_qos_val_reg =
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cci_state->cci_reg_backup[29];
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cci_state->cci_reg->s_inf[1].wr_channel_qos_val_reg =
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cci_state->cci_reg_backup[30];
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cci_state->cci_reg->s_inf[1].qos_ctrl_reg =
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cci_state->cci_reg_backup[31];
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cci_state->cci_reg->s_inf[1].max_ot_reg = cci_state->cci_reg_backup[32];
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cci_state->cci_reg->s_inf[1].regu_target_reg =
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cci_state->cci_reg_backup[33];
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cci_state->cci_reg->s_inf[1].qos_regu_scale_factor_reg =
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cci_state->cci_reg_backup[34];
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cci_state->cci_reg->s_inf[1].qos_range_reg =
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cci_state->cci_reg_backup[35];
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cci_state->cci_reg->s_inf[2].snoop_ctrl_reg =
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cci_state->cci_reg_backup[36];
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cci_state->cci_reg->s_inf[2].share_override_reg =
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cci_state->cci_reg_backup[37];
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cci_state->cci_reg->s_inf[2].rd_channel_qos_val_reg =
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cci_state->cci_reg_backup[38];
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cci_state->cci_reg->s_inf[2].wr_channel_qos_val_reg =
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cci_state->cci_reg_backup[39];
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cci_state->cci_reg->s_inf[2].qos_ctrl_reg =
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cci_state->cci_reg_backup[40];
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cci_state->cci_reg->s_inf[2].max_ot_reg = cci_state->cci_reg_backup[41];
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cci_state->cci_reg->s_inf[2].regu_target_reg =
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cci_state->cci_reg_backup[42];
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cci_state->cci_reg->s_inf[2].qos_regu_scale_factor_reg =
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cci_state->cci_reg_backup[43];
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cci_state->cci_reg->s_inf[2].qos_range_reg =
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cci_state->cci_reg_backup[44];
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cci_state->cci_reg->s_inf[3].snoop_ctrl_reg =
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cci_state->cci_reg_backup[45];
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cci_state->cci_reg->s_inf[3].share_override_reg =
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cci_state->cci_reg_backup[46];
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cci_state->cci_reg->s_inf[3].rd_channel_qos_val_reg =
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cci_state->cci_reg_backup[47];
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cci_state->cci_reg->s_inf[3].wr_channel_qos_val_reg =
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cci_state->cci_reg_backup[48];
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cci_state->cci_reg->s_inf[3].qos_ctrl_reg =
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cci_state->cci_reg_backup[49];
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cci_state->cci_reg->s_inf[3].max_ot_reg = cci_state->cci_reg_backup[50];
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cci_state->cci_reg->s_inf[3].regu_target_reg =
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cci_state->cci_reg_backup[51];
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cci_state->cci_reg->s_inf[3].qos_regu_scale_factor_reg =
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cci_state->cci_reg_backup[52];
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cci_state->cci_reg->s_inf[3].qos_range_reg =
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cci_state->cci_reg_backup[53];
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cci_state->cci_reg->s_inf[4].snoop_ctrl_reg =
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cci_state->cci_reg_backup[54];
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cci_state->cci_reg->s_inf[4].share_override_reg =
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cci_state->cci_reg_backup[55];
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cci_state->cci_reg->s_inf[4].rd_channel_qos_val_reg =
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cci_state->cci_reg_backup[56];
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cci_state->cci_reg->s_inf[4].wr_channel_qos_val_reg =
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cci_state->cci_reg_backup[57];
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cci_state->cci_reg->s_inf[4].qos_ctrl_reg =
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cci_state->cci_reg_backup[58];
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cci_state->cci_reg->s_inf[4].max_ot_reg = cci_state->cci_reg_backup[59];
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cci_state->cci_reg->s_inf[4].regu_target_reg =
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cci_state->cci_reg_backup[60];
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cci_state->cci_reg->s_inf[4].qos_regu_scale_factor_reg =
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cci_state->cci_reg_backup[61];
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cci_state->cci_reg->s_inf[4].qos_range_reg =
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cci_state->cci_reg_backup[62];
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cci_state->cci_reg->c_cnter.cycle_counter_reg =
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cci_state->cci_reg_backup[63];
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cci_state->cci_reg->c_cnter.count_ctrl_reg =
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cci_state->cci_reg_backup[64];
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/* cci_state->cci_reg->c_cnter.overflow_flag_status_reg = cci_state->cci_reg_backup[65]; */
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cci_state->cci_reg->p_cnter[0].event_select_reg =
|
|
cci_state->cci_reg_backup[66];
|
|
cci_state->cci_reg->p_cnter[0].event_count_reg =
|
|
cci_state->cci_reg_backup[67];
|
|
cci_state->cci_reg->p_cnter[0].count_ctrl_reg =
|
|
cci_state->cci_reg_backup[68];
|
|
/* cci_state->cci_reg->p_cnter[0].overflow_flag_status = cci_state->cci_reg_backup[69]; */
|
|
cci_state->cci_reg->p_cnter[1].event_select_reg =
|
|
cci_state->cci_reg_backup[70];
|
|
cci_state->cci_reg->p_cnter[1].event_count_reg =
|
|
cci_state->cci_reg_backup[71];
|
|
cci_state->cci_reg->p_cnter[1].count_ctrl_reg =
|
|
cci_state->cci_reg_backup[72];
|
|
/* cci_state->cci_reg->p_cnter[1].overflow_flag_status = cci_state->cci_reg_backup[73]; */
|
|
cci_state->cci_reg->p_cnter[2].event_select_reg =
|
|
cci_state->cci_reg_backup[74];
|
|
cci_state->cci_reg->p_cnter[2].event_count_reg =
|
|
cci_state->cci_reg_backup[75];
|
|
cci_state->cci_reg->p_cnter[2].count_ctrl_reg =
|
|
cci_state->cci_reg_backup[76];
|
|
/* cci_state->cci_reg->p_cnter[2].overflow_flag_status = cci_state->cci_reg_backup[77]; */
|
|
cci_state->cci_reg->p_cnter[3].event_select_reg =
|
|
cci_state->cci_reg_backup[78];
|
|
cci_state->cci_reg->p_cnter[3].event_count_reg =
|
|
cci_state->cci_reg_backup[79];
|
|
cci_state->cci_reg->p_cnter[3].count_ctrl_reg =
|
|
cci_state->cci_reg_backup[80];
|
|
/* cci_state->cci_reg->p_cnter[3].overflow_flag_status = cci_state->cci_reg_backup[81]; */
|
|
|
|
__asm__ __volatile__("dsb" : : : "memory");
|
|
while (cci_state->cci_reg->status_reg & 0x01)
|
|
;
|
|
|
|
if (debug_mask & PM_STANDBY_PRINT_CCI400_REG) {
|
|
mem_cci400_save(cci_state);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|