509 lines
19 KiB
C
509 lines
19 KiB
C
/*
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* Hibernation support specific for ARM
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*
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* Copyright (C) 2010 Nokia Corporation
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2006 Rafael J. Wysocki <rjw <at> sisk.pl>
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*
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* Contact: Hiroshi DOYU <Hiroshi.DOYU <at> nokia.com>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include "pm_types.h"
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#include "./pm.h"
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unsigned long saved_context_r13_sys[SYS_CONTEXT_SIZE];
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unsigned long saved_cpsr_svc;
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unsigned long saved_context_r12_svc[SVC_CONTEXT_SIZE];
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unsigned long saved_spsr_svc;
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unsigned long saved_context_r13_fiq[FIQ_CONTEXT_SIZE];
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unsigned long saved_spsr_fiq;
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unsigned long saved_context_r13_abt[ABT_CONTEXT_SIZE];
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unsigned long saved_spsr_abt;
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unsigned long saved_context_r13_irq[IRQ_CONTEXT_SIZE];
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unsigned long saved_spsr_irq;
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unsigned long saved_context_r13_und[UND_CONTEXT_SIZE];
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unsigned long saved_spsr_und;
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unsigned long saved_context_r13_mon[MON_CONTEXT_SIZE];
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unsigned long saved_spsr_mon;
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unsigned long saved_empty_context_svc[EMPTY_CONTEXT_SIZE];
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static struct saved_context saved_context;
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static struct saved_context default_copro_value = {
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/* CR0 */
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.cssr = 0x00000002, /* Cache Size Selection */
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/* CR1 */
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#ifdef CORTEX_A8
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.cr = 0x00C52078, /* Control */
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.acr = 0x00000002, /* Auxiliary Control Register */
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.cacr = 0x00000000, /* Coprocessor Access Control */
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.sccfgr = 0x00000000, /* Secure Config Register */
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.scdbgenblr = 0x00000000, /* Secure Debug Enable Register */
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.nonscacctrlr = 0x00000000, /* Nonsecure Access Control Register */
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#elif defined(CORTEX_A9)
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#elif defined(CORTEX_A7)
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.cr = 0x00C50878, /* Control */
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.acr = 0x00006040, /* Auxiliary Control Register: needed for smp */
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.cacr = 0x00000000, /* Coprocessor Access Control */
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.sccfgr = 0x00000000, /* Secure Config Register */
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.scdbgenblr = 0x00000000, /* Secure Debug Enable Register */
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.nonscacctrlr = 0x00000000, /* Nonsecure Access Control Register */
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#endif
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/* CR2 */
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.ttb_0r = 0x00000000, /* Translation Table Base 0 */
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.ttb_1r = 0x00000000, /* Translation Table Base 1 */
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.ttbcr = 0x00000000, /* Translation Talbe Base Control */
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/* CR3 */
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.dacr = 0x00000000, /* Domain Access Control */
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/* CR5 */
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.d_fsr = 0x00000000, /* Data Fault Status */
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.i_fsr = 0x00000000, /* Instruction Fault Status */
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.d_afsr = 0x00000000, /* Data Auxilirary Fault Status */
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.i_afsr = 0x00000000, /* Instruction Auxilirary Fault Status */
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/* CR6 */
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.d_far = 0x00000000, /* Data Fault Address */
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.i_far = 0x00000000, /* Instruction Fault Address */
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/* CR7 */
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.par = 0x00000000, /* Physical Address */
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/* CR9 FIXME: Are they necessary */
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.pmcontrolr = 0x00000000, /* Performance Monitor Control */
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.cesr = 0x00000000, /* Count Enable Set */
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.cecr = 0x00000000, /* Count Enable Clear */
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.ofsr = 0x00000000, /* Overflow Flag Status */
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#ifdef CORTEX_A8
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.sir = 0x00000000, /* Software Increment */
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#elif defined(CORTEX_A7)
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.sir = 0x00000000, /* Software Increment */
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#endif
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.pcsr = 0x00000000, /* Performance Counter Selection */
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.ccr = 0x00000000, /* Cycle Count */
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.esr = 0x00000000, /* Event Selection */
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.pmcountr = 0x00000000, /* Performance Monitor Count */
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.uer = 0x00000000, /* User Enable */
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.iesr = 0x00000000, /* Interrupt Enable Set */
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.iecr = 0x00000000, /* Interrupt Enable Clear */
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#ifdef CORTEX_A8
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.l2clr = 0x00000000, /* L2 Cache Lockdown */
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.l2cauxctrlr = 0x00000042, /* L2 Cache Auxiliary Control */
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#elif defined(CORTEX_A7)
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#endif
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/* CR10 */
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#ifdef CORTEX_A8
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.d_tlblr = 0x00000000, /* Data TLB Lockdown Register */
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.i_tlblr = 0x00000000, /* Instruction TLB Lockdown Register */
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#elif defined(CORTEX_A7)
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#endif
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.prrr = 0x000A81A4, /* Primary Region Remap Register: tex[0], c, b = 010, + A => normal memory
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* tex[0], c, b = 100 || 101, + 1 => strong order or device
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*/
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.nrrr = 0x44E048E0, /* Normal Memory Remap Register */
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/* .prrr = 0xFF0A81A8, Primary Region Remap Register */
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/* .nrrr = 0x40E040E0, Normal Memory Remap Register */
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/* CR11 */
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#ifdef CORTEX_A8
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.pleuar = 0x00000000, /* PLE User Accessibility */
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.plecnr = 0x00000000, /* PLE Channel Number */
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.plecr = 0x00000000, /* PLE Control */
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.pleisar = 0x00000000, /* PLE Internal Start Address */
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.pleiear = 0x00000000, /* PLE Internal End Address */
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.plecidr = 0x00000000, /* PLE Context ID */
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#elif defined(CORTEX_A7)
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#endif
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/* CR12 */
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#ifdef CORTEX_A8
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.snsvbar = 0x00000000, /* Secure or Nonsecure Vector Base Address */
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.monvecbar = 0x00000000, /*Monitor Vector Base */
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#elif defined(CORTEX_A9)
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#elif defined(CORTEX_A7)
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/* only accessable from secure world. */
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#endif
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/* CR13 */
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.fcse = 0x00000000, /* FCSE PID */
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.cid = 0x00000000, /* Context ID */
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.urwtpid = 0x00000000, /* User read/write Thread and Process ID */
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.urotpid = 0x00000000, /* User read-only Thread and Process ID */
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.potpid = 0x00000000, /* Privileged only Thread and Process ID */
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};
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/*__save_processor_state: store the co-processor state into to location point by ctxt
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*@ctxt: indicate where to store co-processor state.
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*/
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void __save_processor_state(struct saved_context *ctxt)
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{
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/* CR0 */
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/* save_mem_status(0x101); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (ctxt->cssr));
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/* CR1 */
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#ifdef CORTEX_A8
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/* save_mem_status(0x102); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (ctxt->cr));
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asm volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (ctxt->cacr));
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#elif defined(CORTEX_A9)
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asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (ctxt->cr));
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (ctxt->actlr));
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asm volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (ctxt->cacr));
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asm volatile ("mrc p15, 0, %0, c1, c1, 1" : "=r" (ctxt->sder));
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asm volatile ("mrc p15, 0, %0, c1, c1, 3" : "=r" (ctxt->vcr));
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#elif defined(CORTEX_A7)
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asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (ctxt->cr));
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asm volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (ctxt->cacr));
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#endif
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/* CR2 */
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/* save_mem_status(0x103); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (ctxt->ttb_0r));
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asm volatile ("mrc p15, 0, %0, c2, c0, 1" : "=r" (ctxt->ttb_1r));
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asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (ctxt->ttbcr));
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/* CR3 */
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/* save_mem_status(0x104); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (ctxt->dacr));
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/* CR5 */
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/* save_mem_status(0x105); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (ctxt->d_fsr));
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asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (ctxt->i_fsr));
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asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r" (ctxt->d_afsr));
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asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r" (ctxt->i_afsr));
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/* save_mem_status(0x106); */
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/* busy_waiting(); */
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/* CR6 */
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asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (ctxt->d_far));
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asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r" (ctxt->i_far));
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/* CR7 */
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/* save_mem_status(0x107); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c7, c4, 0" : "=r" (ctxt->par));
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/* CR9 */
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/* save_mem_status(0x108); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r" (ctxt->pmcontrolr));
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asm volatile ("mrc p15, 0, %0, c9, c12, 1" : "=r" (ctxt->cesr));
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asm volatile ("mrc p15, 0, %0, c9, c12, 2" : "=r" (ctxt->cecr));
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asm volatile ("mrc p15, 0, %0, c9, c12, 3" : "=r" (ctxt->ofsr));
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#ifdef CORTEX_A8
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/* save_mem_status(0x109); */
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/* busy_waiting(); */
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/* asm volatile ("mrc p15, 0, %0, c9, c12, 4" : "=r"(ctxt->sir)); */
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#elif defined(CORTEX_A7)
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/* busy_waiting(); */
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/* asm volatile ("mrc p15, 0, %0, c9, c12, 4" : "=r"(ctxt->sir)); */
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#endif
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/* save_mem_status(0x10a); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c9, c12, 5" : "=r" (ctxt->pcsr));
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asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r" (ctxt->ccr));
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asm volatile ("mrc p15, 0, %0, c9, c13, 1" : "=r" (ctxt->esr));
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asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r" (ctxt->pmcountr));
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asm volatile ("mrc p15, 0, %0, c9, c14, 0" : "=r" (ctxt->uer));
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asm volatile ("mrc p15, 0, %0, c9, c14, 1" : "=r" (ctxt->iesr));
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asm volatile ("mrc p15, 0, %0, c9, c14, 2" : "=r" (ctxt->iecr));
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#ifdef CORTEX_A8
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/* save_mem_status(0x10b); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 1, %0, c9, c0, 0" : "=r" (ctxt->l2clr));
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asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ctxt->l2cauxctrlr));
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#elif defined(CORTEX_A7)
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#endif
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/* CR10 */
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#ifdef CORTEX_A8
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/* save_mem_status(0x10c); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c10, c0, 0" : "=r" (ctxt->d_tlblr));
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/* save_mem_status(0x10d); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 0, %0, c10, c0, 1" : "=r" (ctxt->i_tlblr));
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#elif defined(CORTEX_A7)
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#endif
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asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r" (ctxt->prrr));
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asm volatile ("mrc p15, 0, %0, c10, c2, 1" : "=r" (ctxt->nrrr));
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/* CR11 */
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#ifdef CORTEX_A8
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asm volatile ("mrc p15, 0, %0, c11, c1, 0" : "=r" (ctxt->pleuar));
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asm volatile ("mrc p15, 0, %0, c11, c2, 0" : "=r" (ctxt->plecnr));
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asm volatile ("mrc p15, 0, %0, c11, c4, 0" : "=r" (ctxt->plecr));
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asm volatile ("mrc p15, 0, %0, c11, c5, 0" : "=r" (ctxt->pleisar));
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asm volatile ("mrc p15, 0, %0, c11, c7, 0" : "=r" (ctxt->pleiear));
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asm volatile ("mrc p15, 0, %0, c11, c15, 0" : "=r" (ctxt->plecidr));
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#elif defined(CORTEX_A7)
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#endif
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/* CR12 */
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#ifdef CORTEX_A8
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asm volatile ("mrc p15, 0, %0, c12, c0, 0" : "=r" (ctxt->snsvbar));
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asm volatile ("mrc p15, 0, %0, c12, c0, 1" : "=r" (ctxt->monvecbar));
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#elif defined(CORTEX_A9)
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asm volatile ("mrc p15, 0, %0, c12, c0, 0" : "=r" (ctxt->vbar));
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asm volatile ("mrc p15, 0, %0, c12, c0, 1" : "=r" (ctxt->mvbar));
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asm volatile ("mrc p15, 0, %0, c12, c1, 1" : "=r" (ctxt->vir));
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#elif defined(CORTEX_A7)
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/* only accessable from secure world. */
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asm volatile ("mrc p15, 0, %0, c12, c0, 0" : "=r" (ctxt->vbar));
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/* asm volatile ("mrc p15, 0, %0, c12, c0, 1" : "=r"(ctxt->mvbar)); */
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/* asm volatile ("mrc p15, 0, %0, c12, c1, 0" : "=r"(ctxt->isr)); */
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#endif
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/* CR13 */
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/* save_mem_status(0x10e); */
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/* busy_waiting(); */
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/* asm volatile ("mrc p15, 0, %0, c13, c0, 0" : "=r"(ctxt->fcse)); */
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asm volatile ("mrc p15, 0, %0, c13, c0, 1" : "=r" (ctxt->cid));
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asm volatile ("mrc p15, 0, %0, c13, c0, 2" : "=r" (ctxt->urwtpid));
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asm volatile ("mrc p15, 0, %0, c13, c0, 3" : "=r" (ctxt->urotpid));
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asm volatile ("mrc p15, 0, %0, c13, c0, 4" : "=r" (ctxt->potpid));
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/* CR15 */
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#ifdef CORTEX_A9
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/* save_mem_status(0x10f); */
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/* busy_waiting(); */
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asm volatile ("mrc p15, 5, %0, c15, c7, 2" : "=r" (ctxt->mtlbar));
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#endif
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}
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/*__restore_processor_state: restore the co-processor state according the info point by ctxt
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*@ctxt: indicate where to get the backuped co-processor state.
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*/
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void __restore_processor_state(struct saved_context *ctxt)
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{
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/* CR0 */
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asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (ctxt->cssr));
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/* CR1 */
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#if defined(CORTEX_A8)
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/* busy_waiting(); */
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/* asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ctxt->cr)); //will effect visible addr space, cache, instruction prediction */
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asm volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (ctxt->cacr));
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#elif defined(CORTEX_A9)
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/* asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ctxt->cr)); */
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/* busy_waiting(); */
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asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (ctxt->actlr));
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asm volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (ctxt->cacr));
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asm volatile ("mcr p15, 0, %0, c1, c1, 1" : : "r" (ctxt->sder));
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asm volatile ("mcr p15, 0, %0, c1, c1, 3" : : "r" (ctxt->vcr));
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#elif defined(CORTEX_A7)
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asm volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (ctxt->cacr));
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#endif
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/* CR2 */
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asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ctxt->ttb_0r));
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asm volatile ("dsb");
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asm volatile ("isb");
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asm volatile ("mcr p15, 0, %0, c2, c0, 1" : : "r" (ctxt->ttb_1r));
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asm volatile ("dsb");
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asm volatile ("isb");
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asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (ctxt->ttbcr));
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asm volatile ("dsb");
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asm volatile ("isb");
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/* flush_tlb_all(); */
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/* CR3 */
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asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (ctxt->dacr));
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/* CR7 */
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asm volatile ("mcr p15, 0, %0, c7, c4, 0" : : "r" (ctxt->par));
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/* CR9 */
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asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r" (ctxt->pcsr));
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asm volatile ("mcr p15, 0, %0, c9, c13, 0" : : "r" (ctxt->ccr));
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asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r" (ctxt->esr));
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asm volatile ("mcr p15, 0, %0, c9, c13, 2" : : "r" (ctxt->pmcountr));
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asm volatile ("mcr p15, 0, %0, c9, c14, 0" : : "r" (ctxt->uer));
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asm volatile ("mcr p15, 0, %0, c9, c14, 1" : : "r" (ctxt->iesr));
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asm volatile ("mcr p15, 0, %0, c9, c14, 2" : : "r" (ctxt->iecr));
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#ifdef CORTEX_A8
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asm volatile ("mcr p15, 1, %0, c9, c0, 0" : : "r" (ctxt->l2clr));
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asm volatile ("mcr p15, 1, %0, c9, c0, 2" : : "r" (ctxt->l2cauxctrlr));
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#elif defined(CORTEX_A7)
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#endif
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/* CR10 */
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asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r" (ctxt->prrr));
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asm volatile ("mcr p15, 0, %0, c10, c2, 1" : : "r" (ctxt->nrrr));
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/* CR11 */
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#ifdef CORTEX_A8
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asm volatile ("mcr p15, 0, %0, c11, c1, 0" : : "r" (ctxt->pleuar));
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asm volatile ("mcr p15, 0, %0, c11, c2, 0" : : "r" (ctxt->plecnr));
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asm volatile ("mcr p15, 0, %0, c11, c4, 0" : : "r" (ctxt->plecr));
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asm volatile ("mcr p15, 0, %0, c11, c5, 0" : : "r" (ctxt->pleisar));
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asm volatile ("mcr p15, 0, %0, c11, c7, 0" : : "r" (ctxt->pleiear));
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asm volatile ("mcr p15, 0, %0, c11, c15, 0" : : "r" (ctxt->plecidr));
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#elif defined(CORTEX_A7)
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#endif
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/* CR12 */
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#ifdef CORTEX_A8
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asm volatile ("mcr p15, 0, %0, c12, c0, 0" : : "r" (ctxt->snsvbar));
|
|
asm volatile ("mcr p15, 0, %0, c12, c0, 1" : : "r" (ctxt->monvecbar));
|
|
#elif defined(CORTEX_A9)
|
|
asm volatile ("mcr p15, 0, %0, c12, c0, 0" : : "r" (ctxt->vbar));
|
|
asm volatile ("mcr p15, 0, %0, c12, c0, 1" : : "r" (ctxt->mvbar));
|
|
asm volatile ("mcr p15, 0, %0, c12, c1, 1" : : "r" (ctxt->vir));
|
|
#elif defined(CORTEX_A7)
|
|
/* only accessable from secure world. */
|
|
asm volatile ("mcr p15, 0, %0, c12, c0, 0" : : "r" (ctxt->vbar));
|
|
/* asm volatile ("mcr p15, 0, %0, c12, c0, 1" : : "r"(ctxt->mvbar)); */
|
|
/* asm volatile ("mcr p15, 0, %0, c12, c1, 0" : : "r"(ctxt->isr)); */
|
|
#endif
|
|
|
|
/* CR13 */
|
|
/* asm volatile ("mcr p15, 0, %0, c13, c0, 0" : : "r"(ctxt->fcse)); */
|
|
asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r" (ctxt->cid));
|
|
asm volatile ("mcr p15, 0, %0, c13, c0, 2" : : "r" (ctxt->urwtpid));
|
|
asm volatile ("mcr p15, 0, %0, c13, c0, 3" : : "r" (ctxt->urotpid));
|
|
asm volatile ("mcr p15, 0, %0, c13, c0, 4" : : "r" (ctxt->potpid));
|
|
|
|
/* CR15 */
|
|
#ifdef CORTEX_A9
|
|
asm volatile ("mcr p15, 5, %0, c15, c7, 2" : : "r" (ctxt->mtlbar));
|
|
#endif
|
|
|
|
asm volatile ("dsb");
|
|
asm volatile ("isb");
|
|
}
|
|
|
|
/*disable_cache_invalidate: disable invalidate cache when cpu reset.
|
|
*/
|
|
void disable_cache_invalidate(void)
|
|
{
|
|
#define CPU_CONFIG_REG (0XF1C20D3C)
|
|
__u32 val = *(volatile __u32 *)(CPU_CONFIG_REG);
|
|
val &= (~0x3);
|
|
val |= 0x03; /* disable invalidate */
|
|
*(volatile __u32 *)(CPU_CONFIG_REG) = val;
|
|
|
|
return;
|
|
}
|
|
|
|
/*set_copro_default: set co-processor to default state.
|
|
*note: the api will effect visible addr space, be careful to call it.
|
|
*/
|
|
void set_copro_default(void)
|
|
{
|
|
struct saved_context *ctxt = &default_copro_value;
|
|
/* CR0 */
|
|
asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (ctxt->cssr));
|
|
/* CR1 */
|
|
#ifdef CORTEX_A8
|
|
/* busy_waiting(); */
|
|
asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (ctxt->cr)); /* will effect visible addr space */
|
|
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (ctxt->acr)); /* ? */
|
|
asm volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (ctxt->cacr));
|
|
asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (ctxt->sccfgr)); /* ? */
|
|
asm volatile ("mcr p15, 0, %0, c1, c1, 1" : : "r" (ctxt->scdbgenblr)); /* ? */
|
|
asm volatile ("mcr p15, 0, %0, c1, c1, 2" : : "r" (ctxt->nonscacctrlr)); /* ? */
|
|
#elif defined(CORTEX_A7)
|
|
asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (ctxt->cr)); /* will effect visible addr space */
|
|
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (ctxt->acr)); /* ? */
|
|
asm volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (ctxt->cacr));
|
|
#endif
|
|
|
|
/* CR2 */
|
|
asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ctxt->ttb_0r));
|
|
/* flush_tlb_all(); */
|
|
asm volatile ("mcr p15, 0, %0, c2, c0, 1" : : "r" (ctxt->ttb_1r));
|
|
asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (ctxt->ttbcr));
|
|
/* CR3 */
|
|
asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (ctxt->dacr));
|
|
/* CR5 */
|
|
asm volatile ("mcr p15, 0, %0, c5, c0, 0" : : "r" (ctxt->d_fsr));
|
|
asm volatile ("mcr p15, 0, %0, c5, c0, 1" : : "r" (ctxt->i_fsr));
|
|
asm volatile ("mcr p15, 0, %0, c5, c1, 0" : : "r" (ctxt->d_afsr));
|
|
asm volatile ("mcr p15, 0, %0, c5, c1, 1" : : "r" (ctxt->i_afsr));
|
|
/* CR6 */
|
|
asm volatile ("mcr p15, 0, %0, c6, c0, 0" : : "r" (ctxt->d_far));
|
|
asm volatile ("mcr p15, 0, %0, c6, c0, 2" : : "r" (ctxt->i_far));
|
|
/* CR7 */
|
|
asm volatile ("mcr p15, 0, %0, c7, c4, 0" : : "r" (ctxt->par));
|
|
|
|
/* CR9 */
|
|
asm volatile ("mcr p15, 0, %0, c9, c14, 0" : : "r" (ctxt->uer));
|
|
asm volatile ("mcr p15, 0, %0, c9, c14, 1" : : "r" (ctxt->iesr));
|
|
asm volatile ("mcr p15, 0, %0, c9, c14, 2" : : "r" (ctxt->iecr));
|
|
#ifdef CORTEX_A8
|
|
asm volatile ("mcr p15, 1, %0, c9, c0, 0" : : "r" (ctxt->l2clr));
|
|
asm volatile ("mcr p15, 1, %0, c9, c0, 2" : : "r" (ctxt->l2cauxctrlr)); /* ? */
|
|
#elif defined(CORTEX_A7)
|
|
#endif
|
|
|
|
/* CR10 */
|
|
#ifdef CORTEX_A8
|
|
asm volatile ("mcr p15, 0, %0, c10, c0, 0" : : "r" (ctxt->d_tlblr));
|
|
asm volatile ("mcr p15, 0, %0, c10, c0, 1" : : "r" (ctxt->i_tlblr));
|
|
#elif defined(CORTEX_A7)
|
|
#endif
|
|
asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r" (ctxt->prrr));
|
|
asm volatile ("mcr p15, 0, %0, c10, c2, 1" : : "r" (ctxt->nrrr));
|
|
|
|
/* CR11 */
|
|
#ifdef CORTEX_A8
|
|
asm volatile ("mcr p15, 0, %0, c11, c1, 0" : : "r" (ctxt->pleuar));
|
|
asm volatile ("mcr p15, 0, %0, c11, c2, 0" : : "r" (ctxt->plecnr));
|
|
asm volatile ("mcr p15, 0, %0, c11, c4, 0" : : "r" (ctxt->plecr));
|
|
asm volatile ("mcr p15, 0, %0, c11, c5, 0" : : "r" (ctxt->pleisar));
|
|
asm volatile ("mcr p15, 0, %0, c11, c7, 0" : : "r" (ctxt->pleiear));
|
|
asm volatile ("mcr p15, 0, %0, c11, c15, 0" : : "r" (ctxt->plecidr));
|
|
#elif defined(CORTEX_A7)
|
|
#endif
|
|
|
|
/* CR12 */
|
|
#ifdef CORTEX_A8
|
|
asm volatile ("mcr p15, 0, %0, c12, c0, 0" : : "r" (ctxt->snsvbar));
|
|
asm volatile ("mcr p15, 0, %0, c12, c0, 1" : : "r" (ctxt->monvecbar)); /* ? */
|
|
#elif defined(CORTEX_A7)
|
|
/* asm volatile ("mcr p15, 0, %0, c12, c1, 0" : : "r"(ctxt->isr)); */
|
|
#endif
|
|
|
|
/* CR13 */
|
|
/* asm volatile ("mcr p15, 0, %0, c13, c0, 0" : : "r"(ctxt->fcse)); */
|
|
asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r" (ctxt->cid));
|
|
asm volatile ("mcr p15, 0, %0, c13, c0, 2" : : "r" (ctxt->urwtpid));
|
|
asm volatile ("mcr p15, 0, %0, c13, c0, 3" : : "r" (ctxt->urotpid));
|
|
asm volatile ("mcr p15, 0, %0, c13, c0, 4" : : "r" (ctxt->potpid));
|
|
|
|
asm volatile ("dsb");
|
|
asm volatile ("isb");
|
|
|
|
return;
|
|
}
|
|
|
|
/*save_processor_state: save current co-proccessor state.*/
|
|
void save_processor_state(void)
|
|
{
|
|
__save_processor_state(&saved_context);
|
|
}
|
|
|
|
/*restore_processor_state: restore */
|
|
void restore_processor_state(void)
|
|
{
|
|
__restore_processor_state(&saved_context);
|
|
}
|
|
|
|
void restore_processor_ttbr0(void)
|
|
{
|
|
asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (saved_context.ttb_0r));
|
|
return;
|
|
}
|
|
|
|
void set_ttbr0(void)
|
|
{
|
|
__u32 ttb = 0;
|
|
/* read ttbr1 */
|
|
asm volatile ("mrc p15, 0, %0, c2, c0, 1" : "=r" (ttb));
|
|
/* write ttbr0 */
|
|
asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb));
|
|
asm volatile ("isb");
|
|
return;
|
|
}
|