139 lines
3.4 KiB
C
139 lines
3.4 KiB
C
/*
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* Hibernation support specific for ARM
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*
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* Copyright (C) 2010 Nokia Corporation
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2006 Rafael J. Wysocki <rjw <at> sisk.pl>
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*
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* Contact: Hiroshi DOYU <Hiroshi.DOYU <at> nokia.com>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/module.h>
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#include <linux/suspend.h>
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#include <linux/cdev.h>
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#include <linux/fs.h>
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#include <linux/module.h>
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#include <linux/syscalls.h>
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#include <linux/slab.h>
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#include <linux/major.h>
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#include <linux/device.h>
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#include <asm/uaccess.h>
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#include <asm/delay.h>
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#include <linux/power/aw_pm.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/mach/map.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/pgtable.h>
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#include "pm_o.h"
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/*
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* "Linux" PTE definitions.
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*
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* We keep two sets of PTEs - the hardware and the linux version.
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* This allows greater flexibility in the way we map the Linux bits
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* onto the hardware tables, and allows us to have YOUNG and DIRTY
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* bits.
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*
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* The PTE table pointer refers to the hardware entries; the "Linux"
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* entries are stored 1024 bytes below.
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*/
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#define L_PTE_WRITE (1 << 7)
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#define L_PTE_EXEC (1 << 9)
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#define PAGE_TBL_ADDR (0xc0004000)
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struct saved_mmu_level_one {
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u32 vaddr;
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u32 entry_val;
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};
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static struct saved_mmu_level_one backup_tbl[1];
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/*
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* Create the page directory entries for 0x0000,0000 <-> 0x0000,0000
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*/
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void create_mapping(void)
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{
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*((volatile __u32 *)(PAGE_TBL_ADDR)) = 0xc4a;
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/**
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* clean dcache,, invalidat icache&invalidate tlb,
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*
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* function:
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* to make sure the correct PA will be access.
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*
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* cache:
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* clean cache unit: is cache line size;
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* whether the end addr will be flush? exclusive,not including.
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*
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* tlb:
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* invalidate tlb unit: PAGE_SIZE;
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* Not including end addr.
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*
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* Note:
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* actually, because the PA will be used at resume period time,
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* mean, not use immediately,
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* and, the cache will be clean at the end.
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* so, the clean&invalidate is not necessary.
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* do this here, just in case testing. like: jump to resume code for testing.
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**/
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/* Note: 0xc000,0000,is device area; not need to flush cache. */
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/* ref: ./arch/arm/kernel/head.S */
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__cpuc_coherent_kern_range((unsigned long)(PAGE_TBL_ADDR),
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(unsigned long)(PAGE_TBL_ADDR +
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(sizeof(u32))));
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local_flush_tlb_kernel_range((unsigned long)(PAGE_TBL_ADDR),
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(unsigned long)(PAGE_TBL_ADDR +
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(sizeof(u32))));
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return;
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}
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/**save the va: 0x0000,0000 mapping.
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*@vaddr: the va of mmu mapping to save;
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*/
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void save_mapping(unsigned long vaddr)
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{
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unsigned long addr;
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/* busy_waiting(); */
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addr = vaddr & PAGE_MASK;
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/* __cpuc_flush_kern_all(); */
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backup_tbl[0].vaddr = addr;
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backup_tbl[0].entry_val = *((volatile __u32 *)(PAGE_TBL_ADDR));
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/* flush_tlb_all(); */
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return;
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}
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/**restore the va: 0x0000,0000 mapping.
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*@vaddr: the va of mmu mapping to restore.
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*
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*/
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void restore_mapping(unsigned long vaddr)
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{
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unsigned long addr;
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addr = vaddr & PAGE_MASK;
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if (addr != backup_tbl[0].vaddr) {
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while (1)
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;
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}
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*((volatile __u32 *)(PAGE_TBL_ADDR)) = backup_tbl[0].entry_val;
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/* clean dcache, invalidat icache */
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__cpuc_coherent_kern_range((unsigned long)(PAGE_TBL_ADDR),
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(unsigned long)(PAGE_TBL_ADDR +
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(sizeof(u32))));
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/* flust tlb after change mmu mapping. */
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local_flush_tlb_kernel_range((unsigned long)(PAGE_TBL_ADDR),
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(unsigned long)(PAGE_TBL_ADDR +
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(sizeof(u32))));
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return;
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}
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