280 lines
9.7 KiB
C
280 lines
9.7 KiB
C
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/*
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* Copyright (c) 2011-2015 yanggq.young@allwinnertech.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#ifndef _PM_H
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#define _PM_H
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#if defined(CONFIG_ARCH_SUN8IW6P1) || defined(CONFIG_ARCH_SUN8IW5P1)
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#include "pm_types.h"
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#include "pm_config.h"
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#include "pm_errcode.h"
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#include "pm_debug.h"
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#include "pm_of.h"
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#include <linux/of.h>
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include "mem_cpu.h"
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#include "mem_ccmu.h"
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#include "mem_serial.h"
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#include "mem_key.h"
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#include "mem_ir.h"
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/* #include "mem_twi.h" */
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#include "mem_usb.h"
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#include "mem_printk.h"
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#include "mem_divlibc.h"
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#include "mem_int.h"
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#include "mem_gpio.h"
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#include "mem_tmr.h"
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#include "mem_tmstmp.h"
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#include "mem_clk.h"
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#include "mem_timing.h"
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#include "mem_mapping.h"
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#include "mem_hwspinlock.h"
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#ifdef CONFIG_ARCH_SUN9IW1P1
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#include "mem_cci400.h"
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#include "mem_gtbus.h"
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#endif
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#include "linux/power/aw_pm.h"
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/* extern __u32 debug_mask; */
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typedef enum {
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PM_STANDBY_PRINT_STANDBY = (1U << 0),
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PM_STANDBY_PRINT_RESUME = (1U << 1),
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PM_STANDBY_ENABLE_JTAG = (1U << 2),
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PM_STANDBY_PRINT_PORT = (1U << 3),
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PM_STANDBY_PRINT_IO_STATUS = (1U << 4),
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PM_STANDBY_PRINT_CACHE_TLB_MISS = (1U << 5),
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PM_STANDBY_PRINT_CCU_STATUS = (1U << 6),
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PM_STANDBY_PRINT_PWR_STATUS = (1U << 7),
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PM_STANDBY_PRINT_CPUS_IO_STATUS = (1U << 8),
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PM_STANDBY_PRINT_CCI400_REG = (1U << 9),
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PM_STANDBY_PRINT_GTBUS_REG = (1U << 10),
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PM_STANDBY_TEST = (1U << 11),
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PM_STANDBY_PRINT_RESUME_IO_STATUS = (1U << 12)
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} debug_mask_flag;
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extern unsigned int parse_bitmap_en;
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typedef enum {
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DEBUG_WAKEUP_SRC = (0x01 << 0),
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DEBUG_WAKEUP_GPIO_MAP = (0x01 << 1),
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DEBUG_WAKEUP_GPIO_GROUP_MAP = (0x01 << 2),
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DEBUG_PWR_DM_MAP = (0x01 << 3)
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} parse_bitmap_en_flag;
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#define likely(x) __builtin_expect(!!(x), 1)
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#define unlikely(x) __builtin_expect(!!(x), 0)
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#define uk_printf(s, size, fmt, args...) do { \
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if (NULL != s) { \
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s += scnprintf(s, size, fmt, ## args); \
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} else { \
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printk(fmt, ## args); \
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} \
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} while (0)
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struct mmu_state {
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/* CR0 */
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__u32 cssr; /* Cache Size Selection */
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/* CR1 */
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__u32 cr; /* Control */
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__u32 cacr; /* Coprocessor Access Control */
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/* CR2 */
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__u32 ttb_0r; /* Translation Table Base 0 */
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__u32 ttb_1r; /* Translation Table Base 1 */
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__u32 ttbcr; /* Translation Talbe Base Control */
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/* CR3 */
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__u32 dacr; /* Domain Access Control */
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/*cr10 */
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__u32 prrr; /* Primary Region Remap Register */
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__u32 nrrr; /* Normal Memory Remap Register */
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/* mon sp */
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__u32 mon_sp;
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__u32 svc_sp;
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};
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/**
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*@brief struct of super mem
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*/
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struct aw_mem_para {
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void **resume_pointer;
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volatile __u32 mem_flag;
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__u32 monitor_vector;
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__u32 axp_event;
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__u32 sys_event;
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__u32 debug_mask;
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__u32 suspend_delay_ms;
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__u32 saved_runtime_context_svc[RUNTIME_CONTEXT_SIZE];
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struct clk_div_t clk_div;
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struct clk_misc_t clk_misc; /* miscellaneous para. */
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struct pll_factor_t pll_factor;
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struct mmu_state saved_mmu_state;
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struct mmu_state saved_secure_mmu_state;
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};
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typedef int (*suspend_func) (void);
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/*mem_mmu_pc_asm.S*/
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extern unsigned int save_sp_nommu(void);
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extern unsigned int save_sp(void);
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extern void clear_reg_context(void);
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extern void restore_sp(unsigned int sp);
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/* cache */
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extern void invalidate_dcache(void);
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extern void flush_icache(void);
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extern void flush_dcache(void);
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extern void disable_cache(void);
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extern void disable_dcache(void);
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extern void disable_l2cache(void);
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extern void enable_cache(void);
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extern void enable_icache(void);
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extern void disable_program_flow_prediction(void);
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extern void invalidate_branch_predictor(void);
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extern void enable_program_flow_prediction(void);
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extern void mem_flush_tlb(void);
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extern void mem_preload_tlb(void);
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void disable_mmu(void);
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void enable_mmu(void);
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extern int jump_to_resume(void *pointer, __u32 *addr);
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extern int jump_to_resume0(void *pointer);
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void jump_to_suspend(__u32 ttbr1, suspend_func p);
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extern int jump_to_resume0_nommu(void *pointer);
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/*mmu_pc.c*/
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extern void save_mmu_state(struct mmu_state *saved_mmu_state);
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extern void restore_mmu_state(struct mmu_state *saved_mmu_state);
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extern void restore_secure_mmu_state(struct mmu_state *saved_mmu_state);
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void set_ttbr0(void);
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extern void invalidate_dcache(void);
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typedef struct __MEM_TWIC_REG {
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volatile __u32 reg_saddr;
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volatile __u32 reg_xsaddr;
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volatile __u32 reg_data;
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volatile __u32 reg_ctl;
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volatile __u32 reg_status;
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volatile __u32 reg_clkr;
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volatile __u32 reg_reset;
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volatile __u32 reg_efr;
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volatile __u32 reg_lctl;
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} __mem_twic_reg_t;
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struct gic_distributor_state {
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/* distributor */
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volatile __u32 GICD_CTLR; /* offset 0x00, distributor Contrl reg */
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volatile __u32 GICD_IGROUPRn; /* offset 0x80, Interrupt Grp Reg ? */
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volatile __u32 GICD_ISENABLERn[0x180 / 4]; /* offset 0x100-0x17c, Interrupt Set-Enable Reg */
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volatile __u32 GICD_ICENABLERn[0x180 / 4]; /* offset 0x180-0x1fc, Iterrupt Clear-Enable Reg */
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volatile __u32 GICD_ISPENDRn[0x180 / 4]; /* offset 0x200-0x27c, Iterrupt Set-Pending Reg */
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volatile __u32 GICD_ICPENDRn[0x180 / 4]; /* offset 0x280-0x2fc, Iterrupt Clear-Pending Reg */
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volatile __u32 GICD_ISACTIVERn[0x180 / 4]; /* offset 0x300-0x37c, GICv2 Iterrupt Set-Active Reg */
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volatile __u32 GICD_ICACTIVERn[0x180 / 4]; /* offset 0x380-0x3fc, Iterrupt Clear-Active Reg */
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volatile __u32 GICD_IPRIORITYRn[0x180 / 4]; /* offset 0x400-0x7F8, Iterrupt Priority Reg */
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volatile __u32 GICD_ITARGETSRn[(0x400 - 0x20) / 4]; /* offset 0x820-0xbf8, Iterrupt Processor Targets Reg */
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volatile __u32 GICD_ICFGRn[0x100 / 4]; /* offset 0xc00-0xcfc, Iterrupt Config Reg */
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volatile __u32 GICD_NSACRn[0x100 / 4]; /* offset 0xE00-0xEfc, non-secure Access Ctrl Reg ? */
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volatile __u32 GICD_CPENDSGIRn[0x10 / 4]; /* offset 0xf10-0xf1c, SGI Clear-Pending Reg */
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volatile __u32 GICD_SPENDSGIRn[0x10 / 4]; /* offset 0xf20-0xf2c, SGI Set-Pending Reg */
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};
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struct gic_cpu_interface_state {
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/* cpu interface reg */
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volatile __u32 GICC_CTLR_PMR_BPR[0xc / 4]; /* offset 0x00-0x08, cpu interface Ctrl Reg + Interrupt Priority Mask Reg + Binary Point Reg */
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volatile __u32 GICC_ABPR; /* offset 0x1c, Aliased Binary Point Reg */
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volatile __u32 GICC_APRn[0x10 / 4]; /* offset 0xd0-0xdc, Active Priorities Reg */
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volatile __u32 GICC_NSAPRn[0x10 / 4]; /* offset 0xe0-0xec, Non-secure Active Priorities Reg */
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};
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struct gic_distributor_disc {
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/* distributor */
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volatile __u32 GICD_CTLR; /* offset 0x00, distributor Contrl reg */
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volatile __u32 reserved0[0x7c / 4]; /* 0ffset 0x04-0x7c */
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volatile __u32 GICD_IGROUPRn; /* offset 0x80, Interrupt Grp Reg ? */
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volatile __u32 reserved1[0x7c / 4]; /* 0ffset 0x84-0xfc */
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volatile __u32 GICD_ISENABLERn[0x180 / 4]; /* offset 0x100-0x17c, Interrupt Set-Enable Reg */
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volatile __u32 GICD_ICENABLERn[0x180 / 4]; /* offset 0x180-0x1fc, Iterrupt Clear-Enable Reg */
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volatile __u32 GICD_ISPENDRn[0x180 / 4]; /* offset 0x200-0x27c, Iterrupt Set-Pending Reg */
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volatile __u32 GICD_ICPENDRn[0x180 / 4]; /* offset 0x280-0x2fc, Iterrupt Clear-Pending Reg */
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volatile __u32 GICD_ISACTIVERn[0x180 / 4]; /* offset 0x300-0x37c, GICv2 Iterrupt Set-Active Reg */
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volatile __u32 GICD_ICACTIVERn[0x180 / 4]; /* offset 0x380-0x3fc, Iterrupt Clear-Active Reg */
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volatile __u32 GICD_IPRIORITYRn[0x180 / 4]; /* offset 0x400-0x7F8, Iterrupt Priority Reg */
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volatile __u32 reserved2[0x24 / 4]; /* 0ffset 0x7fc-0x81c */
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volatile __u32 GICD_ITARGETSRn[(0x400 - 0x20) / 4]; /* offset 0x820-0xbf8, Iterrupt Processor Targets Reg */
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volatile __u32 reserved3; /* 0ffset 0xbfc */
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volatile __u32 GICD_ICFGRn[0x100 / 4]; /* offset 0xc00-0xcfc, Iterrupt Config Reg */
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volatile __u32 reserved4[0x100 / 4]; /* 0ffset 0xd00-0xdfc */
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volatile __u32 GICD_NSACRn[0x100 / 4]; /* offset 0xE00-0xEfc, non-secure Access Ctrl Reg ? */
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volatile __u32 reserved5[0x10 / 4]; /* 0ffset 0xf00-0xf0c */
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volatile __u32 GICD_CPENDSGIRn[0x10 / 4]; /* offset 0xf10-0xf1c, SGI Clear-Pending Reg */
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volatile __u32 GICD_SPENDSGIRn[0x10 / 4]; /* offset 0xf20-0xf2c, SGI Set-Pending Reg */
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volatile __u32 reserved6[0xd0 / 4]; /* 0ffset 0xf30-0xffc */
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};
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struct gic_cpu_interface_disc {
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/* cpu interface reg */
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volatile __u32 GICC_CTLR_PMR_BPR[0xc / 4]; /* offset 0x00-0x08, cpu interface Ctrl Reg + Interrupt Priority Mask Reg + Binary Point Reg */
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volatile __u32 reserved7[0x10 / 4]; /* 0ffset 0xC-0x18, readonly or writeonly */
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volatile __u32 GICC_ABPR; /* offset 0x1c, Aliased Binary Point Reg */
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volatile __u32 reserved8[0xb0 / 4]; /* 0ffset 0x20-0xcf, readonly or writeonly */
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volatile __u32 GICC_APRn[0x10 / 4]; /* offset 0xd0-0xdc, Active Priorities Reg */
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volatile __u32 GICC_NSAPRn[0x10 / 4]; /* offset 0xe0-0xec, Non-secure Active Priorities Reg */
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volatile __u32 reserved9[0x10 / 4]; /* 0ffset 0xf0-0xfc, readonly or writeonly */
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volatile __u32 reserved10[0xf00 / 4]; /* 0ffset 0x100-0xffc, readonly or writeonly */
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volatile __u32 reserved11; /* 0ffset 0x1000, readonly or writeonly */
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};
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struct gic_state {
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struct gic_distributor_state m_distributor;
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struct gic_cpu_interface_state m_interface;
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};
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struct twi_state {
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__mem_twic_reg_t *twi_reg;
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__u32 twi_reg_backup[7];
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};
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struct sram_state {
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__u32 sram_reg_back[SRAM_REG_LENGTH];
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};
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/* save module state */
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__s32 mem_twi_save(struct twi_state *ptwi_state);
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__s32 mem_twi_restore(struct twi_state *ptwi_state);
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__s32 mem_sram_save(struct sram_state *psram_state);
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__s32 mem_sram_restore(struct sram_state *psram_state);
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__s32 mem_ccu_save(struct ccm_state *ccm_reg);
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__s32 mem_ccu_restore(struct ccm_state *ccm_reg);
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extern struct aw_mem_para mem_para_info;
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extern struct super_standby_para super_standby_para_info;
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#if defined(CONFIG_ARCH_SUN8IW8P1)
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#else
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#ifdef CONFIG_SUNXI_ARISC
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#else
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#warning "ARISC driver is not enabled!!!!!!!!!"
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#endif
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#endif
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#endif
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#endif /*_PM_H*/
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