495 lines
14 KiB
C
495 lines
14 KiB
C
/*
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* drivers/thermal/sunxi_ths_driver.h
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*
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* Copyright (C) 2013-2024 allwinner.
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* JiaRui Xiao<xiaojiarui@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef THERMAL_SENSOR_DRIVER_H
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#define THERMAL_SENSOR_DRIVER_H
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#if defined(CONFIG_ARCH_SUN8IW5)
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#define THERMAL_VERSION 1
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#elif defined(CONFIG_ARCH_SUN8IW10) || defined(CONFIG_ARCH_SUN8IW11) || \
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defined(CONFIG_ARCH_SUN50IW1) || defined(CONFIG_ARCH_SUN50IW2)
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#define THERMAL_VERSION 2
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#elif defined(CONFIG_ARCH_SUN50IW3) || defined(CONFIG_ARCH_SUN50IW6)
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#define THERMAL_VERSION 3
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#endif
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enum alarm_irq_temp_type {
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THS_LOW_TEMP_ALARM = 0,
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THS_HIGH_TEMP_ALARM,
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};
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struct ths_irq_enable {
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u32 reg;
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u8 shift;
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};
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struct ths_irq_status {
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u32 reg;
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u8 shift;
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};
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struct ths_threshold {
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u32 reg;
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u8 shift;
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u8 width;
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};
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struct sunxi_thermal_hw_ctrl {
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struct ths_irq_enable irq_enable;
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struct ths_irq_status irq_status;
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struct ths_threshold threshold;
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};
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/*
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struct sunxi_thermal_hw_shut {
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struct ths_irq_enable shut_irq_enable;
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struct ths_irq_status shut_irq_status;
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struct ths_threshold shut_threshold;
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}
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*/
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struct sunxi_thermal_hw_sensor {
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u8 sensor_id;
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struct sunxi_thermal_hw_ctrl *alarm;
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struct sunxi_thermal_hw_ctrl *shut;
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struct sunxi_thermal_hw_ctrl *alarm_off;
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};
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#define SUNXI_THERMAL_HW_CTRL(name, irq_enable_reg, \
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irq_enable_shift, irq_sta_reg, irq_sta_shift, \
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thresh_reg, thresh_shift, thresh_width) \
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static struct sunxi_thermal_hw_ctrl sunxi_ths_hw_##name = { \
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.irq_enable = { \
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.reg = irq_enable_reg, \
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.shift = irq_enable_shift, \
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}, \
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.irq_status = { \
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.reg = irq_sta_reg, \
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.shift = irq_sta_shift, \
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}, \
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.threshold = { \
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.reg = thresh_reg, \
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.shift = thresh_shift, \
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.width = thresh_width, \
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}, \
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}
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#if defined(CONFIG_ARCH_SUN8IW5)
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#define ENABLE_CLK (false)
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/* temperature = -0.118*sensor + 256
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* = (256000 - 118*sensor)/1000
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* = (262144 - 120.832*sensor)/1024
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* = (268435456 - 123732*sensor)/1024/1024
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* = ( MINUPA - reg * MULPA) / 2^DIVPA
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* sensor value range:
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* = 0 - 0xffff,ffff/2/123732
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* = 0 - 17355
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*/
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char *id_name_mapping[] = {
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"cpuc0"
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};
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struct temp_calculate_coefficent thermal_cal_coefficent[] = {
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[0] = {
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.down_limit = {(-227), (0xfff)},
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.up_limit = {(256), (0x000)},
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.nt_para = {
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/* MUL_PARA DIV_PARA MINU_PARA */
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{(1000), (6180), (1662420)},
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}
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}
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};
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struct thermal_reg thermal_reg_init[] = {
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/* name address value reg_type*/
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{"THS_CTRL0_REG", (0x00), (0x002000ff), (NORMAL_REG)},
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{"THS_CTRL1_REG", (0x04), (0x100), (NORMAL_REG)},
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{"THS_INT_CTRL_REG", (0x10), (0x0), (NORMAL_REG)},
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{"THS_INT_STA_REG", (0x14), (0x40000), (INT_STA_REG)},
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{"THS_PRO_CTRL_REG", (0x18), (0x1005f), (ENABLE_REG)},
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{"THS_0_DATA_REG", (0x20), (0x0), (TDATA_REG)},
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{"THS_0_CDATA_REG", (0x40), (0x0), (CDATA_REG)},
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{"", (0), (0), (0)}
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};
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#endif /* CONFIG_ARCH_SUN8IW5 */
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#if defined(CONFIG_ARCH_SUN8IW10)
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#define ENABLE_CLK (true)
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/* temperature = -0.118*sensor + 256
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* = (256000 - 118*sensor)/1000
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* = (262144 - 120.832*sensor)/1024
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* = (268435456 - 123732*sensor)/1024/1024
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* = ( MINUPA - reg * MULPA) / 2^DIVPA
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* sensor value range:
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* = 0 - 0xffff,ffff/2/123732
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* = 0 - 17355
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*/
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char *id_name_mapping[] = {
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"cpuc0",
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"dram"
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};
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struct temp_calculate_coefficent thermal_cal_coefficent[] = {
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[0] = {
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.down_limit = {(-227), (0xfff)},
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.up_limit = {(256), (0x000)},
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.nt_para = {
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/* MUL_PARA DIV_PARA MINU_PARA */
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{(1180), (10000), (2560000)},
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{(1180), (10000), (2560000)}
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}
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}
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};
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struct thermal_reg thermal_reg_init[] = {
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/* name address value reg_type*/
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{"THS_CTRL2_REG", (0x40), (0x01df0000), (ENABLE_REG)},
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{"THS_INT_CTRL_REG", (0x44), (0x3a030), (NORMAL_REG)},
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{"THS_INT_STA_REG", (0x48), (0x333), (INT_STA_REG)},
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{"THS_0_INT_ALM_TH_REG", (0x50), (0x0), (NO_INIT)},
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{"THS_1_INT_ALM_TH_REG", (0x54), (0x0), (NO_INIT)},
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{"THS_0_INT_SHUT_TH_REG", (0x60), (0x0), (SHT_TMP_REG)},
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{"THS_1_INT_SHUT_TH_REG", (0x64), (0x0), (SHT_TMP_REG)},
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{"THS_FILT_CTRL_REG", (0x70), (0x06), (NORMAL_REG)},
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{"THS_0_1_CDATA_REG", (0x74), (0x0), (CDATA_REG)},
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{"THS_0_DATA_REG", (0x80), (0x0), (TDATA_REG)},
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{"THS_1_DATA_REG", (0x84), (0x0), (TDATA_REG)},
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{"", (0), (0), (0)}
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};
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#endif /* CONFIG_ARCH_SUN8IW10 */
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#if defined(CONFIG_ARCH_SUN8IW11)
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#define ENABLE_CLK (true)
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/* temperature = -0.1125*sensor + 250
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* = (2500000 - 1125*sensor)/10000
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* = (xxx - 117964.8*sensor)/1024/1024
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* = ( MINUPA - reg * MULPA) / 2^DIVPA
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* sensor value range:
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* = 0 - 0xffff,ffff/2/117964
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* = 0 - 18204
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*/
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char *id_name_mapping[] = {
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"cpuc0",
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"gpu"
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};
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struct temp_calculate_coefficent thermal_cal_coefficent[] = {
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[0] = {
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.down_limit = {(-210), (0xfff)},
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.up_limit = {(250), (0x000)},
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/*MUL_PARA DIV_PARA MINU_PARA */
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.nt_para = {
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{(1125), (10000), (2500000)},
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{(1125), (10000), (2500000)}
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}
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}
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};
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/** @THS_INT_CTRL_VALUE:per sampling takes: 10ms
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* @THS_CTRL0_VALUE:acq time = 20us
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* @THS_FILT_CTRL_REG :got 1 data for per 8 sampling,
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* time = 10ms * 8 = 80ms
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*/
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struct thermal_reg thermal_reg_init[] = {
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/* name address value reg_type*/
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{"THS_CTRL0_REG", (0x00), (0x1df), (NORMAL_REG)},
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{"THS_CTRL1_REG", (0x04), (0x1<<17), (NORMAL_REG)},
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{"ADC_CDAT_REG", (0x14), (0x0), (NO_INIT)},
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{"THS_CTRL2_REG", (0x40), (0x01df0000), (ENABLE_REG)},
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{"THS_INT_CTRL_REG", (0x44), (0x3a030), (NORMAL_REG)},
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{"THS_INT_STA_REG", (0x48), (0x333), (INT_STA_REG)},
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{"THS_0_INT_ALM_TH_REG", (0x50), (0x0), (NO_INIT)},
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{"THS_1_INT_ALM_TH_REG", (0x54), (0x0), (NO_INIT)},
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{"THS_0_INT_SHUT_TH_REG", (0x60), (0x0), (SHT_TMP_REG)},
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{"THS_1_INT_SHUT_TH_REG", (0x64), (0x0), (SHT_TMP_REG)},
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{"THS_FILT_CTRL_REG", (0x70), (0x06), (NORMAL_REG)},
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{"THS_0_1_CDATA_REG", (0x74), (0x0), (CDATA_REG)},
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{"THS_0_DATA_REG", (0x80), (0x0), (TDATA_REG)},
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{"THS_1_DATA_REG", (0x84), (0x0), (TDATA_REG)},
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{"", (0), (0), (0)}
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};
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#endif /* CONFIG_ARCH_SUN8IW11 */
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#if defined(CONFIG_ARCH_SUN50IW1)
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#define ENABLE_CLK (true)
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/* temperature = ( MINUPA - reg * MULPA) / DIVPA */
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char *id_name_mapping[] = {
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"cpuc0",
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"cpuc1",
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"gpu"
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};
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struct temp_calculate_coefficent thermal_cal_coefficent[] = {
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[0] = {
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.down_limit = {(-210), (0xfff)},
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.up_limit = {(250), (0x000)},
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.nt_para = {
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{(1000), (8560), (2170000)},
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{(1000), (8560), (2170000)},
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{(1000), (8560), (2170000)}
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}
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}
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};
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struct thermal_reg thermal_reg_init[] = {
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/* name address value reg_type*/
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{"THS_CTRL0_REG", (0x00), (0x190), (NORMAL_REG)},
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{"THS_CTRL1_REG", (0x04), (0x1<<17), (NORMAL_REG)},
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{"ADC_CDAT_REG", (0x14), (0x0), (NO_INIT)},
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{"THS_CTRL2_REG", (0x40), (0x01900000), (ENABLE_REG)},
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{"THS_INT_CTRL_REG", (0x44), (0x18070), (NORMAL_REG)},
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{"THS_INT_STA_REG", (0x48), (0x777), (INT_STA_REG)},
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{"THS_0_INT_ALM_TH_REG", (0x50), (0x0), (NO_INIT)},
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{"THS_1_INT_ALM_TH_REG", (0x54), (0x0), (NO_INIT)},
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{"THS_2_INT_ALM_TH_REG", (0x58), (0x0), (NO_INIT)},
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{"THS_0_INT_SHUT_TH_REG", (0x60), (0x0), (SHT_TMP_REG)},
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{"THS_1_INT_SHUT_TH_REG", (0x64), (0x0), (SHT_TMP_REG)},
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{"THS_2_INT_SHUT_TH_REG", (0x68), (0x0), (SHT_TMP_REG)},
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{"THS_FILT_CTRL_REG", (0x70), (0x06), (NORMAL_REG)},
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{"THS_0_1_CDATA_REG", (0x74), (0x0), (CDATA_REG)},
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{"THS_2_CDATA_REG", (0x78), (0x0), (CDATA_REG)},
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{"THS_0_DATA_REG", (0x80), (0x0), (TDATA_REG)},
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{"THS_1_DATA_REG", (0x84), (0x0), (TDATA_REG)},
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{"THS_2_DATA_REG", (0x88), (0x0), (TDATA_REG)},
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{"", (0), (0), (0)}
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};
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#endif /*CONFIG_ARCH_SUN50IW1 */
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#if defined(CONFIG_ARCH_SUN50IW2)
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#define ENABLE_CLK (true)
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/* when temperature <= 70C (sample_data >= 0x500)
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* temperature = -0.1191*sensor + 223
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* = (2230000 - 1191*sensor)/10000
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* = (233832448 - 124885.4016*sensor)/1024/1024
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* = (233832448 - 124885*sensor)/1024/1024
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* = ( MINUPA - reg * MULPA) / 2^DIVPA
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* sensor value range:
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* = 0 - 0xffff,ffff/2/124885
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* = 0 - 17195
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*/
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char *id_name_mapping[] = {
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"cpuc0",
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"gpu"
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};
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struct temp_calculate_coefficent thermal_cal_coefficent[] = {
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[0] = {
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.down_limit = {(-268), (0xfff)},
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.up_limit = {(70), (0x500)},
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.nt_para = {
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{(1191), (10000), (2230000)},
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{(1191), (10000), (2230000)}
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}
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},
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[1] = {
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.down_limit = {(70), (0x500)},
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.up_limit = {(223), (0x000)},
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.nt_para = {
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{(1452), (10000), (2590000)},
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{(1590), (10000), (2760000)}
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}
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}
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};
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/* when temperature > 70C (sample_data < 0x500)
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* cpu_temperature = -0.1452*sensor + 259
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* = (2590000 - 1452*sensor)/10000
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* = (271581184 - 152253.2352*sensor)/1024/1024
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* = (271581184 - 152253*sensor)/1024/1024
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* = ( MINUPA - reg * MULPA) / 2^DIVPA
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* sensor value range:
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* = 0 - 0xffff,ffff/2/152253
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* = 0 - 14104
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*
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* gpu_temperature = -0.159*sensor + 276
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* = (2760000 - 1590*sensor)/10000
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* = (289406976 - 166723.5840*sensor)/1024/1024
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* = (289406976 - 166724*sensor)/1024/1024
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* = ( MINUPA - reg * MULPA) / 2^DIVPA
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* sensor value range:
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* = 0 - 0xffff,ffff/2/166724
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* = 0 - 2047
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*/
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struct thermal_reg thermal_reg_init[] = {
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/* name address value reg_type*/
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{"THS_CTRL0_REG", (0x00), (0x1df), (NORMAL_REG)},
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{"THS_CTRL1_REG", (0x04), (0x1<<17), (NORMAL_REG)},
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{"ADC_CDAT_REG", (0x14), (0x0), (NO_INIT)},
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{"THS_CTRL2_REG", (0x40), (0x01df0000), (ENABLE_REG)},
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{"THS_INT_CTRL_REG", (0x44), (0x3a030), (NORMAL_REG)},
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{"THS_INT_STA_REG", (0x48), (0x333), (INT_STA_REG)},
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{"THS_0_INT_ALM_TH_REG", (0x50), (0x0), (NO_INIT)},
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{"THS_1_INT_ALM_TH_REG", (0x54), (0x0), (NO_INIT)},
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{"THS_0_INT_SHUT_TH_REG", (0x60), (0x0), (SHT_TMP_REG)},
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{"THS_1_INT_SHUT_TH_REG", (0x64), (0x0), (SHT_TMP_REG)},
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{"THS_FILT_CTRL_REG", (0x70), (0x06), (NORMAL_REG)},
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{"THS_0_1_CDATA_REG", (0x74), (0x0), (CDATA_REG)},
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{"THS_0_DATA_REG", (0x80), (0x0), (TDATA_REG)},
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{"THS_1_DATA_REG", (0x84), (0x0), (TDATA_REG)},
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{"", (0), (0), (0)}
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};
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#endif /* CONFIG_ARCH_SUN50IW2 */
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#if defined(CONFIG_ARCH_SUN50IW3)
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#define ENABLE_CLK (true)
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struct temp_calculate_coefficent thermal_cal_coefficent[] = {
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[0] = {
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.down_limit = {(-210), (0xfff)},
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.up_limit = {(250), (0x000)},
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/*MUL_PARA DIV_PARA MINU_PARA */
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.nt_para = {
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{(1125), (10000), (2360000)},
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{(1125), (10000), (2360000)}
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}
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}
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};
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/**
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* SUN50IW3 Thermal Sensor Register
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*/
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char *id_name_mapping[] = {
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"cpuc0",
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"gpu",
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};
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struct thermal_reg thermal_reg_init[] = {
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/* name address value reg_type*/
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{"THS_CTRL_REG", (0x00), (0x01df002f), (NORMAL_REG)},
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{"THS_EN_REG", (0x04), (0x3), (ENABLE_REG)},
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{"THS_PER_REG", (0x08), (0x3a), (NORMAL_REG)},
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{"THS_DATA_INTC_REG", (0x10), (0x0), (NO_INIT)},
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{"THS_SHUT_INTC_REG", (0x14), (0x3), (NORMAL_REG)},
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{"THS_ALARM_INTC_REG", (0x18), (0x0), (NO_INIT)},
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{"THS_DATA_INTS_REG", (0x20), (0x3), (INT_STA_REG)},
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{"THS_SHUT_INTS_REG", (0x24), (0x3), (INT_STA_REG)},
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{"THS_ALARMO_INTS_REG", (0x28), (0x3), (INT_STA_REG)},
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{"THS_ALARM_INTS_REG", (0x2C), (0x3), (INT_STA_REG)},
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{"THS_FILT_CTRL_REG", (0x30), (0x06), (NORMAL_REG)},
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{"THS_0_ALARM_CTRL_REG", (0x40), (0x0), (NO_INIT)},
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{"THS_1_ALARM_CTRL_REG", (0x44), (0x0), (NO_INIT)},
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{"THS_0_1_SHUT_CTRL_REG", (0x80), (0x0), (SHT_TMP_REG)},
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{"THS_0_1_CDATA_REG", (0xA0), (0x0), (CDATA_REG)},
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{"THS_0_DATA_REG", (0xC0), (0x0), (TDATA_REG)},
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{"THS_1_DATA_REG", (0xC4), (0x0), (TDATA_REG)},
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{"", (0), (0), (0)}
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};
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#endif /* defined(CONFIG_ARCH_SUN50IW3P1)*/
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#if defined(CONFIG_ARCH_SUN50IW6)
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#define SUNXI_THERMAL_SUPPORT_IRQ
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#define ENABLE_CLK (true)
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struct temp_calculate_coefficent thermal_cal_coefficent[] = {
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[0] = {
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.down_limit = {(-210), (0xfff)},
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.up_limit = {(250), (0x000)},
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|
/*MUL_PARA DIV_PARA MINU_PARA */
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.nt_para = {
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{(1000), (14882), (2794000)},
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|
{(1000), (14882), (2794000)}
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|
}
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|
}
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|
};
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|
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|
#define THS_SHUT_INT_CTL 0x14
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#define THS_SHUT_INT_STATUS 0x24
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#define THS_ALARM_INT_CTL 0x18
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#define THS_ALARMOFF_INT_STATUS 0x28
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#define THS_ALARM_INT_STATUS 0x2C
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#define THS0_ALARM_THRESHOLD_CTL 0x40
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#define THS1_ALARM_THRESHOLD_CTL 0X44
|
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#define THS_SHUT_THRESHOLD_CTL 0x80
|
|
|
|
SUNXI_THERMAL_HW_CTRL(alarm0, THS_ALARM_INT_CTL, 0, THS_ALARM_INT_STATUS, 0,
|
|
THS0_ALARM_THRESHOLD_CTL, 16, 12);
|
|
SUNXI_THERMAL_HW_CTRL(alarm1, THS_ALARM_INT_CTL, 1, THS_ALARM_INT_STATUS, 1,
|
|
THS1_ALARM_THRESHOLD_CTL, 16, 12);
|
|
SUNXI_THERMAL_HW_CTRL(alarmoff0, THS_ALARM_INT_CTL, 0, THS_ALARMOFF_INT_STATUS,
|
|
0, THS0_ALARM_THRESHOLD_CTL, 0, 12);
|
|
SUNXI_THERMAL_HW_CTRL(alarmoff1, THS_ALARM_INT_CTL, 1, THS_ALARMOFF_INT_STATUS,
|
|
1, THS1_ALARM_THRESHOLD_CTL, 0, 12);
|
|
SUNXI_THERMAL_HW_CTRL(shut0, THS_SHUT_INT_CTL, 0, THS_SHUT_INT_STATUS, 0,
|
|
THS_SHUT_THRESHOLD_CTL, 0, 12);
|
|
SUNXI_THERMAL_HW_CTRL(shut1, THS_SHUT_INT_CTL, 1, THS_SHUT_INT_STATUS, 1,
|
|
THS_SHUT_THRESHOLD_CTL, 16, 12);
|
|
|
|
struct sunxi_thermal_hw_sensor ths_hw_sensor[] = {
|
|
{0, &sunxi_ths_hw_alarm0, &sunxi_ths_hw_shut0, &sunxi_ths_hw_alarmoff0},
|
|
{1, &sunxi_ths_hw_alarm1, &sunxi_ths_hw_shut1, &sunxi_ths_hw_alarmoff1},
|
|
};
|
|
/**
|
|
* SUN50IW3 Thermal Sensor Register
|
|
*/
|
|
char *id_name_mapping[] = {
|
|
"cpuc0",
|
|
"gpu",
|
|
};
|
|
|
|
struct thermal_reg thermal_reg_init[] = {
|
|
/* name address value reg_type*/
|
|
{"THS_CTRL_REG", (0x00), (0x01df002f), (NORMAL_REG)},
|
|
{"THS_EN_REG", (0x04), (0x3), (ENABLE_REG)},
|
|
{"THS_PER_REG", (0x08), (0x3a000), (NORMAL_REG)},
|
|
{"THS_DATA_INTC_REG", (0x10), (0x0), (NO_INIT)},
|
|
{"THS_SHUT_INTC_REG", (0x14), (0x3), (NORMAL_REG)},
|
|
{"THS_ALARM_INTC_REG", (0x18), (0x0), (NO_INIT)},
|
|
{"THS_DATA_INTS_REG", (0x20), (0x3), (INT_STA_REG)},
|
|
{"THS_SHUT_INTS_REG", (0x24), (0x3), (INT_STA_REG)},
|
|
{"THS_ALARMO_INTS_REG", (0x28), (0x3), (INT_STA_REG)},
|
|
{"THS_ALARM_INTS_REG", (0x2C), (0x3), (INT_STA_REG)},
|
|
{"THS_FILT_CTRL_REG", (0x30), (0x06), (NORMAL_REG)},
|
|
{"THS_0_ALARM_CTRL_REG", (0x40), (0x0), (NO_INIT)},
|
|
{"THS_1_ALARM_CTRL_REG", (0x44), (0x0), (NO_INIT)},
|
|
{"THS_0_1_SHUT_CTRL_REG", (0x80), (0x0), (SHT_TMP_REG)},
|
|
{"THS_0_1_CDATA_REG", (0xA0), (0x0), (CDATA_REG)},
|
|
{"THS_0_DATA_REG", (0xC0), (0x0), (TDATA_REG)},
|
|
{"THS_1_DATA_REG", (0xC4), (0x0), (TDATA_REG)},
|
|
{"", (0), (0), (0)}
|
|
};
|
|
|
|
#endif /* defined(CONFIG_ARCH_SUN50IW6P1)*/
|
|
|
|
#endif /* THERMAL_SENSOR_DRIVER_H */
|