595 lines
12 KiB
C
595 lines
12 KiB
C
/*
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* sound\soc\sunxi\audiocodec\sunxi-codec.c
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* (C) Copyright 2010-2016
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* Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
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* huangxin <huangxin@Reuuimllatech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/dma.h>
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#include "sunxi_codecdma.h"
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#ifdef CONFIG_ARCH_SUN8IW5
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#include "sun8iw5_sndcodec.h"
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#endif
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#ifdef CONFIG_ARCH_SUN8IW9
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#include "sun8iw9_sndcodec.h"
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#endif
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#define SUNXI_PCM_RATES (SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT)
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#if defined CONFIG_ARCH_SUN8IW5 || defined CONFIG_ARCH_SUN8IW9
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static u32 sample_resolution = 16;
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static struct sunxi_dma_params sunxi_pcm_pcm_stereo_out = {
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.name = "audio_play",
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.dma_addr = CODEC_BASSADDRESS + SUNXI_DA_TXFIFO,/*send data address*/
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};
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static struct sunxi_dma_params sunxi_pcm_pcm_stereo_in = {
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.name = "audio_capture",
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.dma_addr = CODEC_BASSADDRESS + SUNXI_DA_RXFIFO,/*accept data address*/
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};
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static void sunxi_snd_txctrl(struct snd_pcm_substream *substream, int on)
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{
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/*clear TX counter*/
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codec_wr_control(SUNXI_DA_TXCNT, 0xffffffff, TX_CNT, 0);
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/*flush TX FIFO*/
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codec_wr_control(SUNXI_DA_FCTL, 0x1, FTX, 1);
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if (on) {
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/* enable DMA DRQ mode for play */
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codec_wr_control(SUNXI_DA_INT, 0x1, TX_DRQ, 1);
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} else {
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/* DISBALE dma DRQ mode */
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codec_wr_control(SUNXI_DA_INT, 0x1, TX_DRQ, 0);
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}
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}
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static void sunxi_snd_rxctrl(struct snd_pcm_substream *substream, int on)
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{
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/*clear RX counter*/
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codec_wr_control(SUNXI_DA_RXCNT, 0xffffffff, RX_CNT, 0);
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/*flush RX FIFO*/
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codec_wr_control(SUNXI_DA_FCTL, 0x1, FRX, 1);
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if (on) {
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/* enable DMA DRQ mode for record */
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codec_wr_control(SUNXI_DA_INT, 0x1, RX_DRQ, 1);
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} else {
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/* DISBALE dma DRQ mode */
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codec_wr_control(SUNXI_DA_INT, 0x1, RX_DRQ, 0);
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}
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}
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static int sunxi_i2s_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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/*enable i2s tx*/
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sunxi_snd_txctrl(substream, 1);
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return 0;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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sunxi_snd_txctrl(substream, 0);
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return 0;
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default:
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return -EINVAL;
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}
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} else {
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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sunxi_snd_rxctrl(substream, 1);
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return 0;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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sunxi_snd_rxctrl(substream, 0);
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return 0;
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default:
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pr_err("error:%s,%d\n", __func__, __LINE__);
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return -EINVAL;
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}
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}
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return 0;
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}
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static int sunxi_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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int rs_value = 0;
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct sunxi_dma_params *dma_data;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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sample_resolution = 16;
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break;
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case SNDRV_PCM_FORMAT_S20_3LE:
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sample_resolution = 24;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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sample_resolution = 24;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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sample_resolution = 24;
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break;
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default:
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return -EINVAL;
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}
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/* sample rate */
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switch (sample_resolution) {
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case 16:
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rs_value = 0;
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break;
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case 20:
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rs_value = 1;
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break;
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case 24:
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rs_value = 2;
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break;
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default:
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return -EINVAL;
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/*
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case 32: rs_value = 3;
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break;
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*/
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}
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codec_wr_control(SUNXI_DA_FAT0, 0x3, SR, rs_value);
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#ifdef CONFIG_ARCH_SUN8IW5
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/*calculate word select bit*/
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switch (sample_resolution) {
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case 16:
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rs_value = 0x1;
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break;
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case 8:
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rs_value = 0x0;
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break;
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case 20:
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rs_value = 0x2;
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break;
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case 24:
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rs_value = 0x3;
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break;
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default:
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break;
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}
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codec_wr_control(SUNXI_AIF1CLK_CTRL, 0x3, AIF1_WORD_SIZ, rs_value);
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#endif
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if (sample_resolution == 24)
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codec_wr_control(SUNXI_DA_FCTL, 0xf, RXOM, 0x1);
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else
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codec_wr_control(SUNXI_DA_FCTL, 0xf, RXOM, 0x5);
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/* play or record */
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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dma_data = &sunxi_pcm_pcm_stereo_out;
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else
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dma_data = &sunxi_pcm_pcm_stereo_in;
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snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_data);
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return 0;
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}
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static int sunxi_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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/*config i2s clk*/
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#ifdef CONFIG_ARCH_SUN8IW5
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sunxi_i2s_set_rate(freq);
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/*config aif1 clk from pll*/
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codec_wr_control(SUNXI_SYSCLK_CTL, 0x3, AIF1CLK_SRC, 0x3);
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/*config sys clk from aif1clk*/
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codec_wr_control(SUNXI_SYSCLK_CTL, 0x1, SYSCLK_SRC, 0x0);
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#endif
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return 0;
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}
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static int sunxi_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
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int div_id, int samplerate)
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{
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u32 mclk_div = 0;
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u32 bclk_div = 0;
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int wss_value = 0;
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u32 over_sample_rate = 0;
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u32 word_select_size = 32;
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#ifdef CONFIG_ARCH_SUN8IW5
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u32 bclk_lrck_div = 64;
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#endif
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/*mclk div calculate*/
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switch (samplerate) {
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case 8000:
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{
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over_sample_rate = 128;
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mclk_div = 24;
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break;
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}
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case 16000:
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{
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over_sample_rate = 128;
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mclk_div = 12;
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break;
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}
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case 32000:
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{
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over_sample_rate = 128;
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mclk_div = 6;
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break;
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}
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case 64000:
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{
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over_sample_rate = 384;
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mclk_div = 1;
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break;
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}
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case 11025:
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case 12000:
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{
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over_sample_rate = 128;
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mclk_div = 16;
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break;
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}
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case 22050:
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case 24000:
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{
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over_sample_rate = 128;
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mclk_div = 8;
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break;
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}
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case 44100:
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case 48000:
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{
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over_sample_rate = 128;
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mclk_div = 4;
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break;
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}
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case 88200:
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case 96000:
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{
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over_sample_rate = 128;
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mclk_div = 2;
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break;
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}
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case 176400:
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case 192000:
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{
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over_sample_rate = 128;
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mclk_div = 1;
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break;
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}
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}
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/*bclk div caculate*/
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bclk_div = over_sample_rate/(2*word_select_size);
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/*calculate MCLK Divide Ratio*/
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switch (mclk_div) {
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case 1:
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mclk_div = 0;
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break;
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case 2:
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mclk_div = 1;
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break;
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case 4:
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mclk_div = 2;
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break;
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case 6:
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mclk_div = 3;
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break;
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case 8:
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mclk_div = 4;
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break;
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case 12:
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mclk_div = 5;
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break;
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case 16:
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mclk_div = 6;
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break;
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case 24:
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mclk_div = 7;
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break;
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case 32:
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mclk_div = 8;
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break;
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case 48:
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mclk_div = 9;
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break;
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case 64:
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mclk_div = 0xA;
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break;
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}
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mclk_div &= 0xf;
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/*calculate BCLK Divide Ratio*/
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switch (bclk_div) {
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case 2:
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bclk_div = 0;
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break;
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case 4:
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bclk_div = 1;
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break;
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case 6:
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bclk_div = 2;
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break;
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case 8:
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bclk_div = 3;
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break;
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case 12:
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bclk_div = 4;
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break;
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case 16:
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bclk_div = 5;
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break;
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case 32:
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bclk_div = 6;
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break;
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case 64:
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bclk_div = 7;
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break;
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}
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bclk_div &= 0x7;
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/*confige mclk and bclk dividor register*/
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codec_wr_control(SUNXI_DA_CLKD, 0x7, BCLKDIV, bclk_div);
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codec_wr_control(SUNXI_DA_CLKD, 0xf, MCLKDIV, mclk_div);
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codec_wr_control(SUNXI_DA_CLKD, 0x1, 7, 1);
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/* word select size */
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switch (word_select_size) {
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case 16:
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wss_value = 0;
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break;
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case 20:
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wss_value = 1;
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break;
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case 24:
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wss_value = 2;
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break;
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case 32:
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wss_value = 3;
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break;
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}
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codec_wr_control(SUNXI_DA_FAT0, 0x3, WSS, wss_value);
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#ifdef CONFIG_ARCH_SUN8IW5
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/*********aif1 part************ */
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/*calculate bclk_lrck_div Ratio*/
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switch (bclk_lrck_div) {
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case 16:
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bclk_lrck_div = 0;
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break;
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case 32:
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bclk_lrck_div = 1;
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break;
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case 64:
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bclk_lrck_div = 2;
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break;
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case 128:
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bclk_lrck_div = 3;
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break;
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case 256:
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bclk_lrck_div = 4;
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break;
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default:
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break;
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}
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codec_wr_control(SUNXI_AIF1CLK_CTRL,
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0x7, AIF1_LRCK_DIV, bclk_lrck_div);
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#endif
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return 0;
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}
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static int sunxi_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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/*i2s part*/
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/*SDO ON*/
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/*codec_wr_control(SUNXI_DA_CTL, 0x1, SDO_EN, 1);*/
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/*master mode*/
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codec_wr_control(SUNXI_DA_CTL, 0x1, MS, 0);
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/*i2s mode*/
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codec_wr_control(SUNXI_DA_CTL, 0x1, PCM, 0);
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/* DAI signal inversions */
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codec_wr_control(SUNXI_DA_FAT0, 0x1, LRCP, 0);
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codec_wr_control(SUNXI_DA_FAT0, 0x1, BCP, 0);
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/*data format*/
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codec_wr_control(SUNXI_DA_FAT0, 0x3, FMT, 0);/*standard i2s fmt*/
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/*RX FIFO trigger level*/
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codec_wr_control(SUNXI_DA_FCTL, 0x7f, TXTL, 0x40);
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/*TX FIFO empty trigger level*/
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codec_wr_control(SUNXI_DA_FCTL, 0x1f, RXTL, 0x1f);
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/*codec_wr_control(SUNXI_DA_FCTL, 0xf, RXOM, 0x5);*/
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#ifdef CONFIG_ARCH_SUN8IW5
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/**aif1 part**/
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/*aif1 slave*/
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codec_wr_control(SUNXI_AIF1CLK_CTRL, 0x1, AIF1_MSTR_MOD, 1);
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/*aif1 i2s mode*/
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codec_wr_control(SUNXI_AIF1CLK_CTRL, 0x3, AIF1_DATA_FMT, 0);
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/* DAI signal inversions */
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codec_wr_control(SUNXI_AIF1CLK_CTRL, 0x1, AIF1_BCLK_INV, 0);
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codec_wr_control(SUNXI_AIF1CLK_CTRL, 0x1, AIF1_LRCK_INV, 0);
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#endif
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return 0;
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}
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static int sunxi_i2s_preapre(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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u32 reg_val = 0;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_val = SUNXI_TXCHSEL_CHNUM(substream->runtime->channels);
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/*confige i2s ap tx channel */
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codec_wr_control(SUNXI_DA_TXCHSEL, 0x7, TX_CHSEL, reg_val);
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if (substream->runtime->channels == 1)
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reg_val = 0x00;
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else
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reg_val = 0x10;
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/*confige i2s ap tx channel mapping*/
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codec_wr_control(SUNXI_DA_TXCHMAP, 0x7, TX_CH0_MAP, reg_val);
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/*SDO ON*/
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codec_wr_control(SUNXI_DA_CTL, 0x1, SDO_EN, 1);
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/* I2S0 TX ENABLE */
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codec_wr_control(SUNXI_DA_CTL, 0x1, TXEN, 1);
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} else {
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reg_val = SUNXI_RXCHSEL_CHNUM(substream->runtime->channels);
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/*confige i2s ap rx channel */
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codec_wr_control(SUNXI_DA_RXCHSEL, 0x7, RX_CHSEL, reg_val);
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if (substream->runtime->channels == 1)
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reg_val = 0x00;
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else
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reg_val = 0x10;
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/*confige i2s ap rx channel mapping*/
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codec_wr_control(SUNXI_DA_RXCHMAP, 0x7, RX_CH0_MAP, reg_val);
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/* I2S0 RX ENABLE */
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codec_wr_control(SUNXI_DA_CTL, 0x1, RXEN, 1);
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}
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return 0;
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}
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static struct snd_soc_dai_ops sunxi_i2s_dai_ops = {
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.trigger = sunxi_i2s_trigger,
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.hw_params = sunxi_i2s_hw_params,
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.set_fmt = sunxi_i2s_set_fmt,
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.set_clkdiv = sunxi_i2s_set_clkdiv,
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.set_sysclk = sunxi_i2s_set_sysclk,
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.prepare = sunxi_i2s_preapre,
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};
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#endif
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static struct snd_soc_dai_driver sunxi_pcm_dai = {
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.playback = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = SUNXI_PCM_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S20_3LE |
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.capture = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = SUNXI_PCM_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S20_3LE |
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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|
},
|
|
|
|
#if defined CONFIG_ARCH_SUN8IW5 || defined CONFIG_ARCH_SUN8IW9
|
|
.ops = &sunxi_i2s_dai_ops,
|
|
#endif
|
|
};
|
|
|
|
static const struct snd_soc_component_driver sunxi_pcm_dai_component = {
|
|
.name = "sunxi-pcm-dai",
|
|
};
|
|
|
|
static int __init sunxi_pcm_dev_probe(struct platform_device *pdev)
|
|
{
|
|
int err = -1;
|
|
|
|
err = snd_soc_register_component(&pdev->dev,
|
|
&sunxi_pcm_dai_component, &sunxi_pcm_dai, 1);
|
|
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to register DAI\n");
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __exit sunxi_pcm_dev_remove(struct platform_device *pdev)
|
|
{
|
|
snd_soc_unregister_component(&pdev->dev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*data relating*/
|
|
static struct platform_device sunxi_pcm_device = {
|
|
.name = "sunxi-codec",
|
|
.id = -1,
|
|
};
|
|
|
|
/*method relating*/
|
|
static struct platform_driver sunxi_pcm_driver = {
|
|
.probe = sunxi_pcm_dev_probe,
|
|
.remove = __exit_p(sunxi_pcm_dev_remove),
|
|
.driver = {
|
|
.name = "sunxi-codec",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init sunxi_pcm_init(void)
|
|
{
|
|
int err = 0;
|
|
|
|
err = platform_device_register(&sunxi_pcm_device);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = platform_driver_register(&sunxi_pcm_driver);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
module_init(sunxi_pcm_init);
|
|
|
|
static void __exit sunxi_pcm_exit(void)
|
|
{
|
|
platform_driver_unregister(&sunxi_pcm_driver);
|
|
}
|
|
module_exit(sunxi_pcm_exit);
|
|
|
|
/* Module information */
|
|
MODULE_AUTHOR("REUUIMLLA");
|
|
MODULE_DESCRIPTION("sunxi PCM SoC Interface");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:sunxi-pcm");
|
|
|