229 lines
11 KiB
C
229 lines
11 KiB
C
/*
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* arch/arm/mach-sunxi/include/mach/sun8i/platform-sun8iw5p1.h
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*
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* Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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* http://www.allwinnertech.com
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*
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* Author: liugang <liugang@allwinnertech.com>
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*
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* sun8i platform header file
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __PLATFORM_SUN8I_W5P1_H
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#define __PLATFORM_SUN8I_W5P1_H
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/*
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* memory definitions
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*/
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#if !defined(SUNXI_IO_PBASE)
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#define SUNXI_IO_PBASE 0x01c00000
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#define SUNXI_IO_SIZE 0x00400000
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#define SUNXI_SRAM_A1_PBASE 0x00000000
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#define SUNXI_SRAM_A1_SIZE 0x00008000
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#define SUNXI_SRAM_A2_PBASE 0x00040000
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#define SUNXI_SRAM_A2_SIZE 0x00014000
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#define SUNXI_SDRAM_PBASE 0x40000000
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#define SUNXI_BROM_PBASE 0xffff0000
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#define SUNXI_BROM_SIZE 0x00008000
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#endif
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/*
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* device physical addresses
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*/
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#define SUNXI_SRAMCTRL_PBASE 0x01c00000
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#define SUNXI_DMA_PBASE 0x01c02000
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#define SUNXI_NANDFLASHC0_PBASE 0x01c03000
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#define SUNXI_LCD0_PBASE 0x01c0c000
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#define SUNXI_VE_PBASE 0x01c0e000
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#define SUNXI_SDMMC0_PBASE 0x01c0f000
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#define SUNXI_SDMMC1_PBASE 0x01c10000
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#define SUNXI_SDMMC2_PBASE 0x01c11000
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#define SUNXI_SS_PBASE 0x01c15000
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#define SUNXI_MSGBOX_PBASE 0x01c17000
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#define SUNXI_SPINLOCK_PBASE 0x01c18000
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#define SUNXI_USB_OTG_PBASE 0x01c19000
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#define SUNXI_USB_HCI0_PBASE 0x01c1a000
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#define SUNXI_CCM_PBASE 0x01c20000
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#define SUNXI_PIO_PBASE 0x01c20800
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#define SUNXI_TIMER_PBASE 0x01c20c00
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#define SUNXI_PWM_PBASE 0x01c21400
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#define SUNXI_DAUDIO0_PBASE 0x01c22000
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#define SUNXI_DAUDIO1_PBASE 0x01c22400
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#define SUNXI_LRADC_PBASE 0x01c22800
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#define SUNXI_AUDIO_PBASE 0x01c22C00
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#define SUNXI_SID_PBASE 0x01c23800
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#define SUNXI_THERMAL_PBASE 0x01c25000
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#define SUNXI_UART0_PBASE 0x01c28000
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#define SUNXI_UART1_PBASE 0x01c28400
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#define SUNXI_UART2_PBASE 0x01c28800
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#define SUNXI_UART3_PBASE 0x01c28c00
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#define SUNXI_UART4_PBASE 0x01c29000
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#define SUNXI_TWI0_PBASE 0x01c2ac00
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#define SUNXI_TWI1_PBASE 0x01c2b000
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#define SUNXI_TWI2_PBASE 0x01c2b400
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#define SUNXI_GPU_PBASE 0x01c40000
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#define SUNXI_HSTMR_PBASE 0x01c60000
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#define SUNXI_DRAMCOM_PBASE 0x01c62000
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#define SUNXI_DRAMCTL0_PBASE 0x01c63000
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#define SUNXI_DRAMPHY0_PBASE 0x01c65000
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#define SUNXI_SPI0_PBASE 0x01c68000
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#define SUNXI_SPI1_PBASE 0x01c69000
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#define SUNXI_SCU_PBASE 0x01c80000
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#define SUNXI_GIC_DIST_PBASE 0x01c81000
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#define SUNXI_GIC_CPU_PBASE 0x01c82000
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#define SUNXI_MIPI_DSI0_PBASE 0x01ca0000
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#define SUNXI_MIPI_DSI0_PHY_PBASE 0x01ca1000
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#define SUNXI_CSI_PBASE 0x01cb0000
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#define SUNXI_DE_FE0_PBASE 0x01e00000
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#define SUNXI_DE_BE0_PBASE 0x01e60000
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#define SUNXI_DRC0_PBASE 0x01e70000
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#define SUNXI_SAT_PBASE 0x01e80000
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#define SUNXI_RTC_PBASE 0x01f00000
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#define SUNXI_R_TIMER_PBASE 0x01f00800
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#define SUNXI_R_INTC_PBASE 0x01f00c00
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#define SUNXI_R_WDOG_PBASE 0x01f01000
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#define SUNXI_R_PRCM_PBASE 0x01f01400
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#define SUNXI_R_CPUCFG_PBASE 0x01f01c00
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#define SUNXI_R_TWI_PBASE 0x01f02400
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#define SUNXI_R_UART_PBASE 0x01f02800
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#define SUNXI_R_PIO_PBASE 0x01f02c00
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#define SUNXI_R_RSB_PBASE 0x01f03400
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#define SUNXI_R_PWM_PBASE 0x01f03800
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#define SUNXI_CORESIGHT_DEBUG_PBASE 0x3f500000
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#define SUNXI_TSGEN_RO_PBASE 0x3f506000
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#define SUNXI_TSGEN_CTRL_PBASE 0x3f507000
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/*
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* define virt addresses
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*/
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#define SUNXI_IO_VBASE IO_ADDRESS(SUNXI_IO_PBASE)
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#define SUNXI_SRAM_A1_VBASE IO_ADDRESS(SUNXI_SRAM_A1_PBASE)
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#define SUNXI_SRAM_A2_VBASE IO_ADDRESS(SUNXI_SRAM_A2_PBASE)
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#define SUNXI_BROM_VBASE 0xf1000000 /* note: IO_ADDRESS(SUNXI_BROM_PBASE) out of vmalloc range */
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#define SUNXI_SRAMCTRL_VBASE IO_ADDRESS(SUNXI_SRAMCTRL_PBASE)
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#define SUNXI_DMA_VBASE IO_ADDRESS(SUNXI_DMA_PBASE)
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#define SUNXI_NANDFLASHC0_VBASE IO_ADDRESS(SUNXI_NANDFLASHC0_PBASE)
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#define SUNXI_LCD0_VBASE IO_ADDRESS(SUNXI_LCD0_PBASE)
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#define SUNXI_VE_VBASE IO_ADDRESS(SUNXI_VE_PBASE)
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#define SUNXI_SDMMC0_VBASE IO_ADDRESS(SUNXI_SDMMC0_PBASE)
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#define SUNXI_SDMMC1_VBASE IO_ADDRESS(SUNXI_SDMMC1_PBASE)
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#define SUNXI_SDMMC2_VBASE IO_ADDRESS(SUNXI_SDMMC2_PBASE)
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#define SUNXI_SS_VBASE IO_ADDRESS(SUNXI_SS_PBASE)
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#define SUNXI_MSGBOX_VBASE IO_ADDRESS(SUNXI_MSGBOX_PBASE)
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#define SUNXI_SPINLOCK_VBASE IO_ADDRESS(SUNXI_SPINLOCK_PBASE)
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#define SUNXI_USB_OTG_VBASE IO_ADDRESS(SUNXI_USB_OTG_PBASE)
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#define SUNXI_USB_HCI0_VBASE IO_ADDRESS(SUNXI_USB_HCI0_PBASE)
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#define SUNXI_CCM_VBASE IO_ADDRESS(SUNXI_CCM_PBASE)
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#define SUNXI_PIO_VBASE IO_ADDRESS(SUNXI_PIO_PBASE)
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#define SUNXI_TIMER_VBASE IO_ADDRESS(SUNXI_TIMER_PBASE)
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#define SUNXI_PWM_VBASE IO_ADDRESS(SUNXI_PWM_PBASE)
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#define SUNXI_DAUDIO0_VBASE IO_ADDRESS(SUNXI_DAUDIO0_PBASE)
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#define SUNXI_DAUDIO1_VBASE IO_ADDRESS(SUNXI_DAUDIO1_PBASE)
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#define SUNXI_LRADC_VBASE IO_ADDRESS(SUNXI_LRADC_PBASE)
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#define SUNXI_AUDIO_VBASE IO_ADDRESS(SUNXI_AUDIO_PBASE)
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#define SUNXI_SID_VBASE IO_ADDRESS(SUNXI_SID_PBASE)
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#define SUNXI_THERMAL_VBASE IO_ADDRESS(SUNXI_THERMAL_PBASE)
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#define SUNXI_UART0_VBASE IO_ADDRESS(SUNXI_UART0_PBASE)
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#define SUNXI_UART1_VBASE IO_ADDRESS(SUNXI_UART1_PBASE)
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#define SUNXI_UART2_VBASE IO_ADDRESS(SUNXI_UART2_PBASE)
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#define SUNXI_UART3_VBASE IO_ADDRESS(SUNXI_UART3_PBASE)
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#define SUNXI_UART4_VBASE IO_ADDRESS(SUNXI_UART4_PBASE)
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#define SUNXI_TWI0_VBASE IO_ADDRESS(SUNXI_TWI0_PBASE)
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#define SUNXI_TWI1_VBASE IO_ADDRESS(SUNXI_TWI1_PBASE)
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#define SUNXI_TWI2_VBASE IO_ADDRESS(SUNXI_TWI2_PBASE)
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#define SUNXI_GPU_VBASE IO_ADDRESS(SUNXI_GPU_PBASE)
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#define SUNXI_HSTMR_VBASE IO_ADDRESS(SUNXI_HSTMR_PBASE)
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#define SUNXI_DRAMCOM_VBASE IO_ADDRESS(SUNXI_DRAMCOM_PBASE)
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#define SUNXI_DRAMCTL0_VBASE IO_ADDRESS(SUNXI_DRAMCTL0_PBASE)
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#define SUNXI_DRAMPHY0_VBASE IO_ADDRESS(SUNXI_DRAMPHY0_PBASE)
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#define SUNXI_SPI0_VBASE IO_ADDRESS(SUNXI_SPI0_PBASE)
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#define SUNXI_SPI1_VBASE IO_ADDRESS(SUNXI_SPI1_PBASE)
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#define SUNXI_SCU_VBASE IO_ADDRESS(SUNXI_SCU_PBASE)
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#define SUNXI_GIC_DIST_VBASE IO_ADDRESS(SUNXI_GIC_DIST_PBASE)
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#define SUNXI_GIC_CPU_VBASE IO_ADDRESS(SUNXI_GIC_CPU_PBASE)
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#define SUNXI_MIPI_DSI0_VBASE IO_ADDRESS(SUNXI_MIPI_DSI0_PBASE)
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#define SUNXI_MIPI_DSI0_PHY_VBASE IO_ADDRESS(SUNXI_MIPI_DSI0_PHY_PBASE)
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#define SUNXI_CSI_VBASE IO_ADDRESS(SUNXI_CSI_PBASE)
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#define SUNXI_DE_FE0_VBASE IO_ADDRESS(SUNXI_DE_FE0_PBASE)
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#define SUNXI_DE_BE0_VBASE IO_ADDRESS(SUNXI_DE_BE0_PBASE)
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#define SUNXI_DRC0_VBASE IO_ADDRESS(SUNXI_DRC0_PBASE)
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#define SUNXI_SAT_VBASE IO_ADDRESS(SUNXI_SAT_PBASE)
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#define SUNXI_RTC_VBASE IO_ADDRESS(SUNXI_RTC_PBASE)
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#define SUNXI_R_TIMER_VBASE IO_ADDRESS(SUNXI_R_TIMER_PBASE)
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#define SUNXI_R_INTC_VBASE IO_ADDRESS(SUNXI_R_INTC_PBASE)
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#define SUNXI_R_WDOG_VBASE IO_ADDRESS(SUNXI_R_WDOG_PBASE)
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#define SUNXI_R_PRCM_VBASE IO_ADDRESS(SUNXI_R_PRCM_PBASE)
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#define SUNXI_R_CPUCFG_VBASE IO_ADDRESS(SUNXI_R_CPUCFG_PBASE)
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#define SUNXI_R_TWI_VBASE IO_ADDRESS(SUNXI_R_TWI_PBASE)
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#define SUNXI_R_UART_VBASE IO_ADDRESS(SUNXI_R_UART_PBASE)
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#define SUNXI_R_PIO_VBASE IO_ADDRESS(SUNXI_R_PIO_PBASE)
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#define SUNXI_R_RSB_VBASE IO_ADDRESS(SUNXI_R_RSB_PBASE)
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#define SUNXI_R_PWM_VBASE IO_ADDRESS(SUNXI_R_PWM_PBASE)
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/*
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* watchdog reg off
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*/
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#define R_WDOG_IRQ_EN_REG 0x0
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#define R_WDOG_IRQ_STA_REG 0x4
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#define R_WDOG_CTRL_REG 0x10
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#define R_WDOG_CFG_REG 0x14
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#define R_WDOG_MODE_REG 0x18
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/*
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* cpucfg
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*/
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#define SUNXI_CPUCFG_P_REG0 0x01a4
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#define SUNXI_CPUCFG_P_REG1 0x01a8
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#define CPUX_RESET_CTL(x) (0x40 + (x) * 0x40)
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#define CPUX_CONTROL(x) (0x44 + (x) * 0x40)
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#define CPUX_STATUS(x) (0x48 + (x) * 0x40)
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#define SUNXI_SYS_RST 0x0140
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#define SUNXI_CPUCFG_GENCTL 0x0184
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#define SUNXI_CPUCFG_DBGCTL0 0x01e0
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#define SUNXI_CPUCFG_DBGCTL1 0x01e4
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/*
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* prcm
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*/
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#define SUNXI_CPU_PWROFF_REG 0x100
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#define SUNXI_CPUX_PWR_CLAMP(x) (0x140 + (x)*0x04)
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/*
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* uart reg off
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*/
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#define SUNXI_UART_RBR 0x00 /* receive buffer register */
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#define SUNXI_UART_THR 0x00 /* transmit holding register */
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#define SUNXI_UART_DLL 0x00 /* divisor latch low register */
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#define SUNXI_UART_DLH 0x04 /* diviso latch high register */
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#define SUNXI_UART_IER 0x04 /* interrupt enable register */
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#define SUNXI_UART_IIR 0x08 /* interrupt identity register */
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#define SUNXI_UART_FCR 0x08 /* FIFO control register */
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#define SUNXI_UART_LCR 0x0c /* line control register */
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#define SUNXI_UART_MCR 0x10 /* modem control register */
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#define SUNXI_UART_LSR 0x14 /* line status register */
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#define SUNXI_UART_MSR 0x18 /* modem status register */
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#define SUNXI_UART_SCH 0x1c /* scratch register */
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#define SUNXI_UART_USR 0x7c /* status register */
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#define SUNXI_UART_TFL 0x80 /* transmit FIFO level */
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#define SUNXI_UART_RFL 0x84 /* RFL */
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#define SUNXI_UART_HALT 0xa4 /* halt tx register */
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#define UART_USR (SUNXI_UART_USR >> 2)
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#define UART_HALT (SUNXI_UART_HALT >> 2)
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#define UART_SCH (SUNXI_UART_SCH >> 2)
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#define UART_FORCE_CFG (1 << 1)
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#define UART_FORCE_UPDATE (1 << 2)
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#define SUNXI_UART_LOG(fmt, args...) do {} while (0)
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#define SUNXI_R_UART_LOG(fmt, args...) \
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do { \
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aw_printk((u32)SUNXI_R_UART_PBASE, "[%s]"fmt"\n", __FUNCTION__, ##args); \
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} while (0)
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#endif /* __PLATFORM_SUN8I_W5P1_H */
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