577 lines
13 KiB
C
577 lines
13 KiB
C
/*
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* The driver of sunxi emce.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* zhouhuacai <zhouhuacai@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/crypto.h>
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#include <linux/scatterlist.h>
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#include <linux/clk.h>
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#include <linux/clk/sunxi.h>
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#include "sunxi_emce.h"
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#ifdef CONFIG_OF
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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static const struct of_device_id sunxi_emce_of_match[] = {
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{.compatible = "allwinner,sunxi-emce",},
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{},
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};
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MODULE_DEVICE_TABLE(of, sunxi_emce_of_match);
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#endif
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#define STORAGE_NAND 0
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#define STORAGE_EMMC 2
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static int boot_type_cmdline = -1;
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static unsigned int boot_type_parse(char *boot_type)
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{
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long int ret;
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int tmp;
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tmp = kstrtol(boot_type, 0, &ret);
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if (STORAGE_NAND == ret)
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return 0;
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if (STORAGE_EMMC == ret)
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return 1;
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return -1;
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}
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static int __init early_boot_type(char *boot_type)
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{
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pr_debug("%s(%s)\n", __func__, boot_type);
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boot_type_cmdline = boot_type_parse(boot_type);
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return 0;
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}
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early_param("boot_type", early_boot_type);
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struct sunxi_emce_t *emce_dev;
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void sunxi_emce_dump(void *addr, u32 size)
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{
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int i;
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pr_debug("=========dump:size:0x%x=========\n", size);
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for (i = 0; i < size; i += 4) {
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if (!(i&0xf))
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pr_debug("\n0x%p : ", (addr + i));
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pr_debug("%08x ", readl(addr + i));
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}
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pr_debug("\n");
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return;
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}
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static DEFINE_MUTEX(emce_lock);
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static void emce_dev_lock(void)
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{
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mutex_lock(&emce_lock);
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}
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static void emce_dev_unlock(void)
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{
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mutex_unlock(&emce_lock);
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}
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static int sunxi_emce_gen_salt(const u8 *mkey,
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u32 mklen, u8 *skey, u32 *sklen)
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{
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int ret = 0;
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struct scatterlist sg = {0};
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struct crypto_hash *tfm = NULL;
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struct hash_desc desc = {0};
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EMCE_ENTER();
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tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
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if (IS_ERR(tfm)) {
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ret = PTR_ERR(tfm);
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EMCE_ERR("Failed to alloc sha256 tfm. %p\n", tfm);
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goto out2;
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}
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desc.tfm = tfm;
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desc.flags = 0;
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sg_init_one(&sg, mkey, mklen);
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ret = crypto_hash_digest(&desc, &sg, mklen, skey);
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if (ret) {
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EMCE_ERR("Failed to do SHA256(), mklen: %d\n", mklen);
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goto out1;
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}
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*sklen = EMCE_SALT_KEY_LEN;
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out1:
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crypto_free_hash(tfm);
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out2:
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return ret;
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}
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static inline void sunxi_emce_set_bit(void __iomem *reg_addr,
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u32 mask, u32 bit, u32 val)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_addr);
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reg_val &= (~mask);
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reg_val |= (val << bit);
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writel(reg_val, reg_addr);
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}
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static inline u32 sunxi_emce_get_bit(void __iomem *reg_addr, u32 mask, u32 bit)
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{
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u32 reg_val = 0;
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reg_val = readl(reg_addr);
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reg_val &= mask;
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return reg_val >> bit;
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}
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static int sunxi_emce_set_cfg(enum cfg_cmd cmd, u32 para)
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{
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int ret = 0;
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void __iomem *reg_addr = emce_dev->base_addr + EMCE_MODE;
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EMCE_ENTER();
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emce_dev_lock();
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switch (cmd) {
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case EMCE_SET_SECTOR_SIZE:
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sunxi_emce_set_bit(reg_addr, EMCE_SECTOR_SIZE_MASK,
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EMCE_SECTOR_SIZE_BIT, para);
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break;
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case EMCE_SET_IV_LEN:
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sunxi_emce_set_bit(reg_addr, EMCE_IV_LEN_MASK,
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EMCE_IV_LEN_BIT, para);
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break;
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case EMCE_SET_KEY_LEN:
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sunxi_emce_set_bit(reg_addr, EMCE_KEY_LEN_MASK,
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EMCE_KEY_LEN_BIT, para);
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break;
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case EMCE_SET_MODE:
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sunxi_emce_set_bit(reg_addr, EMCE_MODE_MASK,
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EMCE_MODE_BIT, para);
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break;
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default:
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EMCE_ERR("Unsupport cmd %d\n", cmd);
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break;
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}
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emce_dev_unlock();
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return ret;
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}
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void sunxi_emce_set_sector_size(u32 para)
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{
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sunxi_emce_set_cfg(EMCE_SET_SECTOR_SIZE, para);
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}
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EXPORT_SYMBOL_GPL(sunxi_emce_set_sector_size);
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void sunxi_emce_set_mode(u32 para)
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{
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sunxi_emce_set_cfg(EMCE_SET_MODE, para);
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}
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EXPORT_SYMBOL_GPL(sunxi_emce_set_mode);
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void sunxi_emce_set_key_len(u32 para)
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{
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sunxi_emce_set_cfg(EMCE_SET_IV_LEN, para);
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sunxi_emce_set_cfg(EMCE_SET_KEY_LEN, para);
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}
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EXPORT_SYMBOL_GPL(sunxi_emce_set_key_len);
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static void sunxi_emce_set_cur_controller(struct sunxi_emce_t *emce_pdev, u32 para)
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{
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void __iomem *reg_addr = emce_pdev->base_addr + EMCE_MODE;
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sunxi_emce_set_bit(reg_addr, EMCE_CUR_CTR_MASK, EMCE_CUR_CTR_BIT, para);
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}
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static void sunxi_emce_set_masterkey(const u8 *mkey, u32 klen)
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{
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int i = 0;
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void __iomem *reg_addr = emce_dev->base_addr + EMCE_MASTER_KEY_OFFSET;
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if ((NULL == mkey) || (klen <= 0))
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EMCE_ERR("sunxi emce masterkey error\n ");
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for (i = 0; i < klen; i = i + 4)
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writel(*(u32 *)(mkey + i) , (reg_addr + i));
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}
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static void sunxi_emce_set_saltkey(const u8 *skey, u32 klen)
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{
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int i = 0;
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void __iomem *reg_addr = emce_dev->base_addr + EMCE_SALT_KEY_OFFSET;
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if ((NULL == skey) || (klen <= 0))
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EMCE_ERR("sunxi emce saltkey error\n ");
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for (i = 0; i < klen; i = i + 4)
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writel((*(u32 *)(skey + i)), reg_addr + i);
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}
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int sunxi_emce_set_key(const u8 *mkey, u32 len)
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{
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u8 saltkey[EMCE_SALT_KEY_LEN];
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u32 skey_len = 0;
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int ret = 0;
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EMCE_ENTER();
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if ((NULL == mkey) || (len <= 0))
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EMCE_ERR("sunxi emce key error\n ");
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ret = sunxi_emce_gen_salt(mkey, len, saltkey, &skey_len);
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if (!ret) {
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sunxi_emce_set_saltkey(saltkey, skey_len);
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sunxi_emce_set_masterkey(mkey, len);
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}
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return ret;
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}
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EXPORT_SYMBOL_GPL(sunxi_emce_set_key);
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static int sunxi_emce_get_version(void)
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{
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int ver = 0;
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ver = readl(emce_dev->base_addr + EMCE_VER);
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pr_info("[EMCE]:VER:0x%x\n", ver);
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return ver;
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}
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static void sunxi_emce_show_cur_controller(u32 cur_controller)
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{
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if (cur_controller)
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pr_info("[EMCE]:Current Controller is EMMC!\n");
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else
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pr_info("[EMCE]:Current Controller is NAND!\n");
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}
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static int sunxi_emce_hw_init(struct sunxi_emce_t *emce)
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{
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struct device_node *pnode = emce->pdev->dev.of_node;
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struct clk *pclk = NULL;
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int ret;
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pclk = of_clk_get(pnode, 1);
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if (IS_ERR_OR_NULL(pclk)) {
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EMCE_ERR("Unable to get pclk, return %x\n", PTR_RET(pclk));
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return PTR_RET(pclk);
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}
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emce->mclk = of_clk_get(pnode, 0);
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if (IS_ERR_OR_NULL(emce->mclk)) {
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EMCE_ERR("Unable to get mclk, return %x\n",
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PTR_RET(emce->mclk));
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return PTR_RET(emce->mclk);
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}
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if (of_property_read_u32(pnode, "clock-frequency",
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&emce->gen_clkrate)) {
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EMCE_ERR("Unable to get clock-frequency.\n");
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return -EINVAL;
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}
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ret = clk_set_parent(emce->mclk, pclk);
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if (ret != 0) {
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EMCE_ERR("clk_set_parent() failed! return %d\n", ret);
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return ret;
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}
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ret = clk_set_rate(emce->mclk, emce->gen_clkrate);
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if (ret != 0) {
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EMCE_ERR("clk_set_rate(%d) failed! return %d\n",
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emce->gen_clkrate, ret);
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return ret;
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}
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EMCE_DBG("[EMCE]: mclk %luMHz, pclk %luMHz\n",
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clk_get_rate(emce->mclk)/1000000,
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clk_get_rate(pclk)/1000000);
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if (clk_prepare_enable(emce->mclk)) {
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EMCE_ERR("Couldn't enable module clock\n");
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return -EBUSY;
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}
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if (boot_type_cmdline == -1) {
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pr_info("[EMCE]:Unsupport Current Storage!\n");
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return -EINVAL;
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}
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else {
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sunxi_emce_set_cur_controller(emce, boot_type_cmdline);
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sunxi_emce_show_cur_controller(boot_type_cmdline);
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}
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clk_put(pclk);
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return 0;
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}
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static int sunxi_emce_hw_exit(struct sunxi_emce_t *emce)
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{
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EMCE_EXIT();
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clk_disable_unprepare(emce->mclk);
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clk_put(emce->mclk);
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emce->mclk = NULL;
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return 0;
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}
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static int sunxi_emce_res_request(struct platform_device *pdev)
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{
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struct device_node *np = NULL;
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struct sunxi_emce_t *emce = platform_get_drvdata(pdev);
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np = pdev->dev.of_node;
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if (!of_device_is_available(np)) {
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EMCE_ERR("sunxi emce is disable\n");
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return -EPERM;
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}
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emce->base_addr = of_iomap(np, 0);
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if (emce->base_addr == 0) {
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EMCE_ERR("Failed to ioremap() io memory region.\n");
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return -EBUSY;
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} else
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EMCE_DBG("sunxi emce reg base: %p !\n", emce->base_addr);
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return 0;
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}
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static int sunxi_emce_res_release(struct sunxi_emce_t *emce)
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{
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iounmap(emce->base_addr);
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return 0;
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}
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static void emce_get_cur_ctl_str(struct sunxi_emce_t *emce, char *str)
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{
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if (str == NULL)
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return;
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if (!sunxi_emce_get_bit(emce->base_addr + EMCE_MODE,
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EMCE_CUR_CTR_MASK, EMCE_CUR_CTR_BIT))
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sprintf(str, "%s", "NDFC");
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else
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sprintf(str, "%s", "SMHC");
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}
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static void emce_get_key_len_str(u32 val, char *str)
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{
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if (str == NULL)
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return;
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switch (val) {
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case EMCE_KEY_128_BIT:
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sprintf(str, "%s", "128bit");
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break;
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case EMCE_KEY_192_BIT:
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sprintf(str, "%s", "192bit");
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break;
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case EMCE_KEY_256_BIT:
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sprintf(str, "%s", "256bit");
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break;
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default:
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sprintf(str, "%s", "reserved");
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break;
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}
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}
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static void emce_get_mode(struct sunxi_emce_t *emce, char *str)
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{
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if (str == NULL)
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return;
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if (!sunxi_emce_get_bit(emce->base_addr + EMCE_MODE,
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EMCE_MODE_MASK, EMCE_MODE_BIT))
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sprintf(str, "%s", "ECB");
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else
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sprintf(str, "%s", "CBC");
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}
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static ssize_t sunxi_emce_info_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 iv_len;
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u32 key_len;
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char cur_ctl_str[MAXNAME];
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char iv_len_str[MAXNAME];
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char key_len_str[MAXNAME];
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char mode_str[MAXNAME];
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struct platform_device *pdev;
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struct sunxi_emce_t *emce;
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pdev = container_of(dev, struct platform_device, dev);
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emce = platform_get_drvdata(pdev);
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iv_len = sunxi_emce_get_bit(emce->base_addr + EMCE_MODE,
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EMCE_IV_LEN_MASK, EMCE_IV_LEN_BIT),
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key_len = sunxi_emce_get_bit(emce->base_addr + EMCE_MODE,
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EMCE_KEY_LEN_MASK, EMCE_KEY_LEN_BIT),
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emce_get_cur_ctl_str(emce, cur_ctl_str);
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emce_get_mode(emce, mode_str);
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emce_get_key_len_str(iv_len, iv_len_str);
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emce_get_key_len_str(key_len, key_len_str);
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return snprintf(buf, PAGE_SIZE,
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"pdev->id = %d\n"
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"pdev->name = %s\n"
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"module clk rate = %ld Mhz\n"
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"IO membase = 0x%p\n"
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"sector size = 0x%x\n"
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"cur controller = %s\n"
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"AES key len(when calcu IV) = %s\n"
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"key len = %s\n"
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"mode = %s\n"
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"emce version = 0x%x\n",
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pdev->id, pdev->name,
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(clk_get_rate(emce->mclk)/1000000), emce->base_addr,
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sunxi_emce_get_bit(emce->base_addr + EMCE_MODE,
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EMCE_SECTOR_SIZE_MASK, EMCE_SECTOR_SIZE_BIT),
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cur_ctl_str, iv_len_str, key_len_str, mode_str,
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readl(emce->base_addr + EMCE_VER));
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}
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static struct device_attribute sunxi_emce_info_attr =
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__ATTR(info, S_IRUGO, sunxi_emce_info_show, NULL);
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static void sunxi_emce_sysfs_create(struct platform_device *_pdev)
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{
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device_create_file(&_pdev->dev, &sunxi_emce_info_attr);
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}
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static void sunxi_emce_sysfs_remove(struct platform_device *_pdev)
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{
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device_remove_file(&_pdev->dev, &sunxi_emce_info_attr);
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}
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static int sunxi_emce_probe(struct platform_device *pdev)
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{
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u32 ret = 0;
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struct sunxi_emce_t *emce = NULL;
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emce = devm_kzalloc(&pdev->dev, sizeof(emce), GFP_KERNEL);
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if (emce == NULL) {
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EMCE_ERR("Unable to allocate emce_data\n");
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return -ENOMEM;
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}
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snprintf(emce->dev_name, sizeof(emce->dev_name), SUNXI_EMCE_DEV_NAME);
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platform_set_drvdata(pdev, emce);
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ret = sunxi_emce_res_request(pdev);
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if (ret != 0)
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goto err0;
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emce->pdev = pdev;
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ret = sunxi_emce_hw_init(emce);
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if (ret != 0) {
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EMCE_ERR("emce hw init failed!\n");
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goto err1;
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}
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emce_dev = emce;
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ret = sunxi_emce_get_version();
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if (!ret) {
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EMCE_ERR("sunxi emce version error\n");
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ret = -ENXIO;
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goto err1;
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}
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sunxi_emce_sysfs_create(pdev);
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return 0;
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err1:
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sunxi_emce_res_release(emce);
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err0:
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platform_set_drvdata(pdev, NULL);
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return ret;
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}
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static int sunxi_emce_remove(struct platform_device *pdev)
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{
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struct sunxi_emce_t *emce = platform_get_drvdata(pdev);
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sunxi_emce_sysfs_remove(pdev);
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sunxi_emce_hw_exit(emce);
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sunxi_emce_res_release(emce);
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platform_set_drvdata(pdev, NULL);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int sunxi_emce_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct sunxi_emce_t *emce = platform_get_drvdata(pdev);
|
|
|
|
EMCE_ENTER();
|
|
sunxi_emce_hw_exit(emce);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_emce_resume(struct device *dev)
|
|
{
|
|
int ret = 0;
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct sunxi_emce_t *emce = platform_get_drvdata(pdev);
|
|
|
|
EMCE_ENTER();
|
|
ret = sunxi_emce_hw_init(emce);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops sunxi_emce_dev_pm_ops = {
|
|
.suspend = sunxi_emce_suspend,
|
|
.resume = sunxi_emce_resume,
|
|
};
|
|
|
|
#define SUNXI_EMCE_DEV_PM_OPS (&sunxi_emce_dev_pm_ops)
|
|
#else
|
|
#define SUNXI_EMCE_DEV_PM_OPS NULL
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct platform_driver sunxi_emce_driver = {
|
|
.probe = sunxi_emce_probe,
|
|
.remove = sunxi_emce_remove,
|
|
.driver = {
|
|
.name = SUNXI_EMCE_DEV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.pm = SUNXI_EMCE_DEV_PM_OPS,
|
|
.of_match_table = sunxi_emce_of_match,
|
|
},
|
|
};
|
|
|
|
static int __init sunxi_emce_init(void)
|
|
{
|
|
int ret = 0;
|
|
EMCE_DBG("Sunxi EMCE init ...\n");
|
|
ret = platform_driver_register(&sunxi_emce_driver);
|
|
if (ret < 0)
|
|
EMCE_ERR("platform_driver_register() failed, return %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit sunxi_emce_exit(void)
|
|
{
|
|
platform_driver_unregister(&sunxi_emce_driver);
|
|
}
|
|
|
|
module_init(sunxi_emce_init);
|
|
module_exit(sunxi_emce_exit);
|
|
|
|
MODULE_AUTHOR("zhouhuacai");
|
|
MODULE_DESCRIPTION("SUNXI EMCE Driver");
|
|
MODULE_ALIAS("platform:"SUNXI_EMCE_DEV_NAME);
|
|
MODULE_LICENSE("GPL");
|
|
|