293 lines
No EOL
7.9 KiB
C
Executable file
293 lines
No EOL
7.9 KiB
C
Executable file
/*
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* linux-3.10/drivers/media/platform/sunxi-vfe/csi/csi_reg.h
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*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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* sunxi csi register read/write interface header file
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* Author:raymonxiu
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*/
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#ifndef __CSI__REG__H__
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#define __CSI__REG__H__
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#include <linux/types.h>
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#define MAX_CSI 2
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/*
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* if format
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*/
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enum csi_if
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{
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CSI_IF_INTLV =0x00, /* 1SEG DATA in one channel */
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CSI_IF_SPL =0x01, /* 2SEG: 1SEG Y in one channel , 1SEG UV in second channel */
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CSI_IF_PL =0x02, /* 3SEG YUV444 */
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CSI_IF_PL_SPL =0x03, /* 3SEG YUV444 to 2SEG YUV422 */
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CSI_IF_CCIR656_1CH =0x04, /* 1SEG ccir656 1ch */
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CSI_IF_CCIR656_1CH_SPL =0x05, /* 2SEG ccir656 1ch */
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CSI_IF_CCIR656_1CH_PL =0x06, /* 3SEG ccir656 1ch */
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CSI_IF_CCIR656_1CH_PL_SPL =0x07, /* 3SEG to 2SEG ccir656 1ch */
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CSI_IF_CCIR656_2CH =0x0c, /* D7~D0:ccir656 2ch */
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CSI_IF_CCIR656_4CH =0x0d, /* D7~D0:ccir656 4ch */
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CSI_IF_MIPI =0x80, /* MIPI CSI */
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};
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/*
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* data width
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*/
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enum csi_data_width
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{
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CSI_8BIT =0,
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CSI_10BIT =1,
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CSI_12BIT =2,
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};
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/*
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* input data format
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*/
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enum csi_input_fmt
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{
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CSI_RAW=0, /* raw stream */
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//CSI_BAYER=1,
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CSI_YUV422=3, /* yuv422 */
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CSI_YUV420=4, /* yuv420 */
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};
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/*
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* output data format
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*/
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enum csi_output_fmt
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{
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/* only when input is raw */
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CSI_FIELD_RAW_8 = 0,
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CSI_FIELD_RAW_10 = 1,
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CSI_FIELD_RAW_12 = 2,
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CSI_FIELD_RGB565 = 4,
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CSI_FIELD_RGB888 = 5,
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CSI_FIELD_PRGB888 = 6,
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CSI_FRAME_RAW_8 = 8,
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CSI_FRAME_RAW_10 = 9,
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CSI_FRAME_RAW_12 = 10,
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CSI_FRAME_RGB565 = 12,
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CSI_FRAME_RGB888 = 13,
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CSI_FRAME_PRGB888 = 14,
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/* only when input is bayer */
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//CSI_PLANAR_RGB242 = 0, /* planar rgb242 */
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/* only when input is yuv422/yuv420 */
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CSI_FIELD_PLANAR_YUV422 = 0, /* parse a field(odd or even) into planar yuv420 */
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CSI_FIELD_PLANAR_YUV420 = 1, /* parse a field(odd or even) into planar yuv420 */
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CSI_FRAME_PLANAR_YUV420 = 2, /* parse and reconstruct every 2 fields(odd and even) into a frame, format is planar yuv420 */
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CSI_FRAME_PLANAR_YUV422 = 3,
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CSI_FIELD_UV_CB_YUV422 = 4,
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CSI_FIELD_UV_CB_YUV420 = 5,
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CSI_FRAME_UV_CB_YUV420 = 6,
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CSI_FRAME_UV_CB_YUV422 = 7,
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CSI_FIELD_MB_YUV422 = 8,
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CSI_FIELD_MB_YUV420 = 9,
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CSI_FRAME_MB_YUV420 = 10,
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CSI_FRAME_MB_YUV422 = 11,
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CSI_FIELD_UV_CB_YUV422_10 = 12,
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CSI_FIELD_UV_CB_YUV420_10 = 13,
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//CSI_INTLC_INTLV_YUV422 = 15,
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};
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/*
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* field sequenc or polarity
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*/
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enum csi_field
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{
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/* For Embedded Sync timing*/
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CSI_FIELD_TF = 0, /* top filed first */
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CSI_FIELD_BF = 1, /* bottom field first */
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/* For External Sync timing */
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CSI_FIELD_NEG = 0, /* field negtive indicates odd field */
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CSI_FIELD_POS = 1, /* field postive indicates odd field */
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};
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/*
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* input field selection, only when input is ccir656
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*/
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enum csi_field_sel
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{
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CSI_ODD, /* odd field */
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CSI_EVEN, /* even field */
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CSI_EITHER, /* either field */
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};
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/*
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* input source type
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*/
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enum csi_src_type
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{
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CSI_PROGRESSIVE=0, /* progressive */
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CSI_INTERLACE=1, /* interlace */
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};
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/*
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* input data sequence
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*/
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enum csi_input_seq
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{
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/* only when input is yuv422 */
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CSI_YUYV=0,
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CSI_YVYU,
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CSI_UYVY,
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CSI_VYUY,
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/* only when input is byer */
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CSI_RGRG=0, /* first line sequence is RGRG... */
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CSI_GRGR, /* first line sequence is GRGR... */
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CSI_BGBG, /* first line sequence is BGBG... */
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CSI_GBGB, /* first line sequence is GBGB... */
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};
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/*
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* input reference signal polarity
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*/
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enum csi_ref_pol
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{
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CSI_LOW, /* active low */
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CSI_HIGH, /* active high */
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};
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/*
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* input data valid of the input clock edge type
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*/
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enum csi_edge_pol
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{
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CSI_FALLING, /* active falling */
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CSI_RISING, /* active rising */
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};
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/*
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* csi interface configuration
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*/
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struct csi_if_cfg
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{
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enum csi_src_type src_type; /* interlaced or progressive */
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enum csi_data_width data_width; /* csi data width */
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enum csi_if interface; /* csi interface */
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};
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/*
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* csi timing configuration
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*/
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struct csi_timing_cfg
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{
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enum csi_field field; /* top or bottom field first / field polarity */
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enum csi_ref_pol vref; /* input vref signal polarity */
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enum csi_ref_pol href; /* input href signal polarity */
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enum csi_edge_pol sample; /* input data valid of the input clock edge type */
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};
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/*
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* csi mode configuration
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*/
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struct csi_fmt_cfg
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{
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enum csi_input_fmt input_fmt; /* input data format */
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enum csi_output_fmt output_fmt; /* output data format */
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enum csi_field_sel field_sel; /* input field selection */
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enum csi_input_seq input_seq; /* input data sequence */
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enum csi_data_width data_width; /* csi data width */
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};
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/*
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* csi buffer
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*/
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enum csi_buf_sel
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{
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CSI_BUF_0_A = 0, /* FIFO for Y address A */
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CSI_BUF_0_B, /* FIFO for Y address B */
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CSI_BUF_1_A, /* FIFO for Cb address A */
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CSI_BUF_1_B, /* FIFO for Cb address B */
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CSI_BUF_2_A, /* FIFO for Cr address A */
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CSI_BUF_2_B, /* FIFO for Cr address B */
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};
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/*
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* csi capture status
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*/
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struct csi_capture_status
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{
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_Bool picture_in_progress;
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_Bool video_in_progress;
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};
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enum csi_cap_mode
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{
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CSI_SCAP = 1,
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CSI_VCAP ,
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};
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/*
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* csi interrupt
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*/
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enum csi_int_sel
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{
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CSI_INT_CAPTURE_DONE = 0X1,
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CSI_INT_FRAME_DONE = 0X2,
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CSI_INT_BUF_0_OVERFLOW = 0X4,
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CSI_INT_BUF_1_OVERFLOW = 0X8,
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CSI_INT_BUF_2_OVERFLOW = 0X10,
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CSI_INT_PROTECTION_ERROR = 0X20,
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CSI_INT_HBLANK_OVERFLOW = 0X40,
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CSI_INT_VSYNC_TRIG = 0X80,
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CSI_INT_ALL = 0XFF,
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};
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/*
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* csi interrupt status
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*/
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struct csi_int_status
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{
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_Bool capture_done;
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_Bool frame_done;
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_Bool buf_0_overflow;
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_Bool buf_1_overflow;
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_Bool buf_2_overflow;
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_Bool protection_error;
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_Bool hblank_overflow;
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_Bool vsync_trig;
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};
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int csi_set_base_addr(unsigned int sel, unsigned long addr);
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void csi_enable(unsigned int sel);
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void csi_disable(unsigned int sel);
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void csi_if_cfg(unsigned int sel, struct csi_if_cfg *csi_if_cfg);
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void csi_timing_cfg(unsigned int sel, struct csi_timing_cfg *csi_tmg_cfg);
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void csi_fmt_cfg(unsigned int sel, unsigned int ch, struct csi_fmt_cfg *csi_fmt_cfg);
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void csi_set_buffer_address(unsigned int sel, unsigned int ch, enum csi_buf_sel buf, u64 addr);
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u64 csi_get_buffer_address(unsigned int sel, unsigned int ch, enum csi_buf_sel buf);
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void csi_capture_start(unsigned int sel, unsigned int ch_total_num, enum csi_cap_mode csi_cap_mode);
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void csi_capture_stop(unsigned int sel, unsigned int ch_total_num, enum csi_cap_mode csi_cap_mode);
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void csi_capture_get_status(unsigned int sel, unsigned int ch, struct csi_capture_status *status);
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void csi_set_size(unsigned int sel, unsigned int ch, unsigned int length_h, unsigned int length_v, unsigned int buf_length_y, unsigned int buf_length_c);
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void csi_set_offset(unsigned int sel, unsigned int ch, unsigned int start_h, unsigned int start_v);
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void csi_int_enable(unsigned int sel, unsigned int ch, enum csi_int_sel interrupt);
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void csi_int_disable(unsigned int sel, unsigned int ch, enum csi_int_sel interrupt);
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void csi_int_get_status(unsigned int sel, unsigned int ch,struct csi_int_status *status);
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void csi_int_clear_status(unsigned int sel, unsigned int ch, enum csi_int_sel interrupt);
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#endif |