181 lines
6.1 KiB
C
181 lines
6.1 KiB
C
#ifndef _PM_CONFIG_SUN8IW11P1_H
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#define _PM_CONFIG_SUN8IW11P1_H
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/*
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* Copyright (c) 2011-2015 yanggq.young@allwinnertech.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include "pm_def_i.h"
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#include "asm-generic/sizes.h"
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#define SUNXI_SRAM_A1_PBASE (0x00000000)
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#define SUNXI_SRAM_A2_PBASE (0x00004000)
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#define SUNXI_SRAM_A3_PBASE (0x00008000)
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#define SUNXI_PIO_PBASE (0x01c20800)
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#define SUNXI_R_PRCM_PBASE (0)
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#define SUNXI_MSGBOX_PBASE (0)
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#define SUNXI_SPINLOCK_PBASE (0)
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#define SUNXI_R_PIO_PBASE (0)
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#define SUNXI_R_CPUCFG_PBASE (0)
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#define SUNXI_UART0_PBASE (0x01c28000)
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#define SUNXI_TWI0_PBASE (0x01c2ac00)
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#define SUNXI_TWI1_PBASE (0x01c2b000)
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#define SUNXI_TWI2_PBASE (0x01c2b400)
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#define SUNXI_CPUCFG_P_REG0 (0)
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#define SUNXI_CPUCFG_GENCTL (0)
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#define SUNXI_CPUX_PWR_CLAMP(x) (0)
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#define SUNXI_CPUX_PWR_CLAMP_STATUS(x) (0)
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#define SUNXI_CPU_PWROFF_REG (0)
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#define SUNXI_RTC_PBASE (0x01c20400)
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#define SUNXI_SRAMCTRL_PBASE (0x01c00000)
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#define SUNXI_LRADC_PBASE (0x01c24400)
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#define SUNXI_GIC_DIST_PBASE (0)
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#define SUNXI_GIC_CPU_PBASE (0)
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#define SUNXI_TIMER_PBASE (0)
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#define SUNXI_CCM_PBASE (0)
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#ifdef CONFIG_FPGA_V4_PLATFORM
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#define SUNXI_IRQ_TIMER0 (38)
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#else
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#define SUNXI_IRQ_TIMER0 (54)
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#endif
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#define SUNXI_IRQ_TIMER1 (55)
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#define SUNXI_IRQ_LRADC (62)
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#define SUNXI_IRQ_NMI (32)
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#define SUNXI_IRQ_ALARM0 (56)
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#define SUNXI_IRQ_USBOTG (70)
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#define SUNXI_IRQ_USBEHCI0 (71)
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#define SUNXI_IRQ_USBOHCI0 (72)
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#define SUNXI_IRQ_USBEHCI1 (96)
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#define SUNXI_IRQ_USBOHCI1 (108)
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#define SUNXI_IRQ_EINTA (0)
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#define SUNXI_IRQ_EINTB (0)
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#define SUNXI_IRQ_EINTD (0)
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#define SUNXI_IRQ_EINTE (0)
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#define SUNXI_IRQ_EINTF (0)
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#define SUNXI_IRQ_EINTG (0)
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#define SUNXI_IRQ_EINTH (60)
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#define SUNXI_IRQ_EINTI (60)
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#define SUNXI_IRQ_MBOX (0)
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#define SUNXI_IRQ_WLAN (0)
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#define SUNXI_BANK_SIZE 32
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#define SUNXI_PA_BASE 0
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#define SUNXI_PB_BASE 32
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#define SUNXI_PC_BASE 64
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#define SUNXI_PD_BASE 96
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#define SUNXI_PE_BASE 128
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#define SUNXI_PF_BASE 160
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#define SUNXI_PG_BASE 192
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#define SUNXI_PH_BASE 224
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#define SUNXI_PI_BASE 256
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#define SUNXI_PJ_BASE 288
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#define SUNXI_PK_BASE 320
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#define SUNXI_PL_BASE 352
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#define SUNXI_PM_BASE 384
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#define SUNXI_PN_BASE 416
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#define SUNXI_PO_BASE 448
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#define AXP_PIN_BASE 1024
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/*debug reg*/
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#define STANDBY_STATUS_REG (0xf1c20500)
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#define STANDBY_STATUS_REG_PA (0x01c20500)
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#define STANDBY_STATUS_REG_NUM (4)
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#define STANDBY_SUPER_FLAG_REG (0xf1c205f8)
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#define STANDBY_SUPER_ADDR_REG (0xf1c205fc)
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/*module base reg*/
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#define AW_LRADC01_BASE (SUNXI_LRADC_PBASE)
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#define AW_CCM_BASE (0x01c20000)
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#define AW_CCM_MOD_BASE (0x01c20000)
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#define AW_CCM_PIO_BUS_GATE_REG_OFFSET (0x68)
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#define AW_CCU_UART_PA (0x01c2006C) /*uart0 gating: bit16, 0: mask, 1: pass */
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#define AW_CCU_UART_RESET_PA (0x01c202D8) /*uart0 reset: bit16, 0: reset, 1: de_assert */
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#define AW_UART0_PBASE (0x01c28000)
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/*uart & jtag para*/
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#define AW_JTAG_PH_GPIO_PA (0x01c20800 + 0x28) /*jtag0: Pb14-Pb17, */
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#define AW_JTAG_PF_GPIO_PA (0x01c20800 + 0xB4) /*jtag0: PF0, PF1, PF3, PF5 bitmap: 0x40, 4044; */
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#define AW_UART_PH_GPIO_PA (0x01c20800 + 0x28) /*uart0: use PB */
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#define AW_UART_PF_GPIO_PA (0x01c20800 + 0xB4) /*uart0: PF2, PF4, bitmap: 0x04, 0400; */
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#define AW_JTAG_PH_CONFIG_VAL_MASK (0x0000ffff)
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#define AW_JTAG_PH_CONFIG_VAL (0x00003333)
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#define AW_JTAG_PF_CONFIG_VAL_MASK (0x00f0f0ff)
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#define AW_JTAG_PF_CONFIG_VAL (0x00303033)
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#define AW_UART_PH_CONFIG_VAL_MASK (0x000F0F00)
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#define AW_UART_PH_CONFIG_VAL (0x00030300)
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#define AW_UART_PF_CONFIG_VAL_MASK (0x000F0F00)
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#define AW_UART_PF_CONFIG_VAL (0x00030300)
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#define AW_JTAG_GPIO_PA (AW_JTAG_PF_GPIO_PA)
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#define AW_UART_GPIO_PA (AW_UART_PF_GPIO_PA)
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#define AW_JTAG_CONFIG_VAL_MASK AW_JTAG_PF_CONFIG_VAL_MASK
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#define AW_JTAG_CONFIG_VAL AW_JTAG_PF_CONFIG_VAL
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#define AW_RTC_BASE (SUNXI_RTC_PBASE)
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#define AW_SRAMCTRL_BASE (SUNXI_SRAMCTRL_PBASE)
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#define GPIO_REG_LENGTH ((0x278+0x4)>>2)
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#define CPUS_GPIO_REG_LENGTH ((0x218+0x4)>>2)
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#define SRAM_REG_LENGTH ((0xF4+0x4)>>2)
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#define CCU_REG_LENGTH ((0x2d8+0x4)>>2)
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/*int src no.*/
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#define AW_IRQ_TIMER1 (SUNXI_IRQ_TIMER1)
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#define AW_IRQ_TOUCHPANEL (0)
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#define AW_IRQ_LRADC (SUNXI_IRQ_LRADC)
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#define AW_IRQ_NMI (SUNXI_IRQ_NMI)
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#define AW_IRQ_MBOX (SUNXI_IRQ_MBOX)
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#define AW_IRQ_WLAN (SUNXI_IRQ_WLAN)
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#define AW_IRQ_ALARM (SUNXI_IRQ_ALARM0)
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#define AW_IRQ_IR0 (0)
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#define AW_IRQ_IR1 (0)
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#define AW_IRQ_USBOTG (SUNXI_IRQ_USBOTG)
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#define AW_IRQ_USBEHCI0 (SUNXI_IRQ_USBEHCI0)
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#define AW_IRQ_USBEHCI1 (SUNXI_IRQ_USBEHCI1)
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#define AW_IRQ_USBEHCI2 (0)
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#define AW_IRQ_USBOHCI0 (SUNXI_IRQ_USBOHCI0)
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#define AW_IRQ_USBOHCI1 (SUNXI_IRQ_USBOHCI1)
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#define AW_IRQ_USBOHCI2 (0)
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#define AW_IRQ_GPIOA (0)
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#define AW_IRQ_GPIOB (0)
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#define AW_IRQ_GPIOC (0)
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#define AW_IRQ_GPIOD (0)
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#define AW_IRQ_GPIOE (0)
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#define AW_IRQ_GPIOF (0)
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#define AW_IRQ_GPIOG (0)
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#define AW_IRQ_GPIOH (SUNXI_IRQ_EINTH)
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#define AW_IRQ_GPIOI (SUNXI_IRQ_EINTI)
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#define AW_IRQ_GPIOJ (0)
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/**start address for function run in sram*/
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#define SRAM_FUNC_START (0xf0000000)
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#define SRAM_FUNC_START_PA (0x00000000)
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/*for mem mapping*/
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#define MEM_SW_VA_SRAM_BASE (0x00000000)
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#define MEM_SW_PA_SRAM_BASE (0x00000000)
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/*dram area*/
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#define DRAM_BASE_ADDR_PA (0x40000000)
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#define DRAM_TRANING_SIZE (16)
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#define CPU_CLK_REST_DEFAULT_VAL (0x00010000) /*SRC is HOSC. */
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/**---stack point address in sram-------------*/
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/*
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* notice: try not to use last 0xc bytes,
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* considering the ds-5 debugger will access (last + 0xc) bytes with unknown reason,
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* which will hangup the soc.
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**/
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#define SP_IN_SRAM 0xf000bff0 /*end of 48k */
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#define SP_IN_SRAM_PA 0x0000bff0 /*end of 48k */
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#define SP_IN_SRAM_START (SRAM_FUNC_START_PA | 0x3c00) /*15k */
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#endif /*_PM_CONFIG_SUN8IW11P1_H*/
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