100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
/*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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*********************************************************************************************************
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* LINUX-KERNEL
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* AllWinner Linux Platform Develop Kits
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* Kernel Module
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*
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* (c) Copyright 2011-2015, gq.yang China
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* All Rights Reserved
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*
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* File : mem_tmr.h
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* By : gq.yang
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* Version : v1.0
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* Date : 2012-11-31 15:23
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* Descript:
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* Update : date auther ver notes
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*********************************************************************************************************
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*/
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#ifndef __MEM_TMR_H__
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#define __MEM_TMR_H__
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typedef struct __MEM_TMR_REG {
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/* offset:0x00 */
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volatile __u32 IntCtl;
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volatile __u32 IntSta;
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volatile __u32 reserved0[2];
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/* offset:0x10 */
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volatile __u32 Tmr0Ctl;
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volatile __u32 Tmr0IntVal;
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volatile __u32 Tmr0CntVal;
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volatile __u32 reserved1;
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/* offset:0x20 */
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volatile __u32 Tmr1Ctl;
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volatile __u32 Tmr1IntVal;
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volatile __u32 Tmr1CntVal;
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volatile __u32 reserved2;
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/* offset:0x30 */
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volatile __u32 Tmr2Ctl;
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volatile __u32 Tmr2IntVal;
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volatile __u32 Tmr2CntVal;
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volatile __u32 reserved3;
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/* offset:0x40 */
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volatile __u32 Tmr3Ctl;
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volatile __u32 Tmr3IntVal;
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volatile __u32 reserved4[2];
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/* offset:0x50 */
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volatile __u32 Tmr4Ctl;
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volatile __u32 Tmr4IntVal;
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volatile __u32 Tmr4CntVal;
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volatile __u32 reserved5;
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/* offset:0x60 */
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volatile __u32 Tmr5Ctl;
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volatile __u32 Tmr5IntVal;
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volatile __u32 Tmr5CntVal;
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volatile __u32 reserved6[5];
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/* offset:0x80 */
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volatile __u32 AvsCtl;
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volatile __u32 Avs0Cnt;
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volatile __u32 Avs1Cnt;
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volatile __u32 AvsDiv;
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/* offset:0x90: reserved */
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volatile __u32 reserved7[4];
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/* offset:0xa0 */
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volatile __u32 WDog1_Irq_En;
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volatile __u32 WDog1_Irq_Sta;
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volatile __u32 reserved8[2];
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/* offset:0xb0 */
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volatile __u32 WDog1_Ctrl_Reg;
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volatile __u32 WDog1_Cfg_Reg;
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volatile __u32 WDog1_Mode_Reg;
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} __mem_tmr_reg_t;
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/* for super standby; */
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__s32 mem_tmr_save(__mem_tmr_reg_t *ptmr_state);
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__s32 mem_tmr_restore(__mem_tmr_reg_t *ptmr_state);
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/* for normal standby; */
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__s32 mem_tmr_init(void);
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__s32 mem_tmr_exit(void);
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void mem_tmr_enable_watchdog(void);
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void mem_tmr_disable_watchdog(void);
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__s32 mem_tmr_set(__u32 second);
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#endif /* __MEM_TMR_H__ */
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