pandory500/redquark-amiberry-rb
2
0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Merge latest TomB version as of 10 July 2016

Browse source
This commit is contained in:
Chips 2016-07-10 18:01:00 +02:00
parent 6a8fc51848
commit 01740246dd
15 changed files with 633 additions and 124 deletions
Download patch file Download diff file Expand all files Collapse all files

18
src/jit/codegen_arm.cpp
View file

@ -248,7 +248,13 @@ LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, RR1 s))
{
#ifdef ARMV6T2
BFI_rrii(d, s, 0, 7);
#else
AND_rri(REG_WORK1, s, 0xff);
BIC_rri(d, d, 0xff);
ORR_rrr(d, d, REG_WORK1);
#endif
}
LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, RR1 s))
@ -603,7 +609,12 @@ LENDFUNC(WRITE,RMW,2,compemu_raw_add_l_mi,(IMM d, IMM s))
LOWFUNC(WRITE,NONE,2,compemu_raw_and_TAGMASK,(RW4 d))
{
// TAGMASK is 0x0000ffff
#ifdef ARMV6T2
BFC_rii(d, 16, 31);
#else
BIC_rri(d, d, 0x00ff0000);
BIC_rri(d, d, 0xff000000);
#endif
}
LENDFUNC(WRITE,NONE,2,compemu_raw_and_TAGMASK,(RW4 d))
@ -1009,9 +1020,14 @@ LOWFUNC(NONE,NONE,2,compemu_raw_endblock_pc_inreg,(RR4 rr_pc, IMM cycles))
}
STR_rRI(REG_WORK1, R_REGSTRUCT, offs);
#ifdef ARMV6T2
CC_B_i(NATIVE_CC_MI, 2);
BFC_rii(rr_pc, 16, 31); // apply TAGMASK
#else
CC_B_i(NATIVE_CC_MI, 3);
BIC_rri(rr_pc, rr_pc, 0x00ff0000);
BIC_rri(rr_pc, rr_pc, 0xff000000);
#endif
LDR_rRI(REG_WORK1, RPC_INDEX, 4); // <cache_tags>
LDR_rRR_LSLi(RPC_INDEX, REG_WORK1, rr_pc, 2);

16
src/jit/codegen_arm.h
View file

@ -1311,6 +1311,14 @@ enum {
#define CC_SADD16_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x61 << 20) | (Rn << 16) | (Rd << 12) | (0xf1 << 4) | (Rm))
#define SADD16_rrr(Rd,Rn,Rm) CC_SADD16_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_SXTAB_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x6a << 20) | (Rn << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define SXTAB_rrr(Rd,Rn,Rm) CC_SXTAB_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_SXTAH_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x6b << 20) | (Rn << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define SXTAH_rrr(Rd,Rn,Rm) CC_SXTAH_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
// ARMv6T2
#ifdef ARMV6T2
#define CC_BFI_rrii(cc,Rd,Rn,lsb,msb) _W(((cc) << 28) | (0x3e << 21) | ((msb) << 16) | (Rd << 12) | ((lsb) << 7) | (0x1 << 4) | (Rn))
#define BFI_rrii(Rd,Rn,lsb,msb) CC_BFI_rrii(NATIVE_CC_AL,Rd,Rn,lsb,msb)
@ -1320,18 +1328,12 @@ enum {
#define CC_UBFX_rrii(cc,Rd,Rn,lsb,width) _W(((cc) << 28) | (0x3f << 21) | ((width-1) << 16) | (Rd << 12) | ((lsb) << 7) | (0x5 << 4) | (Rn))
#define UBFX_rrii(Rd,Rn,lsb,width) CC_UBFX_rrii(NATIVE_CC_AL,Rd,Rn,lsb,width)
#define CC_SXTAB_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x6a << 20) | (Rn << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define SXTAB_rrr(Rd,Rn,Rm) CC_SXTAB_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_SXTAH_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x6b << 20) | (Rn << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define SXTAH_rrr(Rd,Rn,Rm) CC_SXTAH_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
// ARMv6T2
#define CC_MOVW_ri16(cc,Rd,i) _W(((cc) << 28) | (0x30 << 20) | (((i >> 12) & 0xf) << 16) | (Rd << 12) | (i & 0x0fff))
#define MOVW_ri16(Rd,i) CC_MOVW_ri16(NATIVE_CC_AL,Rd,i)
#define CC_MOVT_ri16(cc,Rd,i) _W(((cc) << 28) | (0x34 << 20) | (((i >> 12) & 0xf) << 16) | (Rd << 12) | (i & 0x0fff))
#define MOVT_ri16(Rd,i) CC_MOVT_ri16(NATIVE_CC_AL,Rd,i)
#endif
// Floatingpoint

122
src/jit/compemu_midfunc_arm2.cpp
View file

@ -57,12 +57,22 @@ const uae_u32 ARM_CCR_MAP[] = { 0, ARM_C_FLAG, // 1 C
unlock2(x); \
}
#ifdef ARMV6T2
#define DUPLICACTE_CARRY_FROM_REG(r) \
if (needed_flags & FLAG_X) { \
int x = writereg(FLAGX, 4); \
UBFX_rrii(x, r, 29, 1); \
unlock2(x); \
}
#else
#define DUPLICACTE_CARRY_FROM_REG(r) \
if (needed_flags & FLAG_X) { \
int x = writereg(FLAGX, 4); \
LSR_rri(x, r, 29); \
AND_rri(x, x, 1); \
unlock2(x); \
}
#endif
/*
* ADD
@ -357,13 +367,23 @@ MIDFUNC(3,jff_ADDX_b,(W4 d, RR1 s, RR1 v))
MSR_CPSRf_r(REG_WORK1);
MVN_ri(REG_WORK1, 0);
#ifdef ARMV6T2
BFI_rrii(REG_WORK1, s, 24, 31);
#else
BIC_rri(REG_WORK1, REG_WORK1, 0xff000000);
ORR_rrrLSLi(REG_WORK1, REG_WORK1, s, 24);
#endif
ADCS_rrrLSLi(d, REG_WORK1, v, 24);
ASR_rri(d, d, 24);
MRS_CPSR(REG_WORK1);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);
@ -388,13 +408,24 @@ MIDFUNC(3,jff_ADDX_w,(W4 d, RR2 s, RR2 v))
MSR_CPSRf_r(REG_WORK1);
MVN_ri(REG_WORK1, 0);
#ifdef ARMV6T2
BFI_rrii(REG_WORK1, s, 16, 31);
#else
BIC_rri(REG_WORK1, REG_WORK1, 0xff000000);
BIC_rri(REG_WORK1, REG_WORK1, 0x00ff0000);
ORR_rrrLSLi(REG_WORK1, REG_WORK1, s, 16);
#endif
ADCS_rrrLSLi(d, REG_WORK1, v, 16);
ASR_rri(d, d, 16);
MRS_CPSR(REG_WORK1);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);
@ -422,7 +453,12 @@ MIDFUNC(3,jff_ADDX_l,(W4 d, RR4 s, RR4 v))
MRS_CPSR(REG_WORK1);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);
@ -1144,8 +1180,15 @@ MIDFUNC(2,jff_BCHG_b_imm,(RW4 d, IMM s))
uae_u32 v = (1 << s);
MRS_CPSR(REG_WORK1);
EOR_rri(d, d, v);
#ifdef ARMV6T2
UBFX_rrii(REG_WORK2, d, s, 1);
BFI_rrii(REG_WORK1, REG_WORK2, 30, 30);
#else
LSR_rri(REG_WORK2, d, 29);
AND_rri(REG_WORK2, REG_WORK2, 1);
BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
ORR_rrrLSLi(REG_WORK1, REG_WORK1, REG_WORK2, 30);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(d);
@ -1159,8 +1202,15 @@ MIDFUNC(2,jff_BCHG_l_imm,(RW4 d, IMM s))
uae_u32 v = (1 << s);
MRS_CPSR(REG_WORK1);
EOR_rri(d, d, v);
#ifdef ARMV6T2
UBFX_rrii(REG_WORK2, d, s, 1);
BFI_rrii(REG_WORK1, REG_WORK2, 30, 30);
#else
LSR_rri(REG_WORK2, d, 29);
AND_rri(REG_WORK2, REG_WORK2, 1);
BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
ORR_rrrLSLi(REG_WORK1, REG_WORK1, REG_WORK2, 30);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(d);
@ -3278,7 +3328,12 @@ MIDFUNC(2,jff_NEGX_b,(W4 d, RR1 s))
MRS_CPSR(REG_WORK1);
EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);
@ -3307,7 +3362,12 @@ MIDFUNC(2,jff_NEGX_w,(W4 d, RR2 s))
MRS_CPSR(REG_WORK1);
EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);
@ -3335,7 +3395,12 @@ MIDFUNC(2,jff_NEGX_l,(W4 d, RR4 s))
MRS_CPSR(REG_WORK1);
EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);
@ -3602,7 +3667,13 @@ MIDFUNC(3,jff_ROL_b_imm,(W4 d, RR4 s, IMM i))
TST_rr(d, d);
MRS_CPSR(REG_WORK2);
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
#else
TST_ri(d, 1);
CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
#endif
MSR_CPSRf_r(REG_WORK2);
} else {
TST_rr(d, d);
@ -3627,7 +3698,13 @@ MIDFUNC(3,jff_ROL_w_imm,(W4 d, RR4 s, IMM i))
TST_rr(d, d);
MRS_CPSR(REG_WORK2);
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
#else
TST_ri(d, 1);
CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
#endif
MSR_CPSRf_r(REG_WORK2);
} else {
TST_rr(d, d);
@ -3651,7 +3728,13 @@ MIDFUNC(3,jff_ROL_l_imm,(W4 d, RR4 s, IMM i))
MOVS_rr(d, s);
MRS_CPSR(REG_WORK2);
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
#else
TST_ri(d, 1);
CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
#endif
MSR_CPSRf_r(REG_WORK2);
} else {
MOVS_rr(d, s);
@ -3750,7 +3833,13 @@ MIDFUNC(3,jff_ROL_b,(W4 d, RR4 s, RR4 i))
RORS_rrr(d, d, REG_WORK1);
MRS_CPSR(REG_WORK2);
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
#else
TST_ri(d, 1);
ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
#endif
MSR_CPSRf_r(REG_WORK2);
unlock2(d);
@ -3778,7 +3867,13 @@ MIDFUNC(3,jff_ROL_w,(W4 d, RR4 s, RR4 i))
RORS_rrr(d, d, REG_WORK1);
MRS_CPSR(REG_WORK2);
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
#else
TST_ri(d, 1);
ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
#endif
MSR_CPSRf_r(REG_WORK2);
unlock2(d);
@ -3805,7 +3900,13 @@ MIDFUNC(3,jff_ROL_l,(W4 d, RR4 s, RR4 i))
RORS_rrr(d, s, REG_WORK1);
MRS_CPSR(REG_WORK2);
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
#else
TST_ri(d, 1);
ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
#endif
MSR_CPSRf_r(REG_WORK2);
unlock2(d);
@ -3850,7 +3951,13 @@ MIDFUNC(2,jff_ROLW,(W4 d, RR4 s))
RORS_rri(d, d, (32 - 1));
MRS_CPSR(REG_WORK2);
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
#else
TST_ri(d, 1);
ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
#endif
MSR_CPSRf_r(REG_WORK2);
unlock2(d);
@ -4821,7 +4928,12 @@ MIDFUNC(3,jff_SUBX_b,(W4 d, RR1 s, RR1 v))
MRS_CPSR(REG_WORK1);
EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);
@ -4853,7 +4965,12 @@ MIDFUNC(3,jff_SUBX_w,(W4 d, RR2 s, RR2 v))
MRS_CPSR(REG_WORK1);
EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);
@ -4883,7 +5000,12 @@ MIDFUNC(3,jff_SUBX_l,(W4 d, RR4 s, RR4 v))
MRS_CPSR(REG_WORK1);
EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
#ifdef ARMV6T2
UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
#else
LSR_rri(x, REG_WORK1, 29);
AND_rri(x, x, 1);
#endif
MSR_CPSRf_r(REG_WORK1);
unlock2(x);