Merge latest TomB version as of 10 July 2016
This commit is contained in:
Chips
parent
6a8fc51848
commit
01740246dd
15 changed files with 633 additions and 124 deletions
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@ -57,12 +57,22 @@ const uae_u32 ARM_CCR_MAP[] = { 0, ARM_C_FLAG, // 1 C
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unlock2(x); \
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}
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#ifdef ARMV6T2
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#define DUPLICACTE_CARRY_FROM_REG(r) \
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if (needed_flags & FLAG_X) { \
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int x = writereg(FLAGX, 4); \
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UBFX_rrii(x, r, 29, 1); \
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unlock2(x); \
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}
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#else
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#define DUPLICACTE_CARRY_FROM_REG(r) \
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if (needed_flags & FLAG_X) { \
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int x = writereg(FLAGX, 4); \
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LSR_rri(x, r, 29); \
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AND_rri(x, x, 1); \
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unlock2(x); \
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}
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#endif
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/*
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* ADD
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@ -357,13 +367,23 @@ MIDFUNC(3,jff_ADDX_b,(W4 d, RR1 s, RR1 v))
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MSR_CPSRf_r(REG_WORK1);
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MVN_ri(REG_WORK1, 0);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK1, s, 24, 31);
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#else
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BIC_rri(REG_WORK1, REG_WORK1, 0xff000000);
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ORR_rrrLSLi(REG_WORK1, REG_WORK1, s, 24);
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#endif
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ADCS_rrrLSLi(d, REG_WORK1, v, 24);
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ASR_rri(d, d, 24);
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MRS_CPSR(REG_WORK1);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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@ -388,13 +408,24 @@ MIDFUNC(3,jff_ADDX_w,(W4 d, RR2 s, RR2 v))
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MSR_CPSRf_r(REG_WORK1);
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MVN_ri(REG_WORK1, 0);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK1, s, 16, 31);
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#else
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BIC_rri(REG_WORK1, REG_WORK1, 0xff000000);
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BIC_rri(REG_WORK1, REG_WORK1, 0x00ff0000);
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ORR_rrrLSLi(REG_WORK1, REG_WORK1, s, 16);
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#endif
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ADCS_rrrLSLi(d, REG_WORK1, v, 16);
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ASR_rri(d, d, 16);
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MRS_CPSR(REG_WORK1);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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@ -422,7 +453,12 @@ MIDFUNC(3,jff_ADDX_l,(W4 d, RR4 s, RR4 v))
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MRS_CPSR(REG_WORK1);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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@ -1144,8 +1180,15 @@ MIDFUNC(2,jff_BCHG_b_imm,(RW4 d, IMM s))
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uae_u32 v = (1 << s);
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MRS_CPSR(REG_WORK1);
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EOR_rri(d, d, v);
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#ifdef ARMV6T2
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UBFX_rrii(REG_WORK2, d, s, 1);
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BFI_rrii(REG_WORK1, REG_WORK2, 30, 30);
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#else
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LSR_rri(REG_WORK2, d, 29);
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AND_rri(REG_WORK2, REG_WORK2, 1);
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BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
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ORR_rrrLSLi(REG_WORK1, REG_WORK1, REG_WORK2, 30);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(d);
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@ -1159,8 +1202,15 @@ MIDFUNC(2,jff_BCHG_l_imm,(RW4 d, IMM s))
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uae_u32 v = (1 << s);
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MRS_CPSR(REG_WORK1);
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EOR_rri(d, d, v);
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#ifdef ARMV6T2
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UBFX_rrii(REG_WORK2, d, s, 1);
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BFI_rrii(REG_WORK1, REG_WORK2, 30, 30);
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#else
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LSR_rri(REG_WORK2, d, 29);
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AND_rri(REG_WORK2, REG_WORK2, 1);
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BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
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ORR_rrrLSLi(REG_WORK1, REG_WORK1, REG_WORK2, 30);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(d);
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@ -3278,7 +3328,12 @@ MIDFUNC(2,jff_NEGX_b,(W4 d, RR1 s))
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MRS_CPSR(REG_WORK1);
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EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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@ -3307,7 +3362,12 @@ MIDFUNC(2,jff_NEGX_w,(W4 d, RR2 s))
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MRS_CPSR(REG_WORK1);
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EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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@ -3335,7 +3395,12 @@ MIDFUNC(2,jff_NEGX_l,(W4 d, RR4 s))
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MRS_CPSR(REG_WORK1);
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EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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@ -3602,7 +3667,13 @@ MIDFUNC(3,jff_ROL_b_imm,(W4 d, RR4 s, IMM i))
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TST_rr(d, d);
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MRS_CPSR(REG_WORK2);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
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#else
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TST_ri(d, 1);
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CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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#endif
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MSR_CPSRf_r(REG_WORK2);
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} else {
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TST_rr(d, d);
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@ -3627,7 +3698,13 @@ MIDFUNC(3,jff_ROL_w_imm,(W4 d, RR4 s, IMM i))
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TST_rr(d, d);
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MRS_CPSR(REG_WORK2);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
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#else
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TST_ri(d, 1);
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CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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#endif
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MSR_CPSRf_r(REG_WORK2);
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} else {
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TST_rr(d, d);
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@ -3651,7 +3728,13 @@ MIDFUNC(3,jff_ROL_l_imm,(W4 d, RR4 s, IMM i))
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MOVS_rr(d, s);
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MRS_CPSR(REG_WORK2);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
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#else
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TST_ri(d, 1);
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CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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#endif
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MSR_CPSRf_r(REG_WORK2);
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} else {
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MOVS_rr(d, s);
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@ -3750,7 +3833,13 @@ MIDFUNC(3,jff_ROL_b,(W4 d, RR4 s, RR4 i))
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RORS_rrr(d, d, REG_WORK1);
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MRS_CPSR(REG_WORK2);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
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#else
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TST_ri(d, 1);
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ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
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CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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#endif
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MSR_CPSRf_r(REG_WORK2);
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unlock2(d);
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@ -3778,7 +3867,13 @@ MIDFUNC(3,jff_ROL_w,(W4 d, RR4 s, RR4 i))
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RORS_rrr(d, d, REG_WORK1);
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MRS_CPSR(REG_WORK2);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
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#else
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TST_ri(d, 1);
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ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
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CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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#endif
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MSR_CPSRf_r(REG_WORK2);
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unlock2(d);
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@ -3805,7 +3900,13 @@ MIDFUNC(3,jff_ROL_l,(W4 d, RR4 s, RR4 i))
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RORS_rrr(d, s, REG_WORK1);
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MRS_CPSR(REG_WORK2);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
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#else
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TST_ri(d, 1);
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ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
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CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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#endif
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MSR_CPSRf_r(REG_WORK2);
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unlock2(d);
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@ -3850,7 +3951,13 @@ MIDFUNC(2,jff_ROLW,(W4 d, RR4 s))
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RORS_rri(d, d, (32 - 1));
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MRS_CPSR(REG_WORK2);
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#ifdef ARMV6T2
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BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
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#else
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TST_ri(d, 1);
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ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
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CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
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#endif
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MSR_CPSRf_r(REG_WORK2);
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unlock2(d);
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@ -4821,7 +4928,12 @@ MIDFUNC(3,jff_SUBX_b,(W4 d, RR1 s, RR1 v))
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MRS_CPSR(REG_WORK1);
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EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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@ -4853,7 +4965,12 @@ MIDFUNC(3,jff_SUBX_w,(W4 d, RR2 s, RR2 v))
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MRS_CPSR(REG_WORK1);
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EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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@ -4883,7 +5000,12 @@ MIDFUNC(3,jff_SUBX_l,(W4 d, RR4 s, RR4 v))
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MRS_CPSR(REG_WORK1);
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EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
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AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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#ifdef ARMV6T2
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UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
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#else
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LSR_rri(x, REG_WORK1, 29);
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AND_rri(x, x, 1);
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#endif
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MSR_CPSRf_r(REG_WORK1);
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unlock2(x);
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