diff --git a/Makefile b/Makefile
index 6614cc8b..7efdfe18 100644
--- a/Makefile
+++ b/Makefile
@@ -23,14 +23,14 @@ CPPFLAGS+= -MD -MP
 #
 ifeq ($(PLATFORM),rpi3)
     CPU_FLAGS += -march=armv8-a -mtune=cortex-a53 -mfpu=neon-fp-armv8
-    CFLAGS += ${DISPMANX_FLAGS} -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL1
+    CFLAGS += ${DISPMANX_FLAGS} -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL1
     LDFLAGS += ${DISPMANX_LDFLAGS}
     HAVE_NEON = 1
     NAME  = amiberry-rpi3-sdl1-dev
 	
 else ifeq ($(PLATFORM),rpi2)
     CPU_FLAGS += -march=armv7-a -mtune=cortex-a7 -mfpu=neon-vfpv4
-    CFLAGS += ${DISPMANX_FLAGS} -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL1
+    CFLAGS += ${DISPMANX_FLAGS} -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL1
     LDFLAGS += ${DISPMANX_LDFLAGS}
     HAVE_NEON = 1
     NAME  = amiberry-rpi2-sdl1-dev
@@ -43,7 +43,7 @@ else ifeq ($(PLATFORM),rpi1)
 
 else ifeq ($(PLATFORM),android)
     CPU_FLAGS += -mfpu=neon -mfloat-abi=soft
-    DEFS += -DANDROIDSDL -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL1
+    DEFS += -DANDROIDSDL -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL1
     ANDROID = 1
     HAVE_NEON = 1
     HAVE_SDL_DISPLAY = 1
@@ -55,7 +55,7 @@ else ifeq ($(PLATFORM),android)
 else ifeq ($(PLATFORM),rpi3-sdl2-dispmanx)
 USE_SDL2 = 1
     CPU_FLAGS += -march=armv8-a -mtune=cortex-a53 -mfpu=neon-fp-armv8
-    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2 ${DISPMANX_FLAGS}
+    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2 ${DISPMANX_FLAGS}
     LDFLAGS += ${DISPMANX_LDFLAGS}
     HAVE_NEON = 1
     NAME  = amiberry-rpi3-sdl2-dispmanx-dev
@@ -63,7 +63,7 @@ USE_SDL2 = 1
 else ifeq ($(PLATFORM),rpi2-sdl2-dispmanx)
 USE_SDL2 = 1
     CPU_FLAGS += -march=armv7-a -mtune=cortex-a7 -mfpu=neon-vfpv4
-    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2 ${DISPMANX_FLAGS}
+    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2 ${DISPMANX_FLAGS}
     LDFLAGS += ${DISPMANX_LDFLAGS}
     HAVE_NEON = 1
     NAME  = amiberry-rpi2-sdl2-dispmanx-dev
@@ -81,14 +81,14 @@ USE_SDL2 = 1
 else ifeq ($(PLATFORM),rpi3-sdl2)
 USE_SDL2 = 1
     CPU_FLAGS += -march=armv8-a -mtune=cortex-a53 -mfpu=neon-fp-armv8
-    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2
+    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2
     HAVE_NEON = 1
     NAME  = amiberry-rpi3-sdl2-dev
 	
 else ifeq ($(PLATFORM),rpi2-sdl2)
 USE_SDL2 = 1
     CPU_FLAGS += -march=armv7-a -mtune=cortex-a7 -mfpu=neon-vfpv4
-    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2
+    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2
     HAVE_NEON = 1
     NAME  = amiberry-rpi2-sdl2-dev
 	
@@ -101,7 +101,7 @@ USE_SDL2 = 1
 else ifeq ($(PLATFORM),pine64)
 USE_SDL2 = 1
     CPU_FLAGS += -march=armv7-a -mfpu=vfpv3-d16
-    CFLAGS += -DARMV6T2 -D__arm__ -DUSE_SDL2
+    CFLAGS += -DARMV6T2 -D__arm__ -DARM_HAS_DIV -DUSE_SDL2
     CC = arm-linux-gnueabihf-gcc
     CXX = arm-linux-gnueabihf-g++
     NAME  = amiberry-pine64-sdl2-dev
@@ -109,7 +109,7 @@ USE_SDL2 = 1
 else ifeq ($(PLATFORM),xu4)
 USE_SDL2 = 1
     CPU_FLAGS += -march=armv7ve -mcpu=cortex-a15.cortex-a7 -mtune=cortex-a15.cortex-a7 -mfpu=neon-vfpv4
-    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2 -DMALI_GPU -DUSE_RENDER_THREAD
+    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2 -DMALI_GPU -DUSE_RENDER_THREAD
     HAVE_NEON = 1
     NAME  = amiberry-xu4-dev
     ifdef DEBUG
@@ -121,7 +121,7 @@ USE_SDL2 = 1
 else ifeq ($(PLATFORM),tinker)
 USE_SDL2 = 1
     CPU_FLAGS += -march=armv7-a -mtune=cortex-a17 -mfpu=neon-vfpv4
-    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2 -DTINKER -DUSE_RENDER_THREAD -DMALI_GPU -I/usr/local/include
+    CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2 -DTINKER -DUSE_RENDER_THREAD -DMALI_GPU -I/usr/local/include
     LDFLAGS += -L/usr/local/lib
     HAVE_NEON = 1
     NAME  = amiberry-tinker-dev
@@ -129,7 +129,7 @@ USE_SDL2 = 1
 else ifeq ($(PLATFORM),android-sdl2)
 USE_SDL2 = 1
     CPU_FLAGS += -mfpu=neon -mfloat-abi=soft
-    DEFS += -DANDROIDSDL -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2
+    DEFS += -DANDROIDSDL -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2
     ANDROID = 1
     HAVE_NEON = 1
     HAVE_SDL_DISPLAY = 1
diff --git a/src/archivers/lha/uae_lha.cpp b/src/archivers/lha/uae_lha.cpp
index c10066fb..967b923e 100644
--- a/src/archivers/lha/uae_lha.cpp
+++ b/src/archivers/lha/uae_lha.cpp
@@ -18,7 +18,7 @@ static const char *methods[] =
 	NULL
 };
 
-struct zvolume *archive_directory_lha(struct zfile *zf)
+struct zvolume *archive_directory_lha (struct zfile *zf)
 {
     struct zvolume *zv;
     struct zarchive_info zai;
@@ -26,53 +26,53 @@ struct zvolume *archive_directory_lha(struct zfile *zf)
     int i;
 
     _tzset();
-    zv = zvolume_alloc(zf, ArchiveFormatLHA, NULL, NULL);
+    zv = zvolume_alloc (zf, ArchiveFormatLHA, NULL, NULL);
     while (get_header(zf, &hdr)) {
-	struct znode *zn;
-	int method;
+		struct znode *zn;
+		int method;
 
-	for (i = 0; methods[i]; i++) {
-	    if (!strcmp(methods[i], hdr.method))
-		method = i;
-	}
-	memset(&zai, 0, sizeof zai);
-	zai.name = au (hdr.name);
-	zai.size = hdr.original_size;
-	zai.flags = hdr.attribute;
-	if (hdr.extend_type != 0) {
-		zai.tv.tv_sec = hdr.unix_last_modified_stamp -= _timezone;
-	} else {
-		struct tm t;
-		uae_u32 v = hdr.last_modified_stamp;
-
-		t.tm_sec = (v & 0x1f) * 2;
-		t.tm_min = (v >> 5) & 0x3f;
-		t.tm_hour = (v >> 11) & 0x1f;
-		t.tm_mday = (v >> 16) & 0x1f;
-		t.tm_mon = ((v >> 21) & 0xf) - 1;
-		t.tm_year = ((v >> 25) & 0x7f) + 80;
-		zai.tv.tv_sec = mktime (&t) - _timezone;
-	}
-	if (hdr.name[strlen(hdr.name) + 1] != 0)
-	    zai.comment = au (&hdr.name[strlen(hdr.name) + 1]);
-	if (method == LZHDIRS_METHOD_NUM) {
-	    zvolume_adddir_abs(zv, &zai);
-	} else {
-	  zn = zvolume_addfile_abs(zv, &zai);
-		if (zn) {
-	    zn->offset = zfile_ftell(zf);
-	    zn->packedsize = hdr.packed_size;
-	    zn->method = method;
+		for (i = 0; methods[i]; i++) {
+			if (!strcmp (methods[i], hdr.method))
+				method = i;
 		}
-	}
-	xfree (zai.name);
-	xfree (zai.comment);
-	zfile_fseek(zf, hdr.packed_size, SEEK_CUR);
+		memset (&zai, 0, sizeof zai);
+		zai.name = au (hdr.name);
+		zai.size = hdr.original_size;
+		zai.flags = hdr.attribute;
+		if (hdr.extend_type != 0) {
+			zai.tv.tv_sec = hdr.unix_last_modified_stamp -= _timezone;
+		} else {
+			struct tm t;
+			uae_u32 v = hdr.last_modified_stamp;
+
+			t.tm_sec = (v & 0x1f) * 2;
+			t.tm_min = (v >> 5) & 0x3f;
+			t.tm_hour = (v >> 11) & 0x1f;
+			t.tm_mday = (v >> 16) & 0x1f;
+			t.tm_mon = ((v >> 21) & 0xf) - 1;
+			t.tm_year = ((v >> 25) & 0x7f) + 80;
+			zai.tv.tv_sec = mktime (&t) - _timezone;
+		}
+		if (hdr.name[strlen(hdr.name) + 1] != 0)
+			zai.comment = au (&hdr.name[strlen(hdr.name) + 1]);
+		if (method == LZHDIRS_METHOD_NUM) {
+			zvolume_adddir_abs (zv, &zai);
+		} else {
+			zn = zvolume_addfile_abs (zv, &zai);
+			if (zn) {
+				zn->offset = zfile_ftell(zf);
+				zn->packedsize = hdr.packed_size;
+				zn->method = method;
+			}
+		}
+		xfree (zai.name);
+		xfree (zai.comment);
+		zfile_fseek (zf, hdr.packed_size, SEEK_CUR);
     }
     return zv;
 }
 
-struct zfile *archive_access_lha(struct znode *zn)
+struct zfile *archive_access_lha (struct znode *zn)
 {
     struct zfile *zf = zn->volume->archive;
     struct zfile *out = zfile_fopen_empty (zf, zn->name, zn->size);
@@ -95,7 +95,7 @@ struct zfile *archive_access_lha(struct znode *zn)
 	case LARC_METHOD_NUM:		/* -lzs- */
 	    lhinterface.dicbit = 11;
 	    decode(&lhinterface);
-        break;
+	break;
 	case LZHUFF1_METHOD_NUM:		/* -lh1- */
 	case LZHUFF4_METHOD_NUM:		/* -lh4- */
 	case LARC5_METHOD_NUM:			/* -lz5- */
diff --git a/src/guisan/include/guisan/exception.hpp b/src/guisan/include/guisan/exception.hpp
index 243d8f1d..ef4f8b26 100644
--- a/src/guisan/include/guisan/exception.hpp
+++ b/src/guisan/include/guisan/exception.hpp
@@ -62,8 +62,8 @@
 #include "guisan/platform.hpp"
 
 
-#ifdef _MSC_VER
-#if _MSC_VER <= 1200
+#ifdef _MSC_VER_
+#if _MSC_VER_ <= 1200
 #define __FUNCTION__ "?"
 #endif
 #endif
diff --git a/src/include/fpp.h b/src/include/fpp.h
index f12f8e66..bcf5b10e 100644
--- a/src/include/fpp.h
+++ b/src/include/fpp.h
@@ -20,5 +20,3 @@
 #if defined(CPU_i386) || defined(CPU_x86_64)
 extern void init_fpucw_x87(void);
 #endif
-
-extern void fpsr_set_exception(uae_u32 exception);
\ No newline at end of file
diff --git a/src/include/uae/string.h b/src/include/uae/string.h
index 26680d3b..6ec9ddf3 100644
--- a/src/include/uae/string.h
+++ b/src/include/uae/string.h
@@ -7,6 +7,17 @@
 #include "uae/types.h"
 #include <string.h>
 
+#ifdef _WIN32_
+/* Make sure the real _tcs* functions are already declared before we
+ * re-define them below. */
+#include <tchar.h>
+#include <wchar.h>
+#include <stdlib.h>
+#endif
+
+#ifdef _WIN32_
+/* Using the real _tcs* functions */
+#else
 #define _istdigit isdigit
 #define _istspace isspace
 #define _istupper isupper
@@ -42,6 +53,7 @@
 #define _tstol atol
 #define _vsnprintf vsnprintf
 #define _vsntprintf vsnprintf
+#endif
 
 static size_t uae_tcslcpy(char *dst, const TCHAR *src, size_t size)
 {
diff --git a/src/include/uae/types.h b/src/include/uae/types.h
index 9d1fc168..a063f09b 100644
--- a/src/include/uae/types.h
+++ b/src/include/uae/types.h
@@ -53,8 +53,17 @@ typedef uae_u32 uaecptr;
 
 typedef char uae_char;
 
+#ifdef _WIN32_
+#include <tchar.h>
+#ifdef UNICODE
+#define SIZEOF_TCHAR 2
+#else
+#define SIZEOF_TCHAR 1
+#endif
+#else
 typedef char TCHAR;
 #define SIZEOF_TCHAR 1
+#endif
 
 #ifndef _T
 #if SIZEOF_TCHAR == 1
diff --git a/src/jit/codegen_arm.h b/src/jit/codegen_arm.h
index b3e79018..7a54d4f3 100644
--- a/src/jit/codegen_arm.h
+++ b/src/jit/codegen_arm.h
@@ -1341,6 +1341,12 @@ enum {
 #define CC_SSAT_rir(cc,Rd,i,Rn)			_W(((cc) << 28) | (0x6a << 20) | (i << 16) | (Rd << 12) | (0x1 << 4) | (Rn))
 #define SSAT_rir(Rd,i,Rn)						CC_SSAT_rir(NATIVE_CC_AL,Rd,i,Rn)
 
+#define CC_SDIV_rrr(cc,Rd,Rn,Rm)		_W(((cc) << 28) | (0x7 << 24) | (0x1 << 20) | (Rd << 16) | (0xf << 12) | (Rm << 8) | (0x1 << 4) | (Rn))
+#define SDIV_rrr(Rd,Rn,Rm)					CC_SDIV_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_UDIV_rrr(cc,Rd,Rn,Rm)		_W(((cc) << 28) | (0x7 << 24) | (0x3 << 20) | (Rd << 16) | (0xf << 12) | (Rm << 8) | (0x1 << 4) | (Rn))
+#define UDIV_rrr(Rd,Rn,Rm)					CC_UDIV_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+
 //#endif
 
 // Floatingpoint
diff --git a/src/jit/compemu.cpp b/src/jit/compemu.cpp
index 83d7baef..28ba27e0 100644
--- a/src/jit/compemu.cpp
+++ b/src/jit/compemu.cpp
@@ -15295,6 +15295,415 @@ uae_u32 REGPARAM2 op_4c3c_0_comp_ff(uae_u32 opcode)
 }}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
 return 0;
 }
+/* DIVL.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_4c40_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dst=dstreg;
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4c50_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=dodgy?scratchie++:dstreg+8;
+	if (dodgy) 
+		mov_l_rr(dsta,dstreg+8);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4c58_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=scratchie++;
+	mov_l_rr(dsta,dstreg+8);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	arm_ADD_l_ri8(dstreg+8,4);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_4c60_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{{	int dsta=dodgy?scratchie++:dstreg+8;
+	arm_SUB_l_ri8(dstreg+8,4);
+	if (dodgy) 
+	mov_l_rr(dsta,8+dstreg);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4c68_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=scratchie++;
+	mov_l_rr(dsta,8+dstreg);
+	lea_l_brr(dsta,dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4c70_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=scratchie++;
+	calc_disp_ea_020(dstreg+8,comp_get_iword((m68k_pc_offset+=2)-2),dsta,scratchie);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4c78_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta = scratchie++;
+	mov_l_ri(dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4c79_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta = scratchie++;
+	mov_l_ri(dsta,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4c7a_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_s32 dstreg = 2;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=scratchie++;
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	mov_l_ri(dsta,address+PC16off);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4c7b_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_s32 dstreg = 3;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int pctmp=scratchie++;
+	int dsta=scratchie++;
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+{	mov_l_ri(pctmp,address);
+	calc_disp_ea_020(pctmp,comp_get_iword((m68k_pc_offset+=2)-2),dsta,scratchie);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,#<data>.L */
+uae_u32 REGPARAM2 op_4c7c_0_comp_ff(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dst = scratchie++;
+	mov_l_ri(dst,comp_get_ilong((m68k_pc_offset+=4)-4));
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else { 
+	   if (extra & 0x0800) { 
+	     jff_DIVLS32(r2,dst,r3);
+		} else { 
+			  jff_DIVLU32(r2,dst,r3);
+		} 
+	 }
+	 live_flags();
+}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
 /* MVMEL.W #<data>.W,(An) */
 uae_u32 REGPARAM2 op_4c90_0_comp_ff(uae_u32 opcode)
 {
@@ -31240,6 +31649,29 @@ uae_u32 REGPARAM2 op_e108_0_comp_ff(uae_u32 opcode)
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e110_0_comp_ff(uae_u32 opcode)
+{
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+{	int cnt = scratchie++;
+	mov_l_ri(cnt,srcreg);
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 make_flags_live();
+	 jff_ROXL_b(tmp,data,cnt);
+	 live_flags();
+	if(dstreg!=tmp)
+		mov_b_rr(dstreg,tmp);
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROLQ.B #<data>,Dn */
 uae_u32 REGPARAM2 op_e118_0_comp_ff(uae_u32 opcode)
 {
@@ -31314,6 +31746,32 @@ if ((uae_u32)srcreg==(uae_u32)dstreg) {
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e130_0_comp_ff(uae_u32 opcode)
+{
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+if ((uae_u32)srcreg==(uae_u32)dstreg) {
+  FAIL(1);
+  return 0;
+} 
+{	 dont_care_flags();
+{	int cnt=srcreg;
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 make_flags_live();
+	 jff_ROXL_b(tmp,data,cnt);
+	 live_flags();
+	if(dstreg!=tmp)
+		mov_b_rr(dstreg,tmp);
+}}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROL.B Dn,Dn */
 uae_u32 REGPARAM2 op_e138_0_comp_ff(uae_u32 opcode)
 {
@@ -31385,6 +31843,29 @@ uae_u32 REGPARAM2 op_e148_0_comp_ff(uae_u32 opcode)
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e150_0_comp_ff(uae_u32 opcode)
+{
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+{	int cnt = scratchie++;
+	mov_l_ri(cnt,srcreg);
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 make_flags_live();
+	 jff_ROXL_w(tmp,data,cnt);
+	 live_flags();
+	if(dstreg!=tmp)
+		mov_w_rr(dstreg,tmp);
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROLQ.W #<data>,Dn */
 uae_u32 REGPARAM2 op_e158_0_comp_ff(uae_u32 opcode)
 {
@@ -31459,6 +31940,32 @@ if ((uae_u32)srcreg==(uae_u32)dstreg) {
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e170_0_comp_ff(uae_u32 opcode)
+{
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+if ((uae_u32)srcreg==(uae_u32)dstreg) {
+  FAIL(1);
+  return 0;
+} 
+{	 dont_care_flags();
+{	int cnt=srcreg;
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 make_flags_live();
+	 jff_ROXL_w(tmp,data,cnt);
+	 live_flags();
+	if(dstreg!=tmp)
+		mov_w_rr(dstreg,tmp);
+}}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROL.W Dn,Dn */
 uae_u32 REGPARAM2 op_e178_0_comp_ff(uae_u32 opcode)
 {
@@ -31530,6 +32037,29 @@ uae_u32 REGPARAM2 op_e188_0_comp_ff(uae_u32 opcode)
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e190_0_comp_ff(uae_u32 opcode)
+{
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+{	int cnt = scratchie++;
+	mov_l_ri(cnt,srcreg);
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 make_flags_live();
+	 jff_ROXL_l(tmp,data,cnt);
+	 live_flags();
+	if(dstreg!=tmp)
+		mov_l_rr(dstreg,tmp);
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROLQ.L #<data>,Dn */
 uae_u32 REGPARAM2 op_e198_0_comp_ff(uae_u32 opcode)
 {
@@ -31604,6 +32134,32 @@ if ((uae_u32)srcreg==(uae_u32)dstreg) {
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1b0_0_comp_ff(uae_u32 opcode)
+{
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+if ((uae_u32)srcreg==(uae_u32)dstreg) {
+  FAIL(1);
+  return 0;
+} 
+{	 dont_care_flags();
+{	int cnt=srcreg;
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 make_flags_live();
+	 jff_ROXL_l(tmp,data,cnt);
+	 live_flags();
+	if(dstreg!=tmp)
+		mov_l_rr(dstreg,tmp);
+}}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROL.L Dn,Dn */
 uae_u32 REGPARAM2 op_e1b8_0_comp_ff(uae_u32 opcode)
 {
@@ -47039,6 +47595,404 @@ uae_u32 REGPARAM2 op_4c3c_0_comp_nf(uae_u32 opcode)
 }}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
 return 0;
 }
+/* DIVL.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_4c40_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dst=dstreg;
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4c50_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=dodgy?scratchie++:dstreg+8;
+	if (dodgy) 
+		mov_l_rr(dsta,dstreg+8);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4c58_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=scratchie++;
+	mov_l_rr(dsta,dstreg+8);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	arm_ADD_l_ri8(dstreg+8,4);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_4c60_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{{	int dsta=dodgy?scratchie++:dstreg+8;
+	arm_SUB_l_ri8(dstreg+8,4);
+	if (dodgy) 
+	mov_l_rr(dsta,8+dstreg);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4c68_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=scratchie++;
+	mov_l_rr(dsta,8+dstreg);
+	lea_l_brr(dsta,dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4c70_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=scratchie++;
+	calc_disp_ea_020(dstreg+8,comp_get_iword((m68k_pc_offset+=2)-2),dsta,scratchie);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4c78_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta = scratchie++;
+	mov_l_ri(dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4c79_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta = scratchie++;
+	mov_l_ri(dsta,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4c7a_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_s32 dstreg = 2;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dsta=scratchie++;
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	mov_l_ri(dsta,address+PC16off);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4c7b_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_s32 dstreg = 3;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int pctmp=scratchie++;
+	int dsta=scratchie++;
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+{	mov_l_ri(pctmp,address);
+	calc_disp_ea_020(pctmp,comp_get_iword((m68k_pc_offset+=2)-2),dsta,scratchie);
+{	int dst=scratchie++;
+	readlong(dsta,dst,scratchie);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+/* DIVL.L #<data>.W,#<data>.L */
+uae_u32 REGPARAM2 op_4c7c_0_comp_nf(uae_u32 opcode)
+{
+#ifndef ARMV6T2
+  FAIL(1);
+  return 0;
+#else
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+{	int dst = scratchie++;
+	mov_l_ri(dst,comp_get_ilong((m68k_pc_offset+=4)-4));
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) { 
+	     jnf_DIVLS32(r2,dst,r3);
+		} else { 
+			  jnf_DIVLU32(r2,dst,r3);
+		} 
+	 }
+}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
 /* MVMEL.W #<data>.W,(An) */
 uae_u32 REGPARAM2 op_4c90_0_comp_nf(uae_u32 opcode)
 {
@@ -62286,6 +63240,27 @@ uae_u32 REGPARAM2 op_e108_0_comp_nf(uae_u32 opcode)
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e110_0_comp_nf(uae_u32 opcode)
+{
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+{	int cnt = scratchie++;
+	mov_l_ri(cnt,srcreg);
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 jnf_ROXL_b(tmp,data,cnt);
+	if(dstreg!=tmp)
+		mov_b_rr(dstreg,tmp);
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROLQ.B #<data>,Dn */
 uae_u32 REGPARAM2 op_e118_0_comp_nf(uae_u32 opcode)
 {
@@ -62355,6 +63330,30 @@ if ((uae_u32)srcreg==(uae_u32)dstreg) {
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e130_0_comp_nf(uae_u32 opcode)
+{
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+if ((uae_u32)srcreg==(uae_u32)dstreg) {
+  FAIL(1);
+  return 0;
+} 
+{	 dont_care_flags();
+{	int cnt=srcreg;
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 jnf_ROXL_b(tmp,data,cnt);
+	if(dstreg!=tmp)
+		mov_b_rr(dstreg,tmp);
+}}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROL.B Dn,Dn */
 uae_u32 REGPARAM2 op_e138_0_comp_nf(uae_u32 opcode)
 {
@@ -62421,6 +63420,27 @@ uae_u32 REGPARAM2 op_e148_0_comp_nf(uae_u32 opcode)
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e150_0_comp_nf(uae_u32 opcode)
+{
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+{	int cnt = scratchie++;
+	mov_l_ri(cnt,srcreg);
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 jnf_ROXL_w(tmp,data,cnt);
+	if(dstreg!=tmp)
+		mov_w_rr(dstreg,tmp);
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROLQ.W #<data>,Dn */
 uae_u32 REGPARAM2 op_e158_0_comp_nf(uae_u32 opcode)
 {
@@ -62490,6 +63510,30 @@ if ((uae_u32)srcreg==(uae_u32)dstreg) {
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e170_0_comp_nf(uae_u32 opcode)
+{
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+if ((uae_u32)srcreg==(uae_u32)dstreg) {
+  FAIL(1);
+  return 0;
+} 
+{	 dont_care_flags();
+{	int cnt=srcreg;
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 jnf_ROXL_w(tmp,data,cnt);
+	if(dstreg!=tmp)
+		mov_w_rr(dstreg,tmp);
+}}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROL.W Dn,Dn */
 uae_u32 REGPARAM2 op_e178_0_comp_nf(uae_u32 opcode)
 {
@@ -62556,6 +63600,27 @@ uae_u32 REGPARAM2 op_e188_0_comp_nf(uae_u32 opcode)
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e190_0_comp_nf(uae_u32 opcode)
+{
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+	 dont_care_flags();
+{	int cnt = scratchie++;
+	mov_l_ri(cnt,srcreg);
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 jnf_ROXL_l(tmp,data,cnt);
+	if(dstreg!=tmp)
+		mov_l_rr(dstreg,tmp);
+}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROLQ.L #<data>,Dn */
 uae_u32 REGPARAM2 op_e198_0_comp_nf(uae_u32 opcode)
 {
@@ -62625,6 +63690,30 @@ if ((uae_u32)srcreg==(uae_u32)dstreg) {
 	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
 return 0;
 }
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1b0_0_comp_nf(uae_u32 opcode)
+{
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 dodgy=0;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+{	uae_u8 scratchie=S1;
+if ((uae_u32)srcreg==(uae_u32)dstreg) {
+  FAIL(1);
+  return 0;
+} 
+{	 dont_care_flags();
+{	int cnt=srcreg;
+{	int data=dstreg;
+{	 int tmp=scratchie++;
+	 jnf_ROXL_l(tmp,data,cnt);
+	if(dstreg!=tmp)
+		mov_l_rr(dstreg,tmp);
+}}}}}	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;
+return 0;
+}
 /* ROL.L Dn,Dn */
 uae_u32 REGPARAM2 op_e1b8_0_comp_nf(uae_u32 opcode)
 {
diff --git a/src/jit/compemu_midfunc_arm2.cpp b/src/jit/compemu_midfunc_arm2.cpp
index bf22f53c..98309e3c 100644
--- a/src/jit/compemu_midfunc_arm2.cpp
+++ b/src/jit/compemu_midfunc_arm2.cpp
@@ -1860,7 +1860,7 @@ MENDFUNC(2,jff_DBCC,(RR2 d, IMM cc))
   
   UNSIGNED16_REG_2_REG(REG_WORK3, s2);
   TST_rr(REG_WORK3, REG_WORK3);
-  BNE_i(6);     // src is not 0
+  BNE_i(4);     // src is not 0
 
   // Signal exception 5
   MOV_ri(REG_WORK1, 5);
@@ -1872,10 +1872,12 @@ MENDFUNC(2,jff_DBCC,(RR2 d, IMM cc))
   LDR_rRI(REG_WORK2, RPC_INDEX, offs);
 #endif
   STR_rR(REG_WORK1, REG_WORK2);
+#ifdef ARM_HAS_DIV
+  B_i(5);        // end_of_op
   
-  // simplified flag handling for div0: set Z and V (for signed DIV: Z only)
-  MOV_ri(REG_WORK1, ARM_Z_FLAG | ARM_V_FLAG);
-  MSR_CPSRf_r(REG_WORK1);
+	// src is not 0  
+	UDIV_rrr(REG_WORK1, s1, REG_WORK3);
+#else
   B_i(11);       // end_of_op
 
 // src is not 0  
@@ -1886,11 +1888,12 @@ MENDFUNC(2,jff_DBCC,(RR2 d, IMM cc))
 	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
 	VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
 	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
   
   LSRS_rri(REG_WORK2, REG_WORK1, 16); // if result of this is not 0, DIVU overflows -> no result
   BNE_i(2);
   
-  // Here we have to calc reminder
+  // Here we have to calc remainder
   MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
   SUB_rrr(REG_WORK2, s1, REG_WORK2);
   PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
@@ -1926,6 +1929,12 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
   // simplified flag handling for div0: set Z and V (for signed DIV: Z only)
   MOV_ri(REG_WORK1, ARM_Z_FLAG | ARM_V_FLAG);
   MSR_CPSRf_r(REG_WORK1);
+#ifdef ARM_HAS_DIV
+  B_i(12);        // end_of_op
+
+	// src is not 0  
+	UDIV_rrr(REG_WORK1, s1, REG_WORK3);
+#else
   B_i(18);       // end_of_op
 
 // src is not 0  
@@ -1936,6 +1945,7 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
 	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
 	VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
 	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
   
   LSRS_rri(REG_WORK2, REG_WORK1, 16); // if result of this is not 0, DIVU overflows
   BEQ_i(2);
@@ -1944,7 +1954,7 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
 	MSR_CPSRf_r(REG_WORK1);
   B_i(6);
   
-  // Here we have to calc flags and reminder
+  // Here we have to calc flags and remainder
   LSLS_rri(REG_WORK2, REG_WORK1, 16);  // N and Z ok
 	MRS_CPSR(REG_WORK2);
 	BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
@@ -1979,7 +1989,7 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
   
   SIGNED16_REG_2_REG(REG_WORK3, s2);
   TST_rr(REG_WORK3, REG_WORK3);
-  BNE_i(6);     // src is not 0
+  BNE_i(4);     // src is not 0
 
   // Signal exception 5
   MOV_ri(REG_WORK1, 5);
@@ -1991,10 +2001,12 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
   LDR_rRI(REG_WORK2, RPC_INDEX, offs);
 #endif
   STR_rR(REG_WORK1, REG_WORK2);
+#ifdef ARM_HAS_DIV
+  B_i(12);        // end_of_op
   
-  // simplified flag handling for div0: set Z and V (for signed DIV: Z only)
-  MOV_ri(REG_WORK1, ARM_Z_FLAG);
-  MSR_CPSRf_r(REG_WORK1);
+	// src is not 0  
+	SDIV_rrr(REG_WORK1, s1, REG_WORK3);
+#else
   B_i(18);       // end_of_op
 
 // src is not 0  
@@ -2005,6 +2017,7 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
 	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
 	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
 	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
   
   // check for overflow
   MVN_ri(REG_WORK2, 0);
@@ -2014,7 +2027,7 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
 	CMP_rr(REG_WORK3, REG_WORK2);
 	BNE_i(5);															// overflow -> end_of_op
 	
-  // Here we have to calc reminder
+  // Here we have to calc remainder
   SIGNED16_REG_2_REG(REG_WORK3, s2);
   MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
 	SUB_rrr(REG_WORK2, s1, REG_WORK2);		// REG_WORK2 contains remainder
@@ -2055,6 +2068,12 @@ MIDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
   // simplified flag handling for div0: set Z and V (for signed DIV: Z only)
   MOV_ri(REG_WORK1, ARM_Z_FLAG);
   MSR_CPSRf_r(REG_WORK1);
+#ifdef ARM_HAS_DIV
+  B_i(19);        // end_of_op
+
+	// src is not 0  
+	SDIV_rrr(REG_WORK1, s1, REG_WORK3);
+#else
   B_i(25);       // end_of_op
 
 // src is not 0  
@@ -2065,6 +2084,7 @@ MIDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
 	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
 	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
 	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
 
   // check for overflow
   MVN_ri(REG_WORK2, 0);
@@ -2103,6 +2123,201 @@ MIDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
 }
 MENDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
 
+MIDFUNC(3,jnf_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+{
+  s1 = readreg(s1, 4);
+  d = rmw(d, 4, 4);
+  rem = writereg(rem, 4);
+
+  TST_rr(s1, s1);
+  BNE_i(4);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
+  MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
+  STR_rR(REG_WORK1, REG_WORK2);
+#ifdef ARM_HAS_DIV
+	B_i(3);        // end_of_op
+
+	// src is not 0  
+	UDIV_rrr(REG_WORK1, d, s1);
+#else
+	B_i(9);       // end_of_op
+	
+	// src is not 0  
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
+	VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // Here we have to calc remainder
+  MUL_rrr(REG_WORK2, s1, REG_WORK1);
+  SUB_rrr(rem, d, REG_WORK2);
+  MOV_rr(d, REG_WORK1);
+
+// end_of_op
+	
+  unlock2(rem);
+  unlock2(d);
+  unlock2(s1);
+}
+MENDFUNC(3,jnf_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jff_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+{
+  s1 = readreg(s1, 4);
+  d = rmw(d, 4, 4);
+  rem = writereg(rem, 4);
+
+  TST_rr(s1, s1);
+  BNE_i(6);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
+  MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
+  STR_rR(REG_WORK1, REG_WORK2);
+  
+  // simplified flag handling for div0: set Z and V (for signed DIV: Z only)
+  MOV_ri(REG_WORK1, ARM_Z_FLAG);
+  MSR_CPSRf_r(REG_WORK1);
+#ifdef ARM_HAS_DIV
+	B_i(7);        // end_of_op
+
+	// src is not 0  
+	UDIV_rrr(REG_WORK1, d, s1);
+#else
+	B_i(13);       // end_of_op
+	
+	// src is not 0  
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
+	VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // Here we have to calc flags and remainder
+  TST_rr(REG_WORK1, REG_WORK1);
+	MRS_CPSR(REG_WORK2);
+	BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
+	MSR_CPSRf_r(REG_WORK2);
+  
+  MUL_rrr(REG_WORK2, s1, REG_WORK1);
+  SUB_rrr(rem, d, REG_WORK2);
+  MOV_rr(d, REG_WORK1);
+
+// end_of_op
+	
+  unlock2(rem);
+  unlock2(d);
+  unlock2(s1);
+}
+MENDFUNC(3,jff_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jnf_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+{
+  s1 = readreg(s1, 4);
+  d = rmw(d, 4, 4);
+  rem = writereg(rem, 4);
+
+  TST_rr(s1, s1);
+  BNE_i(4);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
+  MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
+  STR_rR(REG_WORK1, REG_WORK2);
+#ifdef ARM_HAS_DIV
+	B_i(5);        // end_of_op
+
+	// src is not 0  
+	SDIV_rrr(REG_WORK1, d, s1);
+#else
+	B_i(11);       // end_of_op
+	
+	// src is not 0  
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
+	VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // Here we have to calc remainder
+  MUL_rrr(REG_WORK2, s1, REG_WORK1);
+  SUB_rrr(rem, d, REG_WORK2);
+
+	EORS_rrr(REG_WORK3, rem, d);	// If sign of remainder and first operand differs, change sign of remainder
+	CC_RSB_rri(NATIVE_CC_MI, rem, rem, 0);
+  MOV_rr(d, REG_WORK1);
+
+// end_of_op
+	
+  unlock2(rem);
+  unlock2(d);
+  unlock2(s1);
+}
+MENDFUNC(3,jnf_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jff_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+{
+  s1 = readreg(s1, 4);
+  d = rmw(d, 4, 4);
+  rem = writereg(rem, 4);
+
+  TST_rr(s1, s1);
+  BNE_i(4);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
+  MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
+  STR_rR(REG_WORK1, REG_WORK2);
+#ifdef ARM_HAS_DIV
+	B_i(3);        // end_of_op
+
+	// src is not 0  
+	SDIV_rrr(REG_WORK1, d, s1);
+#else
+	B_i(9);       // end_of_op
+	
+	// src is not 0  
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
+	VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // Here we have to calc remainder
+  MUL_rrr(REG_WORK2, s1, REG_WORK1);
+  SUB_rrr(rem, d, REG_WORK2);
+
+	EORS_rrr(REG_WORK3, rem, d);	// If sign of remainder and first operand differs, change sign of remainder
+	CC_RSB_rri(NATIVE_CC_MI, rem, rem, 0);
+  MOV_rr(d, REG_WORK1);
+
+// end_of_op
+	
+  unlock2(rem);
+  unlock2(d);
+  unlock2(s1);
+}
+MENDFUNC(3,jff_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+
 /*
  * EOR
  * Operand Syntax: 	Dn, <ea>
@@ -4159,63 +4374,263 @@ MENDFUNC(2,jff_ROLW,(W4 d, RR4 s))
  * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
  *
  */
-MIDFUNC(3,jnf_ROXL_b_imm,(W4 d, RR4 s, IMM i))
-{
-}
-MENDFUNC(3,jnf_ROXL_b_imm,(W4 d, RR4 s, IMM i))
-
-MIDFUNC(3,jnf_ROXL_w_imm,(W4 d, RR4 s, IMM i))
-{
-}
-MENDFUNC(3,jnf_ROXL_w_imm,(W4 d, RR4 s, IMM i))
-
-MIDFUNC(3,jnf_ROXL_l_imm,(W4 d, RR4 s, IMM i))
-{
-}
-MENDFUNC(3,jnf_ROXL_l_imm,(W4 d, RR4 s, IMM i))
-
-MIDFUNC(3,jff_ROXL_b_imm,(W4 d, RR4 s, IMM i))
-{
-}
-MENDFUNC(3,jff_ROXL_b_imm,(W4 d, RR4 s, IMM i))
-
-MIDFUNC(3,jff_ROXL_w_imm,(W4 d, RR4 s, IMM i))
-{
-}
-MENDFUNC(3,jff_ROXL_w_imm,(W4 d, RR4 s, IMM i))
-
-MIDFUNC(3,jff_ROXL_l_imm,(W4 d, RR4 s, IMM i)) 
-{
-}
-MENDFUNC(3,jff_ROXL_l_imm,(W4 d, RR4 s, IMM i))
-
 MIDFUNC(3,jnf_ROXL_b,(W4 d, RR4 s, RR4 i))
 {
+	i = readreg(i, 4);
+	s = readreg(s, 4);
+  int x = readreg(FLAGX, 4);
+	d = writereg(d, 4);
+
+	clobber_flags();
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 35);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
+	CMP_ri(REG_WORK1, 17);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
+	CMP_ri(REG_WORK1, 8);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
+	TST_rr(REG_WORK1, REG_WORK1);
+	CC_MOV_rr(NATIVE_CC_EQ, d, s);
+	BEQ_i(7);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 8);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+	
+	SUB_rri(REG_WORK3, REG_WORK1, 1);	
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	RSB_rri(REG_WORK3, REG_WORK1, 9);
+	UNSIGNED8_REG_2_REG(REG_WORK1, s);
+	ORR_rrrLSRr(d, REG_WORK2, REG_WORK1, REG_WORK3);
+	
+// end of op
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(s);
+	unlock2(i);
 }
 MENDFUNC(3,jnf_ROXL_b,(W4 d, RR4 s, RR4 i))
 
 MIDFUNC(3,jnf_ROXL_w,(W4 d, RR4 s, RR4 i))
 {
+	i = readreg(i, 4);
+	s = readreg(s, 4);
+  int x = readreg(FLAGX, 4);
+	d = writereg(d, 4);
+
+	clobber_flags();
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 33);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
+	CMP_ri(REG_WORK1, 16);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
+	TST_rr(REG_WORK1, REG_WORK1);
+	CC_MOV_rr(NATIVE_CC_EQ, d, s);
+	BEQ_i(7);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 16);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+	
+	SUB_rri(REG_WORK3, REG_WORK1, 1);	
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	RSB_rri(REG_WORK3, REG_WORK1, 17);
+	UNSIGNED16_REG_2_REG(REG_WORK1, s);
+	ORR_rrrLSRr(d, REG_WORK2, REG_WORK1, REG_WORK3);
+	
+// end of op
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(s);
+	unlock2(i);
 }
 MENDFUNC(3,jnf_ROXL_w,(W4 d, RR4 s, RR4 i))
 
 MIDFUNC(3,jnf_ROXL_l,(W4 d, RR4 s, RR4 i))
 {
+	i = readreg(i, 4);
+	s = readreg(s, 4);
+  int x = readreg(FLAGX, 4);
+	d = writereg(d, 4);
+
+	clobber_flags();
+	
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 32);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
+	TST_rr(REG_WORK1, REG_WORK1);
+	CC_MOV_rr(NATIVE_CC_EQ, d, s);
+	BEQ_i(6);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 32);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+	
+	SUB_rri(REG_WORK3, REG_WORK1, 1);	
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	RSB_rri(REG_WORK3, REG_WORK1, 33);
+	ORR_rrrLSRr(d, REG_WORK2, s, REG_WORK3);
+	
+// end of op
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(s);
+	unlock2(i);
 }
 MENDFUNC(3,jnf_ROXL_l,(W4 d, RR4 s, RR4 i))
 
 MIDFUNC(3,jff_ROXL_b,(W4 d, RR4 s, RR4 i))
 {
+	i = readreg(i, 4);
+	s = readreg(s, 4);
+  int x = rmw(FLAGX, 4, 4);
+	d = writereg(d, 4);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 35);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
+	CMP_ri(REG_WORK1, 17);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
+	CMP_ri(REG_WORK1, 8);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(3);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	MOVS_rrLSLi(d, s, 24);
+	LSR_rri(d, d, 24);
+	B_i(12);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 8);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+	
+	SUB_rri(REG_WORK3, REG_WORK1, 1);	
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	MSR_CPSRf_i(0);
+	RSB_rri(REG_WORK3, REG_WORK1, 9);
+	UNSIGNED8_REG_2_REG(REG_WORK1, s);
+	ORRS_rrrLSRr(d, REG_WORK2, REG_WORK1, REG_WORK3); // this LSR places correct bit in carry
+	
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+	// Calc N and Z
+	BFI_rrii(d, x, 8, 8); // Make sure to set carry (last bit shifted out)
+	LSLS_rri(REG_WORK1, d, 24);
+	
+// end of op
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(s);
+	unlock2(i);
 }
 MENDFUNC(3,jff_ROXL_b,(W4 d, RR4 s, RR4 i))
 
 MIDFUNC(3,jff_ROXL_w,(W4 d, RR4 s, RR4 i))
 {
+	i = readreg(i, 4);
+	s = readreg(s, 4);
+  int x = rmw(FLAGX, 4, 4);
+	d = writereg(d, 4);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 33);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
+	CMP_ri(REG_WORK1, 16);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(3);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	MOVS_rrLSLi(d, s, 16);
+	LSR_rri(d, d, 16);
+	B_i(12);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 16);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+	
+	SUB_rri(REG_WORK3, REG_WORK1, 1);	
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	MSR_CPSRf_i(0);
+	RSB_rri(REG_WORK3, REG_WORK1, 17);
+	UNSIGNED16_REG_2_REG(REG_WORK1, s);
+	ORRS_rrrLSRr(d, REG_WORK2, REG_WORK1, REG_WORK3); // this LSR places correct bit in carry
+	
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+	// Calc N and Z
+	BFI_rrii(d, x, 16, 16); // Make sure to set carry (last bit shifted out)
+	LSLS_rri(REG_WORK1, d, 16);
+	
+// end of op
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(s);
+	unlock2(i);
 }
 MENDFUNC(3,jff_ROXL_w,(W4 d, RR4 s, RR4 i))
 
 MIDFUNC(3,jff_ROXL_l,(W4 d, RR4 s, RR4 i))
 {
+	i = readreg(i, 4);
+	s = readreg(s, 4);
+  int x = rmw(FLAGX, 4, 4);
+	d = writereg(d, 4);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 32);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(2);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	MOVS_rr(d, s);
+	B_i(9);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 32);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+	
+	SUB_rri(REG_WORK3, REG_WORK1, 1);	
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	MSR_CPSRf_i(0);
+	RSB_rri(REG_WORK3, REG_WORK1, 33);
+	ORRS_rrrLSRr(d, REG_WORK2, s, REG_WORK3); // this LSR places correct bit in carry
+	
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+// end of op
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(s);
+	unlock2(i);
 }
 MENDFUNC(3,jff_ROXL_l,(W4 d, RR4 s, RR4 i))
 
@@ -4266,8 +4681,7 @@ MIDFUNC(2,jff_ROXLW,(W4 d, RR4 s))
 	LSL_rri(d, s, 1);
 	ADC_rri(d, d, 0);
 	MSR_CPSRf_i(0);
-	LSLS_rri(d, d, 15);
-	LSR_rri(d, d, 16);
+	LSLS_rri(REG_WORK1, d, 16);
 
   // Duplicate carry
 	MOV_ri(x, 1);
diff --git a/src/jit/compemu_midfunc_arm2.h b/src/jit/compemu_midfunc_arm2.h
index 333db46e..45abf724 100644
--- a/src/jit/compemu_midfunc_arm2.h
+++ b/src/jit/compemu_midfunc_arm2.h
@@ -165,6 +165,12 @@ DECLARE_MIDFUNC(jff_DIVU(W4 d, RR4 s1, RR4 s2));
 DECLARE_MIDFUNC(jnf_DIVS(W4 d, RR4 s1, RR4 s2));
 DECLARE_MIDFUNC(jff_DIVS(W4 d, RR4 s1, RR4 s2));
 
+// DIVL
+DECLARE_MIDFUNC(jnf_DIVLU32(RW4 d, RR4 s1, W4 rem));
+DECLARE_MIDFUNC(jff_DIVLU32(RW4 d, RR4 s1, W4 rem));
+DECLARE_MIDFUNC(jnf_DIVLS32(RW4 d, RR4 s1, W4 rem));
+DECLARE_MIDFUNC(jff_DIVLS32(RW4 d, RR4 s1, W4 rem));
+
 // EOR
 DECLARE_MIDFUNC(jnf_EOR(W4 d, RR4 s, RR4 v));
 DECLARE_MIDFUNC(jff_EOR_b(W4 d, RR1 s, RR1 v));
diff --git a/src/jit/compstbl.cpp b/src/jit/compstbl.cpp
index 72cef950..4580e2c2 100644
--- a/src/jit/compstbl.cpp
+++ b/src/jit/compstbl.cpp
@@ -864,17 +864,17 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
 { op_4c3a_0_comp_ff, 0x00000002, 19514 }, /* MULL */
 { op_4c3b_0_comp_ff, 0x00000002, 19515 }, /* MULL */
 { op_4c3c_0_comp_ff, 0x00000002, 19516 }, /* MULL */
-{ NULL, 0x00000001, 19520 }, /* DIVL */
-{ NULL, 0x00000001, 19536 }, /* DIVL */
-{ NULL, 0x00000001, 19544 }, /* DIVL */
-{ NULL, 0x00000001, 19552 }, /* DIVL */
-{ NULL, 0x00000001, 19560 }, /* DIVL */
-{ NULL, 0x00000001, 19568 }, /* DIVL */
-{ NULL, 0x00000001, 19576 }, /* DIVL */
-{ NULL, 0x00000001, 19577 }, /* DIVL */
-{ NULL, 0x00000001, 19578 }, /* DIVL */
-{ NULL, 0x00000001, 19579 }, /* DIVL */
-{ NULL, 0x00000001, 19580 }, /* DIVL */
+{ op_4c40_0_comp_ff, 0x00000002, 19520 }, /* DIVL */
+{ op_4c50_0_comp_ff, 0x00000002, 19536 }, /* DIVL */
+{ op_4c58_0_comp_ff, 0x00000002, 19544 }, /* DIVL */
+{ op_4c60_0_comp_ff, 0x00000002, 19552 }, /* DIVL */
+{ op_4c68_0_comp_ff, 0x00000002, 19560 }, /* DIVL */
+{ op_4c70_0_comp_ff, 0x00000002, 19568 }, /* DIVL */
+{ op_4c78_0_comp_ff, 0x00000002, 19576 }, /* DIVL */
+{ op_4c79_0_comp_ff, 0x00000002, 19577 }, /* DIVL */
+{ op_4c7a_0_comp_ff, 0x00000002, 19578 }, /* DIVL */
+{ op_4c7b_0_comp_ff, 0x00000002, 19579 }, /* DIVL */
+{ op_4c7c_0_comp_ff, 0x00000002, 19580 }, /* DIVL */
 { op_4c90_0_comp_ff, 0x00000002, 19600 }, /* MVMEL */
 { op_4c98_0_comp_ff, 0x00000002, 19608 }, /* MVMEL */
 { op_4ca8_0_comp_ff, 0x00000002, 19624 }, /* MVMEL */
@@ -1667,27 +1667,27 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
 { op_e0f9_0_comp_ff, 0x00000002, 57593 }, /* ASRW */
 { op_e100_0_comp_ff, 0x00000000, 57600 }, /* ASL */
 { op_e108_0_comp_ff, 0x00000000, 57608 }, /* LSL */
-{ NULL, 0x00000008, 57616 }, /* ROXL */
+{ op_e110_0_comp_ff, 0x00000008, 57616 }, /* ROXL */
 { op_e118_0_comp_ff, 0x00000000, 57624 }, /* ROL */
 { op_e120_0_comp_ff, 0x00000000, 57632 }, /* ASL */
 { op_e128_0_comp_ff, 0x00000000, 57640 }, /* LSL */
-{ NULL, 0x00000008, 57648 }, /* ROXL */
+{ op_e130_0_comp_ff, 0x00000008, 57648 }, /* ROXL */
 { op_e138_0_comp_ff, 0x00000000, 57656 }, /* ROL */
 { op_e140_0_comp_ff, 0x00000000, 57664 }, /* ASL */
 { op_e148_0_comp_ff, 0x00000000, 57672 }, /* LSL */
-{ NULL, 0x00000008, 57680 }, /* ROXL */
+{ op_e150_0_comp_ff, 0x00000008, 57680 }, /* ROXL */
 { op_e158_0_comp_ff, 0x00000000, 57688 }, /* ROL */
 { op_e160_0_comp_ff, 0x00000000, 57696 }, /* ASL */
 { op_e168_0_comp_ff, 0x00000000, 57704 }, /* LSL */
-{ NULL, 0x00000008, 57712 }, /* ROXL */
+{ op_e170_0_comp_ff, 0x00000008, 57712 }, /* ROXL */
 { op_e178_0_comp_ff, 0x00000000, 57720 }, /* ROL */
 { op_e180_0_comp_ff, 0x00000000, 57728 }, /* ASL */
 { op_e188_0_comp_ff, 0x00000000, 57736 }, /* LSL */
-{ NULL, 0x00000008, 57744 }, /* ROXL */
+{ op_e190_0_comp_ff, 0x00000008, 57744 }, /* ROXL */
 { op_e198_0_comp_ff, 0x00000000, 57752 }, /* ROL */
 { op_e1a0_0_comp_ff, 0x00000000, 57760 }, /* ASL */
 { op_e1a8_0_comp_ff, 0x00000000, 57768 }, /* LSL */
-{ NULL, 0x00000008, 57776 }, /* ROXL */
+{ op_e1b0_0_comp_ff, 0x00000008, 57776 }, /* ROXL */
 { op_e1b8_0_comp_ff, 0x00000000, 57784 }, /* ROL */
 { op_e1d0_0_comp_ff, 0x00000000, 57808 }, /* ASLW */
 { op_e1d8_0_comp_ff, 0x00000000, 57816 }, /* ASLW */
@@ -2736,17 +2736,17 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
 { op_4c3a_0_comp_nf, 0x00000002, 19514 }, /* MULL */
 { op_4c3b_0_comp_nf, 0x00000002, 19515 }, /* MULL */
 { op_4c3c_0_comp_nf, 0x00000002, 19516 }, /* MULL */
-{ NULL, 0x00000001, 19520 }, /* DIVL */
-{ NULL, 0x00000001, 19536 }, /* DIVL */
-{ NULL, 0x00000001, 19544 }, /* DIVL */
-{ NULL, 0x00000001, 19552 }, /* DIVL */
-{ NULL, 0x00000001, 19560 }, /* DIVL */
-{ NULL, 0x00000001, 19568 }, /* DIVL */
-{ NULL, 0x00000001, 19576 }, /* DIVL */
-{ NULL, 0x00000001, 19577 }, /* DIVL */
-{ NULL, 0x00000001, 19578 }, /* DIVL */
-{ NULL, 0x00000001, 19579 }, /* DIVL */
-{ NULL, 0x00000001, 19580 }, /* DIVL */
+{ op_4c40_0_comp_nf, 0x00000002, 19520 }, /* DIVL */
+{ op_4c50_0_comp_nf, 0x00000002, 19536 }, /* DIVL */
+{ op_4c58_0_comp_nf, 0x00000002, 19544 }, /* DIVL */
+{ op_4c60_0_comp_nf, 0x00000002, 19552 }, /* DIVL */
+{ op_4c68_0_comp_nf, 0x00000002, 19560 }, /* DIVL */
+{ op_4c70_0_comp_nf, 0x00000002, 19568 }, /* DIVL */
+{ op_4c78_0_comp_nf, 0x00000002, 19576 }, /* DIVL */
+{ op_4c79_0_comp_nf, 0x00000002, 19577 }, /* DIVL */
+{ op_4c7a_0_comp_nf, 0x00000002, 19578 }, /* DIVL */
+{ op_4c7b_0_comp_nf, 0x00000002, 19579 }, /* DIVL */
+{ op_4c7c_0_comp_nf, 0x00000002, 19580 }, /* DIVL */
 { op_4c90_0_comp_nf, 0x00000002, 19600 }, /* MVMEL */
 { op_4c98_0_comp_nf, 0x00000002, 19608 }, /* MVMEL */
 { op_4ca8_0_comp_nf, 0x00000002, 19624 }, /* MVMEL */
@@ -3539,27 +3539,27 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
 { op_e0f9_0_comp_nf, 0x00000002, 57593 }, /* ASRW */
 { op_e100_0_comp_nf, 0x00000000, 57600 }, /* ASL */
 { op_e108_0_comp_nf, 0x00000000, 57608 }, /* LSL */
-{ NULL, 0x00000008, 57616 }, /* ROXL */
+{ op_e110_0_comp_nf, 0x00000008, 57616 }, /* ROXL */
 { op_e118_0_comp_nf, 0x00000000, 57624 }, /* ROL */
 { op_e120_0_comp_nf, 0x00000000, 57632 }, /* ASL */
 { op_e128_0_comp_nf, 0x00000000, 57640 }, /* LSL */
-{ NULL, 0x00000008, 57648 }, /* ROXL */
+{ op_e130_0_comp_nf, 0x00000008, 57648 }, /* ROXL */
 { op_e138_0_comp_nf, 0x00000000, 57656 }, /* ROL */
 { op_e140_0_comp_nf, 0x00000000, 57664 }, /* ASL */
 { op_e148_0_comp_nf, 0x00000000, 57672 }, /* LSL */
-{ NULL, 0x00000008, 57680 }, /* ROXL */
+{ op_e150_0_comp_nf, 0x00000008, 57680 }, /* ROXL */
 { op_e158_0_comp_nf, 0x00000000, 57688 }, /* ROL */
 { op_e160_0_comp_nf, 0x00000000, 57696 }, /* ASL */
 { op_e168_0_comp_nf, 0x00000000, 57704 }, /* LSL */
-{ NULL, 0x00000008, 57712 }, /* ROXL */
+{ op_e170_0_comp_nf, 0x00000008, 57712 }, /* ROXL */
 { op_e178_0_comp_nf, 0x00000000, 57720 }, /* ROL */
 { op_e180_0_comp_nf, 0x00000000, 57728 }, /* ASL */
 { op_e188_0_comp_nf, 0x00000000, 57736 }, /* LSL */
-{ NULL, 0x00000008, 57744 }, /* ROXL */
+{ op_e190_0_comp_nf, 0x00000008, 57744 }, /* ROXL */
 { op_e198_0_comp_nf, 0x00000000, 57752 }, /* ROL */
 { op_e1a0_0_comp_nf, 0x00000000, 57760 }, /* ASL */
 { op_e1a8_0_comp_nf, 0x00000000, 57768 }, /* LSL */
-{ NULL, 0x00000008, 57776 }, /* ROXL */
+{ op_e1b0_0_comp_nf, 0x00000008, 57776 }, /* ROXL */
 { op_e1b8_0_comp_nf, 0x00000000, 57784 }, /* ROL */
 { op_e1d0_0_comp_nf, 0x00000000, 57808 }, /* ASLW */
 { op_e1d8_0_comp_nf, 0x00000000, 57816 }, /* ASLW */
diff --git a/src/jit/comptbl.h b/src/jit/comptbl.h
index 9a5735db..ab40977f 100644
--- a/src/jit/comptbl.h
+++ b/src/jit/comptbl.h
@@ -703,6 +703,17 @@ extern compop_func op_4c39_0_comp_ff;
 extern compop_func op_4c3a_0_comp_ff;
 extern compop_func op_4c3b_0_comp_ff;
 extern compop_func op_4c3c_0_comp_ff;
+extern compop_func op_4c40_0_comp_ff;
+extern compop_func op_4c50_0_comp_ff;
+extern compop_func op_4c58_0_comp_ff;
+extern compop_func op_4c60_0_comp_ff;
+extern compop_func op_4c68_0_comp_ff;
+extern compop_func op_4c70_0_comp_ff;
+extern compop_func op_4c78_0_comp_ff;
+extern compop_func op_4c79_0_comp_ff;
+extern compop_func op_4c7a_0_comp_ff;
+extern compop_func op_4c7b_0_comp_ff;
+extern compop_func op_4c7c_0_comp_ff;
 extern compop_func op_4c90_0_comp_ff;
 extern compop_func op_4c98_0_comp_ff;
 extern compop_func op_4ca8_0_comp_ff;
@@ -1417,21 +1428,27 @@ extern compop_func op_e0f8_0_comp_ff;
 extern compop_func op_e0f9_0_comp_ff;
 extern compop_func op_e100_0_comp_ff;
 extern compop_func op_e108_0_comp_ff;
+extern compop_func op_e110_0_comp_ff;
 extern compop_func op_e118_0_comp_ff;
 extern compop_func op_e120_0_comp_ff;
 extern compop_func op_e128_0_comp_ff;
+extern compop_func op_e130_0_comp_ff;
 extern compop_func op_e138_0_comp_ff;
 extern compop_func op_e140_0_comp_ff;
 extern compop_func op_e148_0_comp_ff;
+extern compop_func op_e150_0_comp_ff;
 extern compop_func op_e158_0_comp_ff;
 extern compop_func op_e160_0_comp_ff;
 extern compop_func op_e168_0_comp_ff;
+extern compop_func op_e170_0_comp_ff;
 extern compop_func op_e178_0_comp_ff;
 extern compop_func op_e180_0_comp_ff;
 extern compop_func op_e188_0_comp_ff;
+extern compop_func op_e190_0_comp_ff;
 extern compop_func op_e198_0_comp_ff;
 extern compop_func op_e1a0_0_comp_ff;
 extern compop_func op_e1a8_0_comp_ff;
+extern compop_func op_e1b0_0_comp_ff;
 extern compop_func op_e1b8_0_comp_ff;
 extern compop_func op_e1d0_0_comp_ff;
 extern compop_func op_e1d8_0_comp_ff;
@@ -2194,6 +2211,17 @@ extern compop_func op_4c39_0_comp_nf;
 extern compop_func op_4c3a_0_comp_nf;
 extern compop_func op_4c3b_0_comp_nf;
 extern compop_func op_4c3c_0_comp_nf;
+extern compop_func op_4c40_0_comp_nf;
+extern compop_func op_4c50_0_comp_nf;
+extern compop_func op_4c58_0_comp_nf;
+extern compop_func op_4c60_0_comp_nf;
+extern compop_func op_4c68_0_comp_nf;
+extern compop_func op_4c70_0_comp_nf;
+extern compop_func op_4c78_0_comp_nf;
+extern compop_func op_4c79_0_comp_nf;
+extern compop_func op_4c7a_0_comp_nf;
+extern compop_func op_4c7b_0_comp_nf;
+extern compop_func op_4c7c_0_comp_nf;
 extern compop_func op_4c90_0_comp_nf;
 extern compop_func op_4c98_0_comp_nf;
 extern compop_func op_4ca8_0_comp_nf;
@@ -2908,21 +2936,27 @@ extern compop_func op_e0f8_0_comp_nf;
 extern compop_func op_e0f9_0_comp_nf;
 extern compop_func op_e100_0_comp_nf;
 extern compop_func op_e108_0_comp_nf;
+extern compop_func op_e110_0_comp_nf;
 extern compop_func op_e118_0_comp_nf;
 extern compop_func op_e120_0_comp_nf;
 extern compop_func op_e128_0_comp_nf;
+extern compop_func op_e130_0_comp_nf;
 extern compop_func op_e138_0_comp_nf;
 extern compop_func op_e140_0_comp_nf;
 extern compop_func op_e148_0_comp_nf;
+extern compop_func op_e150_0_comp_nf;
 extern compop_func op_e158_0_comp_nf;
 extern compop_func op_e160_0_comp_nf;
 extern compop_func op_e168_0_comp_nf;
+extern compop_func op_e170_0_comp_nf;
 extern compop_func op_e178_0_comp_nf;
 extern compop_func op_e180_0_comp_nf;
 extern compop_func op_e188_0_comp_nf;
+extern compop_func op_e190_0_comp_nf;
 extern compop_func op_e198_0_comp_nf;
 extern compop_func op_e1a0_0_comp_nf;
 extern compop_func op_e1a8_0_comp_nf;
+extern compop_func op_e1b0_0_comp_nf;
 extern compop_func op_e1b8_0_comp_nf;
 extern compop_func op_e1d0_0_comp_nf;
 extern compop_func op_e1d8_0_comp_nf;
diff --git a/src/jit/gencomp_arm.cpp b/src/jit/gencomp_arm.cpp
index 33448cff..5e074309 100644
--- a/src/jit/gencomp_arm.cpp
+++ b/src/jit/gencomp_arm.cpp
@@ -107,7 +107,7 @@
 //#define DISABLE_I_LSL
 //#define DISABLE_I_ROL
 //#define DISABLE_I_ROR
-#define DISABLE_I_ROXL
+//#define DISABLE_I_ROXL
 #define DISABLE_I_ROXR
 //#define DISABLE_I_ASRW
 //#define DISABLE_I_ASLW
@@ -125,6 +125,7 @@
 
 //#define DISABLE_I_DIVU
 //#define DISABLE_I_DIVS
+//#define DISABLE_I_DIVL
 
 
 #define RETURN "return 0;"
@@ -1300,6 +1301,47 @@ static void gen_divs(uae_u32 opcode, struct instr *curi, char* ssize) {
 	genastore("tmp", curi->dmode, "dstreg", sz_long /*curi->size*/, "dst");
 }
 
+static void gen_divl(uae_u32 opcode, struct instr *curi, char* ssize) {
+	(void) opcode;
+	(void) ssize;
+  comprintf("\t dont_care_flags();\n");
+	comprintf("\t uae_u16 extra=%s;\n", gen_nextiword());
+  comprintf("\t int r2=(extra>>12)&7;\n");
+	comprintf("\t int r3=extra&7;\n");
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+  comprintf("\tregister_possible_exception();\n");
+
+	if (!noflags) {
+		comprintf("\t if (extra & 0x0400) {\n"); /* Need full 64 bit divisor */
+		comprintf("\t   FAIL(1);\n");
+    comprintf("\t   m68k_pc_offset=m68k_pc_offset_thisinst;\n");
+		comprintf("\t  " RETURN "\n");
+		comprintf("\t	} else { \n");
+		/* operands in src and r2, result goes into r2, remainder into r3 */
+		/* s2 = s2 / src */
+		/* s3 = s2 % src */
+		comprintf("\t   if (extra & 0x0800) { \n"); /* signed */
+		comprintf("\t     jff_DIVLS32(r2,dst,r3);\n");
+		comprintf("\t	} else { \n");
+		comprintf("\t\t	  jff_DIVLU32(r2,dst,r3);\n");
+		comprintf("\t	} \n");
+		comprintf("\t }\n");
+		comprintf("\t live_flags();\n");
+	} else {
+		comprintf("\t if (extra & 0x0400) {\n"); /* Need full 64 bit divisor */
+		comprintf("\t   FAIL(1);\n");
+    comprintf("\t   m68k_pc_offset=m68k_pc_offset_thisinst;\n");
+		comprintf("\t  " RETURN "\n");
+		comprintf("\t } else {\n");
+		comprintf("\t   if (extra & 0x0800) { \n"); /* signed */
+		comprintf("\t     jnf_DIVLS32(r2,dst,r3);\n");
+		comprintf("\t	} else { \n");
+		comprintf("\t\t	  jnf_DIVLU32(r2,dst,r3);\n");
+		comprintf("\t	} \n");
+		comprintf("\t }\n");
+	}
+}
+
 static void gen_eor(uae_u32 opcode, struct instr *curi, char* ssize) {
 	(void) opcode;
 	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
@@ -1538,7 +1580,6 @@ static void gen_mull(uae_u32 opcode, struct instr *curi, char* ssize) {
 		comprintf("\t	} \n"); /* The result is in r2/r3, with r2 holding the lower 32 bits */
 		comprintf("\t } else {\n"); /* Only want 32 bit result */
 		/* operands in dst and r2, result goes into r2 */
-		/* shouldn't matter whether it's signed or unsigned?!? */
 		comprintf("\t   if (extra & 0x0800) { \n"); /* signed */
 		comprintf("\t     jff_MULS32(r2,dst);\n");
 		comprintf("\t	} else { \n");
@@ -1557,7 +1598,6 @@ static void gen_mull(uae_u32 opcode, struct instr *curi, char* ssize) {
 		comprintf("\t	} \n"); /* The result is in r2/r3, with r2 holding the lower 32 bits */
 		comprintf("\t } else {\n"); /* Only want 32 bit result */
 		/* operands in dst and r2, result foes into r2 */
-		/* shouldn't matter whether it's signed or unsigned?!? */
 		comprintf("\t   if (extra & 0x0800) { \n"); /* signed */
 		comprintf("\t     jnf_MULS32(r2,dst);\n");
 		comprintf("\t	} else { \n");
@@ -2716,8 +2756,10 @@ gen_opcode(unsigned long int opcode) {
 		break;
 
 	case i_DIVL:
-		isjump;
+#ifdef DISABLE_I_DIVL
 		failure;
+#endif
+		gen_divl(opcode, curi, ssize);
 		break;
 
 	case i_MULL:
@@ -3043,7 +3085,7 @@ generate_one_opcode(int rp, int noflags)
 	dmsk = 7;
 
 	next_cpu_level = -1;
-  if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS) {
+  if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS || table68k[opcode].mnemo == i_DIVL) {
     comprintf("#ifndef ARMV6T2\n");
     comprintf("  FAIL(1);\n");
     comprintf("  " RETURN "\n");
@@ -3141,7 +3183,7 @@ generate_one_opcode(int rp, int noflags)
 		if (global_fpu)	flags |= 32;
 
 	  comprintf ("return 0;\n");
-    if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS) {
+    if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS || table68k[opcode].mnemo == i_DIVL) {
       comprintf("#endif\n");
     }