pandory500/redquark-amiberry-rb
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Updated memory handling from WinUAE

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This commit is contained in:
Dimitris Panokostas 2019-11-01 19:04:31 +01:00
parent e9c124a1dc
commit 821d857735
17 changed files with 2478 additions and 622 deletions
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49
src/akiko.cpp
View file

@ -188,10 +188,12 @@ static int cd32_nvram_size;
static void *cd32_eeprom;
static uae_u8 cd32_i2c_direction;
static bool cd32_i2c_data_scl, cd32_i2c_data_sda;
static struct zfile *cd32_flashfile;
struct zfile *cd32_flashfile;
//extern uae_u8 *cubo_nvram;
static void nvram_read (void)
{
//cubo_nvram = NULL;
zfile_fclose(cd32_flashfile);
cd32_flashfile = NULL;
eeprom_free(cd32_eeprom);
@ -201,11 +203,16 @@ static void nvram_read (void)
if (!currprefs.cs_cd32nvram)
return;
int maxlen = currprefs.cs_cd32nvram_size;
if (is_board_enabled(&currprefs, ROMTYPE_CUBO, 0))
maxlen += 2048 + 16;
if (!cd32_nvram || cd32_nvram_size != maxlen) {
xfree(cd32_nvram);
cd32_nvram = xmalloc(uae_u8, maxlen);
}
memset(cd32_nvram, 0, maxlen);
//if (is_board_enabled(&currprefs, ROMTYPE_CUBO, 0)) {
// cubo_nvram = cd32_nvram + currprefs.cs_cd32nvram_size;
//}
TCHAR path[MAX_DPATH];
cfgfile_resolve_path_out_load(currprefs.flashfile, path, MAX_DPATH, PATH_ROM);
cd32_flashfile = zfile_fopen (path, _T("rb+"), ZFD_NORMAL);
@ -213,6 +220,8 @@ static void nvram_read (void)
cd32_flashfile = zfile_fopen (path, _T("wb"), 0);
if (cd32_flashfile) {
int size = zfile_fread(cd32_nvram, 1, currprefs.cs_cd32nvram_size, cd32_flashfile);
//if (size == currprefs.cs_cd32nvram_size && maxlen > currprefs.cs_cd32nvram_size)
// size += zfile_fread(cubo_nvram, 1, maxlen - currprefs.cs_cd32nvram_size, cd32_flashfile);
if (size < maxlen)
zfile_fwrite(cd32_nvram + size, 1, maxlen - size, cd32_flashfile);
}
@ -410,6 +419,7 @@ static uae_u8 cdrom_command;
static uae_u8 cdrom_last_rx;
static int cdrom_toc_counter;
static uae_u32 cdrom_toc_crc;
static uae_u8 cdrom_toc_buffer[MAX_TOC_ENTRIES * 13];
static struct cd_toc_head cdrom_toc_cd_buffer;
static uae_u8 qcode_buf[SUBQ_SIZE];
@ -434,7 +444,7 @@ static int sector_buffer_sector_1, sector_buffer_sector_2;
static uae_u8 *sector_buffer_info_1, *sector_buffer_info_2;
static int unitnum = -1;
static const uae_u8 cdrom_door = 1;
static uae_u8 cdrom_door = 1;
static bool akiko_inited;
static volatile int mediachanged, mediacheckcounter;
static volatile int frame2counter;
@ -695,6 +705,7 @@ static int get_cdrom_toc (void)
if (s->point >= 2 && s->point < 100 && (s->control & 0x0c) != 0x04 && !secondtrack)
secondtrack = addr;
}
cdrom_toc_crc = get_crc32 (cdrom_toc_buffer, cdrom_toc_cd_buffer.points * 13);
return 0;
}
static bool is_valid_data_sector(int sector)
@ -813,6 +824,13 @@ static int cdrom_command_led (void)
return 0;
}
static int cdrom_command_idle_status (void)
{
cdrom_result_buffer[0] = 0x0a;
cdrom_result_buffer[1] = 0x70;
return 2;
}
static int cdrom_command_media_status (void)
{
cdrom_result_buffer[0] = 0x0a;
@ -1459,6 +1477,8 @@ STATIC_INLINE void akiko_put_long (uae_u32 *p, int offset, int v)
static uae_u32 REGPARAM3 akiko_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 akiko_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 akiko_bget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 akiko_lgeti (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 akiko_wgeti (uaecptr) REGPARAM;
static void REGPARAM3 akiko_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 akiko_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 akiko_bput (uaecptr, uae_u32) REGPARAM;
@ -1529,18 +1549,21 @@ static uae_u32 akiko_bget2 (uaecptr addr, int msg)
// 0x18-0x1b are mirrored to 0x10, 0x14 and 0x1c
case 0x18:
case 0x10:
case 0x14:
case 0x1c:
v = cdrom_subcodeoffset;
break;
case 0x19:
case 0x11:
case 0x15:
case 0x1d:
v = cdcomtxinx;
break;
case 0x1a:
case 0x12:
case 0x16:
case 0x1e:
@ -1793,30 +1816,30 @@ addrbank akiko_bank = {
akiko_lget, akiko_wget, akiko_bget,
akiko_lput, akiko_wput, akiko_bput,
default_xlate, default_check, NULL, NULL, _T("Akiko"),
dummy_wgeti,
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const uae_u8 patchdata[]={0x0c,0x82,0x00,0x00,0x03,0xe8,0x64,0x00,0x00,0x46};
static void patchrom (void)
{
int i;
int i;
if (currprefs.cpu_model > 68020 || currprefs.cachesize || currprefs.m68k_speed != 0) {
uae_u8 *p = extendedkickmem_bank.baseaddr;
uae_u8* p = extendedkickmem_bank.baseaddr;
if (p) {
for (i = 0; i < 524288 - sizeof (patchdata); i++) {
if (!memcmp (p + i, patchdata, sizeof(patchdata))) {
protect_roms (false);
for (i = 0; i < 524288 - sizeof(patchdata); i++) {
if (!memcmp(p + i, patchdata, sizeof(patchdata))) {
protect_roms(false);
p[i + 6] = 0x4e;
p[i + 7] = 0x71;
p[i + 8] = 0x4e;
p[i + 9] = 0x71;
protect_roms (true);
write_log (_T("CD32: extended rom delay loop patched at 0x%08x\n"), i + 6 + 0xe00000);
protect_roms(true);
write_log(_T("CD32: extended rom delay loop patched at 0x%08x\n"), i + 6 + 0xe00000);
return;
}
}
write_log (_T("CD32: couldn't patch extended rom\n"));
write_log(_T("CD32: couldn't patch extended rom\n"));
}
}
}
@ -1834,7 +1857,7 @@ static void akiko_cdrom_free (void)
sector_buffer_info_2 = 0;
}
void akiko_reset (int hardreset)
void akiko_reset(int hardreset)
{
cdaudiostop_do ();
nvram_read ();
@ -1966,7 +1989,7 @@ uae_u8 *save_akiko (int *len, uae_u8 *dstptr)
save_u8 (cdrom_speed);
save_u8 (cdrom_current_sector);
save_u32 (0);
save_u32 (cdrom_toc_crc);
save_u8 (cdrom_toc_cd_buffer.points);
save_u32 (cdrom_toc_cd_buffer.lastaddress);

46
src/ar.cpp
View file

@ -462,21 +462,21 @@ static addrbank hrtmem_bank = {
hrtmem_lget, hrtmem_wget, hrtmem_bget,
hrtmem_lput, hrtmem_wput, hrtmem_bput,
hrtmem_xlate, hrtmem_check, NULL, NULL, _T("Cartridge Bank"),
hrtmem_wget,
hrtmem_lget, hrtmem_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
static addrbank hrtmem2_bank = {
hrtmem2_lget, hrtmem2_wget, hrtmem2_bget,
hrtmem2_lput, hrtmem2_wput, hrtmem2_bput,
hrtmem2_xlate, hrtmem2_check, NULL, NULL, _T("Cartridge Bank 2"),
hrtmem2_wget,
hrtmem2_lget, hrtmem2_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
static addrbank hrtmem3_bank = {
hrtmem3_lget, hrtmem3_wget, hrtmem3_bget,
hrtmem3_lput, hrtmem3_wput, hrtmem3_bput,
hrtmem3_xlate, hrtmem3_check, NULL, NULL, _T("Cartridge Bank 3"),
hrtmem3_wget,
hrtmem3_lget, hrtmem3_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
@ -640,6 +640,29 @@ void REGPARAM2 chipmem_wput_actionreplay23 (uaecptr addr, uae_u32 w)
}
static uae_u32 REGPARAM3 arram_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arram_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arram_bget (uaecptr) REGPARAM;
static void REGPARAM3 arram_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arram_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arram_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 arram_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 arram_xlate (uaecptr addr) REGPARAM;
static uae_u32 REGPARAM3 arrom_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arrom_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arrom_bget (uaecptr) REGPARAM;
static void REGPARAM3 arrom_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arrom_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arrom_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 arrom_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 arrom_xlate (uaecptr addr) REGPARAM;
static void action_replay_unmap_banks (void);
static uae_u32 action_replay_calculate_checksum(void);
static uae_u8* get_checksum_location(void);
static void disable_rom_test(void);
static uae_u32 ar_null(int size)
{
if (size == 4)
@ -803,14 +826,14 @@ static addrbank arrom_bank = {
arrom_lget, arrom_wget, arrom_bget,
arrom_lput, arrom_wput, arrom_bput,
arrom_xlate, arrom_check, NULL, NULL, _T("Action Replay ROM"),
arrom_wget,
arrom_lget, arrom_wget,
ABFLAG_ROM, S_READ, S_WRITE
};
static addrbank arram_bank = {
arram_lget, arram_wget, arram_bget,
arram_lput, arram_wput, arram_bput,
arram_xlate, arram_check, NULL, NULL, _T("Action Replay RAM"),
arram_wget,
arram_lget, arram_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
@ -1258,6 +1281,18 @@ static uae_u8* get_checksum_location (void)
return (uae_u8*)checksum_end;
}
/* Replaces the existing cart checksum with a correct one. */
/* Useful if you want to patch the rom. */
static void action_replay_fixup_checksum (uae_u32 new_checksum)
{
uae_u32* checksum = (uae_u32*)get_checksum_location();
if (checksum)
do_put_mem_long (checksum, new_checksum);
else
write_log (_T("Unable to locate Checksum in ROM.\n"));
return;
}
/* Longword search on word boundary
* the search_value is assumed to already be in the local endian format
* return 0 on failure
@ -1421,6 +1456,7 @@ int action_replay_unload (int in_memory_reset)
static int superiv_init (struct romdata *rd, struct zfile *f)
{
uae_u32 chip = currprefs.chipmem_size - 0x10000;
int subtype = rd->id;
int flags = rd->type & ROMTYPE_MASK;
const TCHAR *memname1, *memname2, *memname3;

119
src/autoconf.cpp
View file

@ -43,8 +43,8 @@ addrbank rtarea_bank = {
rtarea_lget, rtarea_wget, rtarea_bget,
rtarea_lput, rtarea_wput, rtarea_bput,
rtarea_xlate, rtarea_check, NULL, _T("rtarea"), _T("UAE Boot ROM"),
rtarea_wget,
ABFLAG_ROMIN, S_READ, S_WRITE
rtarea_lget, rtarea_wget,
ABFLAG_ROMIN | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
#define MAX_ABSOLUTE_ROM_ADDRESS 1024
@ -96,6 +96,7 @@ static void rethink_traps(void)
rethink_traps2();
}
#define RTAREA_WRITEOFFSET 0xfff0
static bool rtarea_trap_data(uaecptr addr)
@ -123,7 +124,7 @@ static bool rtarea_trap_status_extra(uaecptr addr)
return false;
}
static uae_u8 *REGPARAM2 rtarea_xlate(uaecptr addr)
static uae_u8 *REGPARAM2 rtarea_xlate (uaecptr addr)
{
addr &= 0xFFFF;
return rtarea_bank.baseaddr + addr;
@ -444,54 +445,54 @@ void add_rom_absolute(uaecptr addr)
save_rom_absolute(h);
}
//uae_u32 boot_rom_copy(TrapContext *ctx, uaecptr rombase, int mode)
//{
// uaecptr reloc = 0;
// if (currprefs.uaeboard < 3)
// return 0;
// if (!mode) {
// rtarea_write_enabled = true;
// protect_roms(false);
// rombase_new = rombase;
// int size = 4 + 2 + 4;
// for (int i = 0; i < absolute_rom_address; i++) {
// uae_u32 a = absolute_rom_addresses[i];
// if (a >= rtarea_base && a < rtarea_base + 0x10000) {
// size += 2;
// } else {
// size += 4;
// }
// }
// reloc = uaeboard_alloc_ram(size);
// uae_u8 *p = uaeboard_map_ram(reloc);
// put_long_host(p, rtarea_base);
// p += 4;
// for (int i = 0; i < absolute_rom_address; i++) {
// uae_u32 a = absolute_rom_addresses[i];
// if (a >= rtarea_base && a < rtarea_base + 0x10000) {
// put_word_host(p, a & 0xffff);
// p += 2;
// }
// }
// put_word_host(p, 0);
// p += 2;
// for (int i = 0; i < absolute_rom_address; i++) {
// uae_u32 a = absolute_rom_addresses[i];
// if (a < rtarea_base || a >= rtarea_base + 0x10000) {
// put_long_host(p, a);
// p += 4;
// }
// }
// put_long_host(p, 0);
// write_log(_T("ROMBASE %08x RAMBASE %08x RELOC %08x (%d)\n"), rtarea_base, rombase, reloc, absolute_rom_address);
// } else {
// rtarea_write_enabled = false;
// protect_roms(true);
// write_log(_T("ROMBASE changed.\n"), absolute_rom_address);
// reloc = 1;
// }
// return reloc;
//}
uae_u32 boot_rom_copy(TrapContext *ctx, uaecptr rombase, int mode)
{
uaecptr reloc = 0;
if (currprefs.uaeboard < 3)
return 0;
if (!mode) {
rtarea_write_enabled = true;
protect_roms(false);
rombase_new = rombase;
int size = 4 + 2 + 4;
for (int i = 0; i < absolute_rom_address; i++) {
uae_u32 a = absolute_rom_addresses[i];
if (a >= rtarea_base && a < rtarea_base + 0x10000) {
size += 2;
} else {
size += 4;
}
}
reloc = uaeboard_alloc_ram(size);
uae_u8 *p = uaeboard_map_ram(reloc);
put_long_host(p, rtarea_base);
p += 4;
for (int i = 0; i < absolute_rom_address; i++) {
uae_u32 a = absolute_rom_addresses[i];
if (a >= rtarea_base && a < rtarea_base + 0x10000) {
put_word_host(p, a & 0xffff);
p += 2;
}
}
put_word_host(p, 0);
p += 2;
for (int i = 0; i < absolute_rom_address; i++) {
uae_u32 a = absolute_rom_addresses[i];
if (a < rtarea_base || a >= rtarea_base + 0x10000) {
put_long_host(p, a);
p += 4;
}
}
put_long_host(p, 0);
write_log(_T("ROMBASE %08x RAMBASE %08x RELOC %08x (%d)\n"), rtarea_base, rombase, reloc, absolute_rom_address);
} else {
rtarea_write_enabled = false;
protect_roms(true);
write_log(_T("ROMBASE changed.\n"), absolute_rom_address);
reloc = 1;
}
return reloc;
}
void calltrap (uae_u32 n)
{
@ -536,23 +537,29 @@ static uae_u32 REGPARAM2 nullfunc(TrapContext *ctx)
static uae_u32 REGPARAM2 getchipmemsize (TrapContext *ctx)
{
//trap_set_dreg(ctx, 1, z3chipmem_bank.allocated_size);
//trap_set_areg(ctx, 1, z3chipmem_bank.start);
trap_set_dreg(ctx, 1, z3chipmem_bank.allocated_size);
trap_set_areg(ctx, 1, z3chipmem_bank.start);
return chipmem_bank.allocated_size;
}
static uae_u32 REGPARAM2 uae_puts (TrapContext *ctx)
static uae_u32 REGPARAM2 uae_puts(TrapContext* ctx)
{
uae_char buf[MAX_DPATH];
trap_get_string(ctx, buf, trap_get_areg(ctx, 0), sizeof (uae_char));
TCHAR *s = au(buf);
TCHAR* s = au(buf);
write_log(_T("%s"), s);
xfree(s);
return 0;
}
static void rtarea_init_mem (void)
void rtarea_init_mem (void)
{
if (need_uae_boot_rom(&currprefs)) {
rtarea_bank.flags &= ~ABFLAG_ALLOCINDIRECT;
} else {
// not enabled and something else may use same address space
rtarea_bank.flags |= ABFLAG_ALLOCINDIRECT;
}
rtarea_bank.reserved_size = RTAREA_SIZE;
rtarea_bank.start = rtarea_base;
if (!mapped_malloc(&rtarea_bank)) {

6
src/blkdev.cpp
View file

@ -416,6 +416,12 @@ void blkdev_exitgui (void)
}
}
void check_prefs_changed_cd(void)
{
if (!config_changed)
return;
}
static void check_changes (int unitnum)
{
struct blkdevstate *st = &state[unitnum];

6
src/cd32_fmv.cpp
View file

@ -304,7 +304,7 @@ static addrbank fmv_bank = {
fmv_lget, fmv_wget, fmv_bget,
fmv_lput, fmv_wput, fmv_bput,
default_xlate, default_check, NULL, NULL, _T("CD32 FMV IO"),
fmv_wget,
fmv_lget, fmv_wget,
ABFLAG_IO, S_READ, S_WRITE
};
@ -313,7 +313,7 @@ static addrbank fmv_rom_bank = {
fmv_rom_lget, fmv_rom_wget, fmv_rom_bget,
fmv_rom_lput, fmv_rom_wput, fmv_rom_bput,
fmv_rom_xlate, fmv_rom_check, NULL, _T("*"), _T("CD32 FMV ROM"),
fmv_rom_wget,
fmv_rom_lget, fmv_rom_wget,
ABFLAG_ROM, S_READ, S_WRITE
};
@ -322,7 +322,7 @@ static addrbank fmv_ram_bank = {
fmv_ram_lget, fmv_ram_wget, fmv_ram_bget,
fmv_ram_lput, fmv_ram_wput, fmv_ram_bput,
fmv_ram_xlate, fmv_ram_check, NULL, _T("*"), _T("CD32 FMV RAM"),
fmv_ram_wget,
fmv_ram_lget, fmv_ram_wget,
ABFLAG_RAM, S_READ, S_WRITE
};

16
src/cia.cpp
View file

@ -1132,7 +1132,7 @@ addrbank cia_bank = {
cia_lget, cia_wget, cia_bget,
cia_lput, cia_wput, cia_bput,
default_xlate, default_check, NULL, NULL, _T("CIA"),
cia_wgeti,
cia_lgeti, cia_wgeti,
ABFLAG_IO | ABFLAG_CIA, S_READ, S_WRITE, NULL, 0x3f01, 0xbfc000
};
@ -1329,9 +1329,15 @@ static uae_u32 REGPARAM2 cia_lget (uaecptr addr)
static uae_u32 REGPARAM2 cia_wgeti (uaecptr addr)
{
if (currprefs.cpu_model >= 68020)
return dummy_wgeti(addr);
return cia_wget(addr);
if (currprefs.cpu_model >= 68020)
return dummy_wgeti (addr);
return cia_wget (addr);
}
static uae_u32 REGPARAM2 cia_lgeti (uaecptr addr)
{
if (currprefs.cpu_model >= 68020)
return dummy_lgeti (addr);
return cia_lget (addr);
}
static void REGPARAM2 cia_bput (uaecptr addr, uae_u32 value)
@ -1414,7 +1420,7 @@ addrbank clock_bank = {
clock_lget, clock_wget, clock_bget,
clock_lput, clock_wput, clock_bput,
default_xlate, default_check, NULL, NULL, _T("Battery backed up clock (none)"),
dummy_wgeti,
dummy_lgeti, dummy_wgeti,
ABFLAG_IO, S_READ, S_WRITE, NULL, 0x3f, 0xd80000
};

9
src/custom.cpp
View file

@ -8772,6 +8772,7 @@ int custom_init (void)
static uae_u32 REGPARAM3 custom_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 custom_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 custom_bget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 custom_lgeti (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 custom_wgeti (uaecptr) REGPARAM;
static void REGPARAM3 custom_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 custom_wput (uaecptr, uae_u32) REGPARAM;
@ -8781,7 +8782,7 @@ addrbank custom_bank = {
custom_lget, custom_wget, custom_bget,
custom_lput, custom_wput, custom_bput,
default_xlate, default_check, NULL, NULL, _T("Custom chipset"),
custom_wgeti,
custom_lgeti, custom_wgeti,
ABFLAG_IO, S_READ, S_WRITE, NULL, 0x1ff, 0xdff000
};
@ -8791,6 +8792,12 @@ static uae_u32 REGPARAM2 custom_wgeti (uaecptr addr)
return dummy_wgeti (addr);
return custom_wget (addr);
}
static uae_u32 REGPARAM2 custom_lgeti (uaecptr addr)
{
if (currprefs.cpu_model >= 68020)
return dummy_lgeti (addr);
return custom_lget (addr);
}
STATIC_INLINE uae_u32 REGPARAM2 custom_wget_1(int hpos, uaecptr addr, int noput)
{

402
src/expansion.cpp
View file

@ -217,8 +217,8 @@ static addrbank*(*expamem_map)(struct autoconfig_info*);
static uae_u8 expamem_lo;
static uae_u16 expamem_hi;
static uaecptr expamem_z3_pointer_real, expamem_z3_pointer_uae;
static uaecptr expamem_z3_highram_real, expamem_z3_highram_uae;
uaecptr expamem_z3_pointer_real, expamem_z3_pointer_uae;
uaecptr expamem_z3_highram_real, expamem_z3_highram_uae;
uae_u32 expamem_board_size;
uaecptr expamem_board_pointer;
static uae_u8 slots_e8[8] = { 0 };
@ -231,7 +231,7 @@ void set_expamem_z3_hack_mode(int mode)
z3hack_override = mode;
}
static bool expamem_z3hack(struct uae_prefs *p)
bool expamem_z3hack(struct uae_prefs *p)
{
if (z3hack_override == Z3MAPPING_UAE)
return true;
@ -296,28 +296,42 @@ static void addextrachip (uae_u32 sysbase)
}
}
addrbank expamem_null;
addrbank expamem_null, expamem_none;
DECLARE_MEMORY_FUNCTIONS(expamem_write);
addrbank expamem_write_bank = {
expamem_write_lget, expamem_write_wget, expamem_write_bget,
expamem_write_lput, expamem_write_wput, expamem_write_bput,
default_xlate, default_check, NULL, NULL, _T("Autoconfig Z2 WRITE"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
DECLARE_MEMORY_FUNCTIONS(expamem);
addrbank expamem_bank = {
expamem_lget, expamem_wget, expamem_bget,
expamem_lput, expamem_wput, expamem_bput,
expamem_lget, expamem_wget, expamem_bget,
expamem_lput, expamem_wput, expamem_bput,
default_xlate, default_check, NULL, NULL, _T("Autoconfig Z2"),
dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
DECLARE_MEMORY_FUNCTIONS(expamemz3);
static addrbank expamemz3_bank = {
expamemz3_lget, expamemz3_wget, expamemz3_bget,
expamemz3_lput, expamemz3_wput, expamemz3_bput,
default_xlate, default_check, NULL, NULL, _T("Autoconfig Z3"),
dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
static addrbank *expamem_map_clear (void)
{
write_log (_T("expamem_map_clear() got called. Shouldn't happen.\n"));
return NULL;
}
static void expamem_init_clear (void)
{
memset (expamem, 0xff, sizeof expamem);
memset (expamem, 0xff, sizeof expamem);
expamem_hi = expamem_lo = 0;
expamem_map = NULL;
}
@ -325,9 +339,9 @@ static void expamem_init_clear (void)
static void expamem_init_clear_zero (void)
{
if (currprefs.cpu_model < 68020) {
map_banks (&dummy_bank, 0xe8, 1, 0);
if (!currprefs.address_space_24)
map_banks (&dummy_bank, AUTOCONFIG_Z3 >> 16, 1, 0);
map_banks(&dummy_bank, 0xe8, 1, 0);
if (!currprefs.address_space_24)
map_banks(&dummy_bank, AUTOCONFIG_Z3 >> 16, 1, 0);
} else {
map_banks(&expamem_bank, 0xe8, 1, 0);
if (!currprefs.address_space_24)
@ -340,8 +354,8 @@ static void expamem_init_clear2 (void)
{
expamem_bank.name = _T("Autoconfig Z2");
expamemz3_bank.name = _T("Autoconfig Z3");
expamem_init_clear_zero();
ecard = cardno;
expamem_init_clear_zero ();
ecard = cardno;
}
static addrbank *expamem_init_last (void)
@ -376,8 +390,6 @@ static int REGPARAM2 expamem_type (void)
return expamem_read(0) & 0xc0;
}
static void expamem_next (addrbank *mapped, addrbank *next);
static void call_card_init(int index)
{
addrbank *ab, *abe;
@ -390,6 +402,7 @@ static void call_card_init(int index)
aci->doinit = true;
aci->devnum = (cd->flags >> 16) & 255;
aci->ert = cd->ert;
//aci->cst = cd->cst;
aci->rc = cd->rc;
aci->zorro = cd->zorro;
memset(aci->autoconfig_raw, 0xff, sizeof aci->autoconfig_raw);
@ -407,6 +420,16 @@ static void call_card_init(int index)
expamem_next(NULL, NULL);
return;
}
if (ab == &expamem_none) {
write_log(_T("Card %d: skipping autoconfig (none)\n"), ecard);
expamem_init_clear();
expamem_init_clear_zero();
map_banks(&expamem_bank, 0xE8, 1, 0);
if (!currprefs.address_space_24)
map_banks(&dummy_bank, AUTOCONFIG_Z3 >> 16, 1, 0);
expamem_bank_current = NULL;
return;
}
if (ab == &expamem_null || cd->zorro < 1 || cd->zorro > 3 || aci->zorro < 0) {
write_log(_T("Card %d: skipping autoconfig (not autoconfig)\n"), ecard);
expamem_next(NULL, NULL);
@ -470,18 +493,18 @@ static void boardmessage(addrbank *mapped, bool success)
success ? _T("") : _T(" [SHUT UP]"));
}
static void expamem_next(addrbank *mapped, addrbank *next)
void expamem_next(addrbank* mapped, addrbank* next)
{
if (mapped)
boardmessage(mapped, mapped->start != 0xffffffff);
expamem_init_clear();
expamem_init_clear();
expamem_init_clear_zero();
for (;;) {
++ecard;
if (ecard >= cardno)
break;
struct card_data *ec = cards[ecard];
struct card_data* ec = cards[ecard];
if (ec->zorro == 3 && ec->base == 0xffffffff) {
write_log(_T("Autoconfig chain enumeration aborted, 32-bit address space overflow.\n"));
ecard = cardno;
@ -493,7 +516,8 @@ static void expamem_next(addrbank *mapped, addrbank *next)
aci.prefs = &currprefs;
aci.rc = cards[ecard]->rc;
ec->initrc(&aci);
} else {
}
else {
call_card_init(ecard);
break;
}
@ -806,11 +830,55 @@ static bool expamem_init_cd32fmv (struct autoconfig_info *aci)
/* ********************************************************** */
MEMORY_ARRAY_FUNCTIONS(romboardmem, 0);
MEMORY_ARRAY_FUNCTIONS(romboardmem, 1);
MEMORY_ARRAY_FUNCTIONS(romboardmem, 2);
MEMORY_ARRAY_FUNCTIONS(romboardmem, 3);
static void REGPARAM2 empty_put(uaecptr addr, uae_u32 v)
{
}
addrbank romboardmem_bank[MAX_ROM_BOARDS] =
{
{
romboardmem0_lget, romboardmem0_wget, romboardmem0_bget,
empty_put, empty_put, empty_put,
romboardmem0_xlate, romboardmem0_check, NULL, _T("*"), _T("ROM board"),
romboardmem0_lget, romboardmem0_wget,
ABFLAG_ROM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
romboardmem1_lget, romboardmem1_wget, romboardmem1_bget,
empty_put, empty_put, empty_put,
romboardmem1_xlate, romboardmem1_check, NULL, _T("*"), _T("ROM board"),
romboardmem1_lget, romboardmem1_wget,
ABFLAG_ROM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
romboardmem2_lget, romboardmem2_wget, romboardmem2_bget,
empty_put, empty_put, empty_put,
romboardmem2_xlate, romboardmem2_check, NULL, _T("*"), _T("ROM board"),
romboardmem2_lget, romboardmem2_wget,
ABFLAG_ROM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
romboardmem3_lget, romboardmem3_wget, romboardmem3_bget,
empty_put, empty_put, empty_put,
romboardmem3_xlate, romboardmem3_check, NULL, _T("*"), _T("ROM board"),
romboardmem3_lget, romboardmem3_wget,
ABFLAG_ROM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
}
};
/*
* Fast Memory
*/
MEMORY_ARRAY_FUNCTIONS(fastmem, 0);
MEMORY_ARRAY_FUNCTIONS(fastmem, 1);
MEMORY_ARRAY_FUNCTIONS(fastmem, 2);
MEMORY_ARRAY_FUNCTIONS(fastmem, 3);
addrbank fastmem_bank[MAX_RAM_BOARDS] =
{
@ -818,11 +886,142 @@ addrbank fastmem_bank[MAX_RAM_BOARDS] =
fastmem0_lget, fastmem0_wget, fastmem0_bget,
fastmem0_lput, fastmem0_wput, fastmem0_bput,
fastmem0_xlate, fastmem0_check, NULL, _T("*"), _T("Fast memory"),
fastmem0_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE, 0, 0
fastmem0_lget, fastmem0_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
fastmem1_lget, fastmem1_wget, fastmem1_bget,
fastmem1_lput, fastmem1_wput, fastmem1_bput,
fastmem1_xlate, fastmem1_check, NULL, _T("*"), _T("Fast memory 2"),
fastmem1_lget, fastmem1_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
fastmem2_lget, fastmem2_wget, fastmem2_bget,
fastmem2_lput, fastmem2_wput, fastmem2_bput,
fastmem2_xlate, fastmem2_check, NULL, _T("*"), _T("Fast memory 3"),
fastmem2_lget, fastmem2_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
fastmem3_lget, fastmem3_wget, fastmem3_bget,
fastmem3_lput, fastmem3_wput, fastmem3_bput,
fastmem3_xlate, fastmem3_check, NULL, _T("*"), _T("Fast memory 4"),
fastmem3_lget, fastmem3_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
}
};
#ifdef CATWEASEL
/*
* Catweasel ZorroII
*/
DECLARE_MEMORY_FUNCTIONS(catweasel);
static uae_u32 catweasel_mask;
static uae_u32 catweasel_start;
static uae_u32 REGPARAM2 catweasel_lget (uaecptr addr)
{
write_log (_T("catweasel_lget @%08X!\n"),addr);
return 0;
}
static uae_u32 REGPARAM2 catweasel_wget (uaecptr addr)
{
write_log (_T("catweasel_wget @%08X!\n"),addr);
return 0;
}
static uae_u32 REGPARAM2 catweasel_bget (uaecptr addr)
{
addr -= catweasel_start & catweasel_mask;
addr &= catweasel_mask;
return catweasel_do_bget (addr);
}
static void REGPARAM2 catweasel_lput (uaecptr addr, uae_u32 l)
{
write_log (_T("catweasel_lput @%08X=%08X!\n"),addr,l);
}
static void REGPARAM2 catweasel_wput (uaecptr addr, uae_u32 w)
{
write_log (_T("catweasel_wput @%08X=%04X!\n"),addr,w);
}
static void REGPARAM2 catweasel_bput (uaecptr addr, uae_u32 b)
{
addr -= catweasel_start & catweasel_mask;
addr &= catweasel_mask;
catweasel_do_bput (addr, b);
}
static int REGPARAM2 catweasel_check (uaecptr addr, uae_u32 size)
{
return 0;
}
static uae_u8 *REGPARAM2 catweasel_xlate (uaecptr addr)
{
write_log (_T("catweasel_xlate @%08X size %08X\n"), addr);
return 0;
}
static addrbank catweasel_bank = {
catweasel_lget, catweasel_wget, catweasel_bget,
catweasel_lput, catweasel_wput, catweasel_bput,
catweasel_xlate, catweasel_check, NULL, NULL, _T("Catweasel"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO, S_READ, S_WRITE
};
static addrbank *expamem_map_catweasel(struct autoconfig_info *aci)
{
catweasel_start = expamem_board_pointer;
map_banks_z2(&catweasel_bank, catweasel_start >> 16, 1);
return &catweasel_bank;
}
static bool expamem_init_catweasel (struct autoconfig_info *aci)
{
uae_u8 productid = cwc.type >= CATWEASEL_TYPE_MK3 ? 66 : 200;
uae_u16 vendorid = cwc.type >= CATWEASEL_TYPE_MK3 ? 4626 : 5001;
catweasel_mask = (cwc.type >= CATWEASEL_TYPE_MK3) ? 0xffff : 0x1ffff;
expamem_init_clear ();
expamem_write (0x00, (cwc.type >= CATWEASEL_TYPE_MK3 ? Z2_MEM_64KB : Z2_MEM_128KB) | zorroII);
expamem_write (0x04, productid);
expamem_write (0x08, 0);
expamem_write (0x10, vendorid >> 8);
expamem_write (0x14, vendorid & 0xff);
expamem_write (0x18, 0x00); /* ser.no. Byte 0 */
expamem_write (0x1c, 0x00); /* ser.no. Byte 1 */
expamem_write (0x20, 0x00); /* ser.no. Byte 2 */
expamem_write (0x24, 0x00); /* ser.no. Byte 3 */
expamem_write (0x28, 0x00); /* Rom-Offset hi */
expamem_write (0x2c, 0x00); /* ROM-Offset lo */
expamem_write (0x40, 0x00); /* Ctrl/Statusreg.*/
memcpy(aci->autoconfig_raw, expamem, sizeof aci->autoconfig_raw);
expamem_map = expamem_map_catweasel;
return true;
}
#endif
#ifdef FILESYS
/*
@ -834,8 +1033,8 @@ addrbank filesys_bank = {
filesys_lget, filesys_wget, filesys_bget,
filesys_lput, filesys_wput, filesys_bput,
filesys_xlate, filesys_check, NULL, _T("*"), _T("Filesystem autoconfig"),
filesys_wget,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
filesys_lget, filesys_wget,
ABFLAG_IO | ABFLAG_SAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
static bool filesys_write(uaecptr addr)
@ -845,32 +1044,41 @@ static bool filesys_write(uaecptr addr)
static uae_u32 REGPARAM2 filesys_lget (uaecptr addr)
{
uae_u8 *m;
addr -= filesys_bank.start;
addr &= 65535;
m = filesys_bank.baseaddr + addr;
return do_get_mem_long ((uae_u32 *)m);
uae_u8 *m;
addr -= filesys_bank.start & 65535;
addr &= 65535;
m = filesys_bank.baseaddr + addr;
#if EXP_DEBUG
write_log (_T("filesys_lget %x %x\n"), addr, do_get_mem_long ((uae_u32 *)m));
#endif
return do_get_mem_long ((uae_u32 *)m);
}
static uae_u32 REGPARAM2 filesys_wget (uaecptr addr)
{
uae_u8 *m;
addr -= filesys_bank.start;
addr &= 65535;
m = filesys_bank.baseaddr + addr;
return do_get_mem_word ((uae_u16 *)m);
uae_u8 *m;
addr -= filesys_bank.start & 65535;
addr &= 65535;
m = filesys_bank.baseaddr + addr;
#if EXP_DEBUG
write_log (_T("filesys_wget %x %x\n"), addr, do_get_mem_word ((uae_u16 *)m));
#endif
return do_get_mem_word ((uae_u16 *)m);
}
static uae_u32 REGPARAM2 filesys_bget (uaecptr addr)
{
addr -= filesys_bank.start;
addr &= 65535;
return filesys_bank.baseaddr[addr];
addr -= filesys_bank.start & 65535;
addr &= 65535;
#if EXP_DEBUG
write_log (_T("filesys_bget %x %x\n"), addr, filesys_bank.baseaddr[addr]);
#endif
return filesys_bank.baseaddr[addr];
}
static void REGPARAM2 filesys_bput(uaecptr addr, uae_u32 b)
{
addr -= filesys_bank.start;
addr -= filesys_bank.start & 65535;
addr &= 65535;
if (!filesys_write(addr))
return;
@ -879,7 +1087,7 @@ static void REGPARAM2 filesys_bput(uaecptr addr, uae_u32 b)
static void REGPARAM2 filesys_lput (uaecptr addr, uae_u32 l)
{
addr -= filesys_bank.start;
addr -= filesys_bank.start & 65535;
addr &= 65535;
if (!filesys_write(addr))
return;
@ -891,7 +1099,7 @@ static void REGPARAM2 filesys_lput (uaecptr addr, uae_u32 l)
static void REGPARAM2 filesys_wput (uaecptr addr, uae_u32 w)
{
addr -= filesys_bank.start;
addr -= filesys_bank.start & 65535;
addr &= 65535;
if (!filesys_write(addr))
return;
@ -901,13 +1109,13 @@ static void REGPARAM2 filesys_wput (uaecptr addr, uae_u32 w)
static int REGPARAM2 filesys_check(uaecptr addr, uae_u32 size)
{
addr -= filesys_bank.start;
addr -= filesys_bank.start & 65535;
addr &= 65535;
return (addr + size) <= filesys_bank.allocated_size;
}
static uae_u8 *REGPARAM2 filesys_xlate(uaecptr addr)
{
addr -= filesys_bank.start;
addr -= filesys_bank.start & 65535;
addr &= 65535;
return filesys_bank.baseaddr + addr;
}
@ -919,13 +1127,41 @@ addrbank uaeboard_bank = {
uaeboard_lget, uaeboard_wget, uaeboard_bget,
uaeboard_lput, uaeboard_wput, uaeboard_bput,
uaeboard_xlate, uaeboard_check, NULL, _T("*"), _T("UAE Board"),
dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
static uae_u32 uaeboard_base; /* Determined by the OS */
uae_u32 uaeboard_base; /* Determined by the OS */
static uae_u32 uaeboard_ram_start;
#define UAEBOARD_WRITEOFFSET 0x4000
uae_u8* uaeboard_map_ram(uaecptr p)
{
if (currprefs.uaeboard > 1) {
p -= uaeboard_base;
return uaeboard_bank.baseaddr + p;
} else {
p -= filesys_bank.start;
return filesys_bank.baseaddr + p;
}
}
uaecptr uaeboard_alloc_ram(uae_u32 size)
{
uaecptr p;
size += 7;
size &= ~7;
if (currprefs.uaeboard > 1) {
p = uaeboard_ram_start + uaeboard_base;
memset(uaeboard_bank.baseaddr + uaeboard_ram_start, 0, size);
} else {
p = uaeboard_ram_start + filesys_bank.start;
memset(filesys_bank.baseaddr + uaeboard_ram_start, 0, size);
}
uaeboard_ram_start += size;
return p;
}
static bool uaeboard_write(uaecptr addr)
{
if (addr >= UAEBOARD_WRITEOFFSET)
@ -1004,8 +1240,14 @@ static uae_u8 *REGPARAM2 uaeboard_xlate(uaecptr addr)
static addrbank *expamem_map_uaeboard(struct autoconfig_info *aci)
{
uaeboard_base = expamem_board_pointer;
uaeboard_ram_start = UAEBOARD_WRITEOFFSET;
uaeboard_bank.start = uaeboard_base;
map_banks_z2(&uaeboard_bank, uaeboard_base >> 16, 1);
if (currprefs.uaeboard > 1) {
rtarea_bank.start = uaeboard_base + 65536;
map_banks_z2(&rtarea_bank, (uaeboard_base + 65536) >> 16, 1);
ce_cachable[(uaeboard_base + 65536) >> 16] = CACHE_DISABLE_ALLOCATE;
}
return &uaeboard_bank;
}
@ -1076,6 +1318,9 @@ static bool expamem_init_uaeboard(struct autoconfig_info *aci)
*/
MEMORY_ARRAY_FUNCTIONS(z3fastmem, 0);
MEMORY_ARRAY_FUNCTIONS(z3fastmem, 1);
MEMORY_ARRAY_FUNCTIONS(z3fastmem, 2);
MEMORY_ARRAY_FUNCTIONS(z3fastmem, 3);
addrbank z3fastmem_bank[MAX_RAM_BOARDS] =
{
@ -1083,9 +1328,40 @@ addrbank z3fastmem_bank[MAX_RAM_BOARDS] =
z3fastmem0_lget, z3fastmem0_wget, z3fastmem0_bget,
z3fastmem0_lput, z3fastmem0_wput, z3fastmem0_bput,
z3fastmem0_xlate, z3fastmem0_check, NULL, _T("*"), _T("Zorro III Fast RAM"),
z3fastmem0_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE, 0, 0
}
z3fastmem0_lget, z3fastmem0_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
z3fastmem1_lget, z3fastmem1_wget, z3fastmem1_bget,
z3fastmem1_lput, z3fastmem1_wput, z3fastmem1_bput,
z3fastmem1_xlate, z3fastmem1_check, NULL, _T("*"), _T("Zorro III Fast RAM #2"),
z3fastmem1_lget, z3fastmem1_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
z3fastmem2_lget, z3fastmem2_wget, z3fastmem2_bget,
z3fastmem2_lput, z3fastmem2_wput, z3fastmem2_bput,
z3fastmem2_xlate, z3fastmem2_check, NULL, _T("*"), _T("Zorro III Fast RAM #3"),
z3fastmem2_lget, z3fastmem2_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
},
{
z3fastmem3_lget, z3fastmem3_wget, z3fastmem3_bget,
z3fastmem3_lput, z3fastmem3_wput, z3fastmem3_bput,
z3fastmem3_xlate, z3fastmem3_check, NULL, _T("*"), _T("Zorro III Fast RAM #4"),
z3fastmem3_lget, z3fastmem3_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL | ABFLAG_DIRECTACCESS, 0, 0
}
};
MEMORY_FUNCTIONS(z3chipmem);
addrbank z3chipmem_bank = {
z3chipmem_lget, z3chipmem_wget, z3chipmem_bget,
z3chipmem_lput, z3chipmem_wput, z3chipmem_bput,
z3chipmem_xlate, z3chipmem_check, NULL, _T("*"), _T("MegaChipRAM"),
z3chipmem_lget, z3chipmem_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL, 0, 0
};
/* ********************************************************** */
@ -1201,6 +1477,17 @@ static bool fastmem_autoconfig(struct uae_prefs *p, struct autoconfig_info *aci,
return true;
}
static const uae_u8 a2630_autoconfig[] = { 0xe7, 0x51, 0x40, 0x00, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
static bool megachipram_init(struct autoconfig_info *aci)
{
aci->zorro = 0;
aci->start = 0x10000000;
aci->size = aci->prefs->z3chipmem_size;
aci->label = _T("32-bit Chip RAM");
return true;
}
static bool expamem_init_fastcard_2(struct autoconfig_info *aci, int zorro)
{
struct uae_prefs *p = aci->prefs;
@ -1731,6 +2018,21 @@ static void add_expansions(struct uae_prefs *p, int zorro, int *fastmem_nump, in
*fastmem_nump = fastmem_num;
}
uae_u32 expansion_board_size(addrbank* ab)
{
uae_u32 size = 0;
uae_u8 code = (ab->bget(0) & 0xf0) | ((ab->bget(2) & 0xf0) >> 4);
if ((code & 0xc0) == zorroII) {
// Z2
code &= 7;
if (code == 0)
size = 8 * 1024 * 1024;
else
size = 32768 << code;
}
return size;
}
static uae_u8 autoconfig_read(const uae_u8 *autoconfig, int offset)
{
uae_u8 b = (autoconfig[offset] & 0xf0) | (autoconfig[offset + 2] >> 4);

12
src/gayle.cpp
View file

@ -472,7 +472,7 @@ addrbank gayle_bank = {
gayle_lget, gayle_wget, gayle_bget,
gayle_lput, gayle_wput, gayle_bput,
default_xlate, default_check, NULL, NULL, _T("Gayle (low)"),
dummy_wgeti,
dummy_lgeti, dummy_wgeti,
ABFLAG_IO, S_READ, S_WRITE
};
@ -569,7 +569,7 @@ addrbank gayle2_bank = {
gayle2_lget, gayle2_wget, gayle2_bget,
gayle2_lput, gayle2_wput, gayle2_bput,
default_xlate, default_check, NULL, NULL, _T("Gayle (high)"),
dummy_wgeti,
dummy_lgeti, dummy_wgeti,
ABFLAG_IO, S_READ, S_WRITE
};
@ -715,7 +715,7 @@ static addrbank mbres_sub_bank = {
mbres_lget, mbres_wget, mbres_bget,
mbres_lput, mbres_wput, mbres_bput,
default_xlate, default_check, NULL, NULL, _T("Motherboard Resources"),
dummy_wgeti,
dummy_lgeti, dummy_wgeti,
ABFLAG_IO, S_READ, S_WRITE
};
@ -729,7 +729,7 @@ addrbank mbres_bank = {
sub_bank_lget, sub_bank_wget, sub_bank_bget,
sub_bank_lput, sub_bank_wput, sub_bank_bput,
sub_bank_xlate, sub_bank_check, NULL, NULL, _T("Motherboard Resources"),
sub_bank_wgeti,
sub_bank_lgeti, sub_bank_wgeti,
ABFLAG_IO, S_READ, S_WRITE, mbres_sub_banks
};
@ -1244,7 +1244,7 @@ static addrbank gayle_common_bank = {
gayle_common_lget, gayle_common_wget, gayle_common_bget,
gayle_common_lput, gayle_common_wput, gayle_common_bput,
gayle_common_xlate, gayle_common_check, NULL, NULL, _T("Gayle PCMCIA Common"),
gayle_common_wget,
gayle_common_lget, gayle_common_wget,
ABFLAG_RAM | ABFLAG_SAFE, S_READ, S_WRITE
};
@ -1260,7 +1260,7 @@ static addrbank gayle_attr_bank = {
gayle_attr_lget, gayle_attr_wget, gayle_attr_bget,
gayle_attr_lput, gayle_attr_wput, gayle_attr_bput,
default_xlate, default_check, NULL, NULL, _T("Gayle PCMCIA Attribute/Misc"),
dummy_wgeti,
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};

3
src/include/autoconf.h
View file

@ -144,10 +144,13 @@ extern void expansion_init (void);
extern void expansion_cleanup (void);
extern void expansion_clear (void);
extern uaecptr expansion_startaddress(struct uae_prefs*, uaecptr addr, uae_u32 size);
extern uaecptr uaeboard_alloc_ram(uae_u32);
extern uae_u8* uaeboard_map_ram(uaecptr);
extern void expansion_scan_autoconfig(struct uae_prefs*, bool);
extern void expansion_generate_autoconfig_info(struct uae_prefs *p);
extern struct autoconfig_info *expansion_get_autoconfig_by_address(struct uae_prefs *p, uaecptr addr);
extern void expansion_map(void);
extern uae_u32 expansion_board_size(addrbank* ab);
extern void uaegfx_install_code (uaecptr);

2
src/include/gayle.h
View file

@ -14,7 +14,7 @@ void pcmcia_reinsert(struct uae_prefs*);
bool pcmcia_disk_reinsert(struct uae_prefs *p, struct uaedev_config_info *uci, bool ejectonly);
extern int gary_toenb; // non-existing memory access = bus error.
//extern int gary_timeout; // non-existing memory access = delay
extern int gary_timeout; // non-existing memory access = delay
#define PCMCIA_COMMON_START 0x600000
#define PCMCIA_COMMON_SIZE 0x400000

399
src/include/memory.h
View file

@ -22,6 +22,9 @@ extern int special_mem;
bool init_shm (void);
void free_shm (void);
bool preinit_shm (void);
extern bool canbang;
extern bool jit_direct_compatible_memory;
#define Z3BASE_UAE 0x10000000
#define Z3BASE_REAL 0x40000000
@ -32,8 +35,10 @@ void free_shm (void);
#ifdef ADDRESS_SPACE_24BIT
#define MEMORY_BANKS 256
#define MEMORY_RANGE_MASK ((1<<24)-1)
#else
#define MEMORY_BANKS 65536
#define MEMORY_RANGE_MASK (~0)
#endif
typedef uae_u32 (REGPARAM3 *mem_get_func)(uaecptr) REGPARAM;
@ -43,6 +48,12 @@ typedef int (REGPARAM3 *check_func)(uaecptr, uae_u32) REGPARAM;
extern uae_u32 max_z3fastmem;
extern uae_u32 wait_cpu_cycle_read (uaecptr addr, int mode);
extern void wait_cpu_cycle_write (uaecptr addr, int mode, uae_u32 v);
extern uae_u32 wait_cpu_cycle_read_ce020 (uaecptr addr, int mode);
extern void wait_cpu_cycle_write_ce020 (uaecptr addr, int mode, uae_u32 v);
#undef DIRECT_MEMFUNCS_SUCCESSFUL
#include "machdep/maccess.h"
#define chipmem_start_addr 0x00000000
@ -54,19 +65,45 @@ extern uae_u32 max_z3fastmem;
#define ROM_SIZE_256 262144
#define ROM_SIZE_128 131072
extern bool ersatzkickfile;
extern bool cloanto_rom, kickstart_rom;
extern uae_u16 kickstart_version;
extern int uae_boot_rom_type;
extern int uae_boot_rom_size;
extern uaecptr rtarea_base;
extern uaecptr uaeboard_base;
extern uae_u8* baseaddr[];
#define CACHE_ENABLE_DATA 0x01
#define CACHE_ENABLE_DATA_BURST 0x02
#define CACHE_ENABLE_COPYBACK 0x020
#define CACHE_ENABLE_INS 0x80
#define CACHE_ENABLE_INS_BURST 0x40
#define CACHE_ENABLE_BOTH (CACHE_ENABLE_DATA | CACHE_ENABLE_INS)
#define CACHE_ENABLE_ALL (CACHE_ENABLE_BOTH | CACHE_ENABLE_INS_BURST | CACHE_ENABLE_DATA_BURST)
#define CACHE_DISABLE_ALLOCATE 0x08
#define CACHE_DISABLE_MMU 0x10
extern uae_u8 ce_banktype[65536], ce_cachable[65536];
#define ABFLAG_CACHE_SHIFT 24
enum
{
ABFLAG_UNK = 0, ABFLAG_RAM = 1, ABFLAG_ROM = 2, ABFLAG_ROMIN = 4, ABFLAG_IO = 8,
ABFLAG_NONE = 16, ABFLAG_SAFE = 32, ABFLAG_INDIRECT = 64, ABFLAG_NOALLOC = 128,
ABFLAG_RTG = 256, ABFLAG_THREADSAFE = 512, ABFLAG_DIRECTMAP = 1024, ABFLAG_ALLOCINDIRECT = 2048,
ABFLAG_CHIPRAM = 4096, ABFLAG_CIA = 8192, ABFLAG_PPCIOSPACE = 16384
ABFLAG_CHIPRAM = 4096, ABFLAG_CIA = 8192, ABFLAG_PPCIOSPACE = 16384,
ABFLAG_MAPPED = 32768,
ABFLAG_DIRECTACCESS = 65536,
ABFLAG_CACHE_ENABLE_DATA = CACHE_ENABLE_DATA << ABFLAG_CACHE_SHIFT,
ABFLAG_CACHE_ENABLE_DATA_BURST = CACHE_ENABLE_DATA_BURST << ABFLAG_CACHE_SHIFT,
ABFLAG_CACHE_ENABLE_INS = CACHE_ENABLE_INS << ABFLAG_CACHE_SHIFT,
ABFLAG_CACHE_ENABLE_INS_BURST = CACHE_ENABLE_INS_BURST << ABFLAG_CACHE_SHIFT,
};
#define ABFLAG_CACHE_ENABLE_BOTH (ABFLAG_CACHE_ENABLE_DATA | ABFLAG_CACHE_ENABLE_INS)
#define ABFLAG_CACHE_ENABLE_ALL (ABFLAG_CACHE_ENABLE_BOTH | ABFLAG_CACHE_ENABLE_INS_BURST | ABFLAG_CACHE_ENABLE_DATA_BURST)
typedef struct {
/* These ones should be self-explanatory... */
mem_get_func lget, wget, bget;
@ -85,20 +122,25 @@ typedef struct {
of going through function calls, and instead simply grab the memory
ourselves. This holds the memory address where the start of memory is
for this particular bank. */
uae_u8 *baseaddr;
const TCHAR *label;
const TCHAR *name;
/* for instruction opcode/operand fetches */
mem_get_func wgeti;
int flags;
uae_u8* baseaddr;
const TCHAR* label;
const TCHAR* name;
/* for instruction opcode/operand fetches */
mem_get_func lgeti, wgeti;
int flags;
int jit_read_flag, jit_write_flag;
struct addrbank_sub *sub_banks;
struct addrbank_sub* sub_banks;
uae_u32 mask;
uae_u32 startmask;
uae_u32 start;
// if RAM: size of allocated RAM. Zero if failed.
uae_u32 allocated_size;
// size of bank (if IO or before RAM allocation)
uae_u32 reserved_size;
/* non-NULL if xget/xput can be bypassed */
uae_u8 *baseaddr_direct_r;
uae_u8 *baseaddr_direct_w;
uae_u32 startaccessmask;
} addrbank;
#define MEMORY_MIN_SUBBANK 1024
@ -113,30 +155,71 @@ struct addrbank_sub
struct autoconfig_info
{
struct uae_prefs *prefs;
struct uae_prefs* prefs;
bool doinit;
bool postinit;
int devnum;
uae_u8 autoconfig_raw[128];
uae_u8 autoconfig_bytes[16];
TCHAR name[128];
const uae_u8 *autoconfigp;
bool autoconfig_automatic;
uae_u32 start;
uae_u32 size;
int zorro;
const TCHAR *label;
addrbank *addrbankp;
const TCHAR* label;
addrbank* addrbankp;
uaecptr write_bank_address;
struct romconfig *rc;
uae_u32 last_high_ram;
const struct cpuboardsubtype *cst;
const struct expansionromtype *ert;
struct autoconfig_info *parent;
const int *parent_romtype;
bool parent_of_previous;
bool parent_address_space;
bool direct_vram;
const TCHAR *parent_name;
bool can_sort;
bool hardwired;
bool (*get_params)(struct uae_prefs*, struct expansion_params*);
bool (*set_params)(struct uae_prefs*, struct expansion_params*);
void *userdata;
};
#define CE_MEMBANK_FAST32 0
#define CE_MEMBANK_CHIP16 1
#define CE_MEMBANK_CHIP32 2
#define CE_MEMBANK_CIA 3
#define CE_MEMBANK_FAST16 4
//#define CE_MEMBANK_FAST16_EXTRA_ACCURACY 5
#define MEMORY_LGETI(name) \
static uae_u32 REGPARAM3 name ## _lgeti (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## _lgeti (uaecptr addr) \
{ \
uae_u8 *m; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
return do_get_mem_long ((uae_u32 *)m); \
}
#define MEMORY_WGETI(name) \
static uae_u32 REGPARAM3 name ## _wgeti (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## _wgeti (uaecptr addr) \
{ \
uae_u8 *m; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
return do_get_mem_word ((uae_u16 *)m); \
}
#define MEMORY_LGET(name) \
static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## _lget (uaecptr addr) \
{ \
uae_u8 *m; \
addr -= name ## _bank.start; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
return do_get_mem_long ((uae_u32 *)m); \
@ -146,7 +229,7 @@ static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## _wget (uaecptr addr) \
{ \
uae_u8 *m; \
addr -= name ## _bank.start; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
return do_get_mem_word ((uae_u16 *)m); \
@ -155,7 +238,7 @@ static uae_u32 REGPARAM2 name ## _wget (uaecptr addr) \
static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## _bget (uaecptr addr) \
{ \
addr -= name ## _bank.start; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
return name ## _bank.baseaddr[addr]; \
}
@ -164,7 +247,7 @@ static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## _lput (uaecptr addr, uae_u32 l) \
{ \
uae_u8 *m; \
addr -= name ## _bank.start; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
do_put_mem_long ((uae_u32 *)m, l); \
@ -174,7 +257,7 @@ static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## _wput (uaecptr addr, uae_u32 w) \
{ \
uae_u8 *m; \
addr -= name ## _bank.start; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
do_put_mem_word ((uae_u16 *)m, w); \
@ -183,7 +266,7 @@ static void REGPARAM2 name ## _wput (uaecptr addr, uae_u32 w) \
static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## _bput (uaecptr addr, uae_u32 b) \
{ \
addr -= name ## _bank.start; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
name ## _bank.baseaddr[addr] = b; \
}
@ -191,7 +274,7 @@ static void REGPARAM2 name ## _bput (uaecptr addr, uae_u32 b) \
static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
static int REGPARAM2 name ## _check (uaecptr addr, uae_u32 size) \
{ \
addr -= name ## _bank.start; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
return (addr + size) <= name ## _bank.allocated_size; \
}
@ -199,13 +282,14 @@ static int REGPARAM2 name ## _check (uaecptr addr, uae_u32 size) \
static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM; \
static uae_u8 *REGPARAM2 name ## _xlate (uaecptr addr) \
{ \
addr -= name ## _bank.start; \
addr -= name ## _bank.startaccessmask; \
addr &= name ## _bank.mask; \
return name ## _bank.baseaddr + addr; \
}
#define DECLARE_MEMORY_FUNCTIONS(name) \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _lget) (uaecptr) REGPARAM; \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _lgeti) (uaecptr) REGPARAM; \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _wget) (uaecptr) REGPARAM; \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _wgeti) (uaecptr) REGPARAM; \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _bget) (uaecptr) REGPARAM; \
@ -215,6 +299,18 @@ static void REGPARAM3 NOWARN_UNUSED(name ## _bput) (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 NOWARN_UNUSED(name ## _check) (uaecptr addr, uae_u32 size) REGPARAM; \
static uae_u8 *REGPARAM3 NOWARN_UNUSED(name ## _xlate) (uaecptr addr) REGPARAM;
#define DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(name, suffix) \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _lget_ ## suffix) (uaecptr) REGPARAM; \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _lgeti_ ## suffix) (uaecptr) REGPARAM; \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _wget_ ## suffix) (uaecptr) REGPARAM; \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _wgeti_ ## suffix) (uaecptr) REGPARAM; \
static uae_u32 REGPARAM3 NOWARN_UNUSED(name ## _bget_ ## suffix) (uaecptr) REGPARAM; \
static void REGPARAM3 NOWARN_UNUSED(name ## _lput_ ## suffix) (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM3 NOWARN_UNUSED(name ## _wput_ ## suffix) (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM3 NOWARN_UNUSED(name ## _bput_ ## suffix) (uaecptr, uae_u32) REGPARAM; \
static int REGPARAM3 NOWARN_UNUSED(name ## _check_ ## suffix) (uaecptr addr, uae_u32 size) REGPARAM; \
static uae_u8 *REGPARAM3 NOWARN_UNUSED(name ## _xlate_ ## suffix) (uaecptr addr) REGPARAM;
#define MEMORY_FUNCTIONS(name) \
MEMORY_LGET(name); \
MEMORY_WGET(name); \
@ -225,12 +321,13 @@ MEMORY_BPUT(name); \
MEMORY_CHECK(name); \
MEMORY_XLATE(name);
#define MEMORY_ARRAY_LGET(name, index) \
static uae_u32 REGPARAM3 name ## index ## _lget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## index ## _lget (uaecptr addr) \
{ \
uae_u8 *m; \
addr -= name ## _bank[index].start; \
addr -= name ## _bank[index].startaccessmask; \
addr &= name ## _bank[index].mask; \
m = name ## _bank[index].baseaddr + addr; \
return do_get_mem_long ((uae_u32 *)m); \
@ -240,7 +337,7 @@ static uae_u32 REGPARAM3 name ## index ## _wget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## index ## _wget (uaecptr addr) \
{ \
uae_u8 *m; \
addr -= name ## _bank[index].start; \
addr -= name ## _bank[index].startaccessmask; \
addr &= name ## _bank[index].mask; \
m = name ## _bank[index].baseaddr + addr; \
return do_get_mem_word ((uae_u16 *)m); \
@ -249,7 +346,7 @@ static uae_u32 REGPARAM2 name ## index ## _wget (uaecptr addr) \
static uae_u32 REGPARAM3 name ## index ## _bget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## index ## _bget (uaecptr addr) \
{ \
addr -= name ## _bank[index].start; \
addr -= name ## _bank[index].startaccessmask; \
addr &= name ## _bank[index].mask; \
return name ## _bank[index].baseaddr[addr]; \
}
@ -258,7 +355,7 @@ static void REGPARAM3 name ## index ## _lput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## index ## _lput (uaecptr addr, uae_u32 l) \
{ \
uae_u8 *m; \
addr -= name ## _bank[index].start; \
addr -= name ## _bank[index].startaccessmask; \
addr &= name ## _bank[index].mask; \
m = name ## _bank[index].baseaddr + addr; \
do_put_mem_long ((uae_u32 *)m, l); \
@ -268,7 +365,7 @@ static void REGPARAM3 name ## index ## _wput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## index ## _wput (uaecptr addr, uae_u32 w) \
{ \
uae_u8 *m; \
addr -= name ## _bank[index].start; \
addr -= name ## _bank[index].startaccessmask; \
addr &= name ## _bank[index].mask; \
m = name ## _bank[index].baseaddr + addr; \
do_put_mem_word ((uae_u16 *)m, w); \
@ -277,7 +374,7 @@ static void REGPARAM2 name ## index ## _wput (uaecptr addr, uae_u32 w) \
static void REGPARAM3 name ## index ## _bput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## index ## _bput (uaecptr addr, uae_u32 b) \
{ \
addr -= name ## _bank[index].start; \
addr -= name ## _bank[index].startaccessmask; \
addr &= name ## _bank[index].mask; \
name ## _bank[index].baseaddr[addr] = b; \
}
@ -285,7 +382,7 @@ static void REGPARAM2 name ## index ## _bput (uaecptr addr, uae_u32 b) \
static int REGPARAM3 name ## index ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
static int REGPARAM2 name ## index ## _check (uaecptr addr, uae_u32 size) \
{ \
addr -= name ## _bank[index].start; \
addr -= name ## _bank[index].startaccessmask; \
addr &= name ## _bank[index].mask; \
return (addr + size) <= name ## _bank[index].allocated_size; \
}
@ -293,7 +390,7 @@ static int REGPARAM2 name ## index ## _check (uaecptr addr, uae_u32 size) \
static uae_u8 *REGPARAM3 name ## index ## _xlate (uaecptr addr) REGPARAM; \
static uae_u8 *REGPARAM2 name ## index ## _xlate (uaecptr addr) \
{ \
addr -= name ## _bank[index].start; \
addr -= name ## _bank[index].startaccessmask; \
addr &= name ## _bank[index].mask; \
return name ## _bank[index].baseaddr + addr; \
}
@ -309,6 +406,8 @@ MEMORY_ARRAY_CHECK(name, index); \
MEMORY_ARRAY_XLATE(name, index);
extern addrbank chipmem_bank;
extern addrbank chipmem_agnus_bank;
extern addrbank chipmem_bank_ce2;
extern addrbank kickmem_bank;
extern addrbank custom_bank;
extern addrbank clock_bank;
@ -317,40 +416,55 @@ extern addrbank rtarea_bank;
extern addrbank filesys_bank;
extern addrbank uaeboard_bank;
extern addrbank expamem_bank;
extern addrbank expamem_null;
extern addrbank expamem_null, expamem_none;
extern addrbank fastmem_bank[MAX_RAM_BOARDS];
extern addrbank *gfxmem_banks[MAX_RTG_BOARDS];
extern addrbank fastmem_nojit_bank[MAX_RAM_BOARDS];
extern addrbank* gfxmem_banks[MAX_RTG_BOARDS];
extern addrbank gayle_bank;
extern addrbank gayle2_bank;
extern addrbank mbres_bank;
extern addrbank akiko_bank;
extern addrbank cardmem_bank;
extern addrbank bogomem_bank;
extern addrbank z3fastmem_bank[MAX_RAM_BOARDS];
extern addrbank z3chipmem_bank;
extern addrbank mem25bit_bank;
extern addrbank debugmem_bank;
extern addrbank a3000lmem_bank;
extern addrbank a3000hmem_bank;
extern addrbank extendedkickmem_bank;
extern addrbank extendedkickmem2_bank;
extern addrbank custmem1_bank;
extern addrbank custmem2_bank;
extern addrbank romboardmem_bank[MAX_ROM_BOARDS];
extern void rtarea_init(void);
extern void rtarea_free(void);
extern void rtarea_setup (void);
extern void rtarea_init_mem(void);
extern void rtarea_setup(void);
extern void expamem_reset(int);
extern void expamem_next(addrbank* mapped, addrbank* next);
extern void expamem_shutup(addrbank* mapped);
extern bool expamem_z3hack(struct uae_prefs*);
extern void expansion_cpu_fallback(void);
extern void set_expamem_z3_hack_mode(int);
extern uaecptr expamem_board_pointer;
extern uaecptr expamem_board_pointer, expamem_highmem_pointer;
extern uaecptr expamem_z3_pointer_real, expamem_z3_pointer_uae;
extern uae_u32 expamem_z3_highram_real, expamem_z3_highram_uae;
extern uae_u32 expamem_board_size;
extern uae_u32 last_custom_value1;
/* Default memory access functions */
extern void dummy_put (uaecptr addr, int size, uae_u32 val);
extern uae_u32 dummy_get (uaecptr addr, int size, bool inst, uae_u32 defvalue);
extern uae_u32 dummy_get_safe(uaecptr addr, int size, bool inst, uae_u32 defvalue);
extern int REGPARAM3 default_check(uaecptr addr, uae_u32 size) REGPARAM;
extern uae_u8 *REGPARAM3 default_xlate(uaecptr addr) REGPARAM;
/* 680x0 opcode fetches */
extern uae_u32 REGPARAM3 dummy_lgeti (uaecptr addr) REGPARAM;
extern uae_u32 REGPARAM3 dummy_wgeti (uaecptr addr) REGPARAM;
/* sub bank support */
@ -360,6 +474,7 @@ extern uae_u32 REGPARAM3 sub_bank_bget(uaecptr) REGPARAM;
extern void REGPARAM3 sub_bank_lput(uaecptr, uae_u32) REGPARAM;
extern void REGPARAM3 sub_bank_wput(uaecptr, uae_u32) REGPARAM;
extern void REGPARAM3 sub_bank_bput(uaecptr, uae_u32) REGPARAM;
extern uae_u32 REGPARAM3 sub_bank_lgeti(uaecptr) REGPARAM;
extern uae_u32 REGPARAM3 sub_bank_wgeti(uaecptr) REGPARAM;
extern int REGPARAM3 sub_bank_check(uaecptr addr, uae_u32 size) REGPARAM;
extern uae_u8 *REGPARAM3 sub_bank_xlate(uaecptr addr) REGPARAM;
@ -369,40 +484,72 @@ extern addrbank *get_sub_bank(uaecptr *addr);
extern addrbank *mem_banks[MEMORY_BANKS];
#ifdef JIT
extern uae_u8* baseaddr[MEMORY_BANKS];
#endif
#define get_mem_bank(addr) (*mem_banks[bankindex(addr)])
extern addrbank* get_mem_bank_real(uaecptr);
extern void memory_cleanup (void);
extern void map_banks (addrbank *bank, int first, int count, int realsize);
extern void map_banks_z2 (addrbank *bank, int first, int count);
extern void map_banks_z3(addrbank *bank, int first, int count);
extern bool validate_banks_z2(addrbank *bank, int start, int size);
extern void map_banks_cond (addrbank *bank, int first, int count, int realsize);
extern void map_overlay (int chip);
extern void memory_hardreset (int);
extern void memory_clear (void);
extern void free_fastmemory (int);
extern bool read_kickstart_version(struct uae_prefs *p);
#ifdef JIT
#define put_mem_bank(addr, b, realstart) do { \
(mem_banks[bankindex(addr)] = (b)); \
if ((b)->baseaddr) \
baseaddr[bankindex(addr)] = (b)->baseaddr - (realstart); \
else \
baseaddr[bankindex(addr)] = (uae_u8*)(((uae_u8*)b)+1); \
} while (0)
#else
#define put_mem_bank(addr, b, realstart) \
(mem_banks[bankindex(addr)] = (b));
#endif
#define memory_get_long(addr) (call_mem_get_func(get_mem_bank(addr).lget, addr))
#define memory_get_word(addr) (call_mem_get_func(get_mem_bank(addr).wget, addr))
#define memory_get_byte(addr) (call_mem_get_func(get_mem_bank(addr).bget, addr))
#define memory_get_wordi(addr) (call_mem_get_func(get_mem_bank(addr).wgeti, addr))
extern void memory_init(void);
extern void memory_cleanup(void);
extern void restore_banks(void);
extern void map_banks(addrbank * bank, int first, int count, int realsize);
extern void map_banks_z2(addrbank * bank, int first, int count);
extern uae_u32 map_banks_z2_autosize(addrbank * bank, int first);
extern void map_banks_z3(addrbank * bank, int first, int count);
extern bool validate_banks_z2(addrbank * bank, int start, int size);
extern bool validate_banks_z3(addrbank * bank, int start, int size);
extern void map_banks_quick(addrbank * bank, int first, int count, int realsize);
extern void map_banks_nojitdirect(addrbank * bank, int first, int count, int realsize);
extern void map_banks_cond(addrbank * bank, int first, int count, int realsize);
extern void map_overlay(int chip);
extern void memory_hardreset(int);
extern void memory_clear(void);
extern void free_fastmemory(int);
extern void set_roms_modified(void);
extern void reload_roms(void);
extern bool read_kickstart_version(struct uae_prefs* p);
extern void chipmem_setindirect(void);
uae_u32 memory_get_long(uaecptr);
uae_u32 memory_get_word(uaecptr);
uae_u32 memory_get_byte(uaecptr);
uae_u32 memory_get_longi(uaecptr);
uae_u32 memory_get_wordi(uaecptr);
STATIC_INLINE uae_u32 get_long(uaecptr addr)
{
return memory_get_long(addr);
return memory_get_long(addr);
}
STATIC_INLINE uae_u32 get_word(uaecptr addr)
STATIC_INLINE uae_u32 get_word (uaecptr addr)
{
return memory_get_word(addr);
return memory_get_word(addr);
}
STATIC_INLINE uae_u32 get_byte(uaecptr addr)
STATIC_INLINE uae_u32 get_byte (uaecptr addr)
{
return memory_get_byte(addr);
return memory_get_byte(addr);
}
STATIC_INLINE uae_u32 get_longi(uaecptr addr)
{
return memory_get_longi(addr);
}
STATIC_INLINE uae_u32 get_wordi(uaecptr addr)
{
return memory_get_wordi(addr);
return memory_get_wordi(addr);
}
// do split memory access if it can cross memory banks
@ -435,30 +582,61 @@ STATIC_INLINE uae_u32 get_byte_compatible(uaecptr addr)
{
return memory_get_byte(addr);
}
STATIC_INLINE uae_u32 get_longi_compatible(uaecptr addr)
{
if ((addr & 0xffff) < 0xfffd) {
return memory_get_longi(addr);
} else {
uae_u16 v0 = memory_get_wordi(addr + 0);
uae_u16 v1 = memory_get_wordi(addr + 2);
return (v0 << 16) | (v1 << 0);
}
}
STATIC_INLINE uae_u32 get_wordi_compatible(uaecptr addr)
{
return memory_get_wordi(addr);
}
STATIC_INLINE uae_u32 get_long_jit(uaecptr addr)
{
addrbank *bank = &get_mem_bank(addr);
#ifdef JIT
addrbank *bank = &get_mem_bank(addr);
special_mem |= bank->jit_read_flag;
#endif
return bank->lget(addr);
return memory_get_long(addr);
}
STATIC_INLINE uae_u32 get_word_jit(uaecptr addr)
{
addrbank *bank = &get_mem_bank(addr);
#ifdef JIT
addrbank *bank = &get_mem_bank(addr);
special_mem |= bank->jit_read_flag;
#endif
return bank->wget(addr);
return memory_get_word(addr);
}
STATIC_INLINE uae_u32 get_byte_jit(uaecptr addr)
{
addrbank *bank = &get_mem_bank(addr);
#ifdef JIT
addrbank *bank = &get_mem_bank(addr);
special_mem |= bank->jit_read_flag;
#endif
return bank->bget(addr);
return memory_get_byte(addr);
}
STATIC_INLINE uae_u32 get_longi_jit(uaecptr addr)
{
#ifdef JIT
addrbank *bank = &get_mem_bank(addr);
special_mem |= bank->jit_read_flag;
#endif
return memory_get_longi(addr);
}
STATIC_INLINE uae_u32 get_wordi_jit(uaecptr addr)
{
#ifdef JIT
addrbank *bank = &get_mem_bank(addr);
special_mem |= bank->jit_read_flag;
#endif
return memory_get_wordi(addr);
}
/*
@ -470,26 +648,30 @@ STATIC_INLINE uae_u32 get_byte_jit(uaecptr addr)
# if SIZEOF_VOID_P == 8
STATIC_INLINE void *get_pointer (uaecptr addr)
{
const unsigned int n = SIZEOF_VOID_P / 4;
union {
void *ptr;
uae_u32 longs[SIZEOF_VOID_P / 4];
} p;
unsigned int i;
const unsigned int n = SIZEOF_VOID_P / 4;
union {
void *ptr;
uae_u32 longs[SIZEOF_VOID_P / 4];
} p;
unsigned int i;
for (i = 0; i < n; i++) {
p.longs[n - 1 - i] = get_long (addr + i * 4);
}
return p.ptr;
for (i = 0; i < n; i++) {
#ifdef WORDS_BIGENDIAN
p.longs[i] = get_long (addr + i * 4);
#else
p.longs[n - 1 - i] = get_long (addr + i * 4);
#endif
}
return p.ptr;
}
# else
# error "Unknown or unsupported pointer size."
# endif
#endif
#define memory_put_long(addr,l) (call_mem_put_func(get_mem_bank(addr).lput, addr, l))
#define memory_put_word(addr,w) (call_mem_put_func(get_mem_bank(addr).wput, addr, w))
#define memory_put_byte(addr,b) (call_mem_put_func(get_mem_bank(addr).bput, addr, b))
void memory_put_long(uaecptr, uae_u32);
void memory_put_word(uaecptr, uae_u32);
void memory_put_byte(uaecptr, uae_u32);
STATIC_INLINE void put_long (uaecptr addr, uae_u32 l)
{
@ -535,34 +717,34 @@ STATIC_INLINE void put_byte_compatible(uaecptr addr, uae_u32 b)
STATIC_INLINE void put_long_jit(uaecptr addr, uae_u32 l)
{
addrbank *bank = &get_mem_bank(addr);
#ifdef JIT
addrbank *bank = &get_mem_bank(addr);
special_mem |= bank->jit_write_flag;
#endif
bank->lput(addr, l);
memory_put_long(addr, l);
}
STATIC_INLINE void put_word_jit(uaecptr addr, uae_u32 l)
{
addrbank *bank = &get_mem_bank(addr);
#ifdef JIT
addrbank *bank = &get_mem_bank(addr);
special_mem |= bank->jit_write_flag;
#endif
bank->wput(addr, l);
memory_put_word(addr, l);
}
STATIC_INLINE void put_byte_jit(uaecptr addr, uae_u32 l)
{
addrbank *bank = &get_mem_bank(addr);
#ifdef JIT
addrbank *bank = &get_mem_bank(addr);
special_mem |= bank->jit_write_flag;
#endif
bank->bput(addr, l);
memory_put_byte(addr, l);
}
/*
* Store host pointer v at addr
*/
#if SIZEOF_VOID_P == 4
# define put_pointer(addr, p) (put_long((addr), (uae_u32)(p)))
# define put_pointer(addr, p) (put_long ((addr), (uae_u32)(p)))
#else
# if SIZEOF_VOID_P == 8
STATIC_INLINE void put_pointer (uaecptr addr, void *v)
@ -574,25 +756,38 @@ STATIC_INLINE void put_pointer (uaecptr addr, void *v)
} p;
unsigned int i;
p.ptr = v;
p.ptr = v;
for (i = 0; i < n; i++) {
put_long (addr + i * 4, p.longs[n - 1 - i]);
}
for (i = 0; i < n; i++) {
#ifdef WORDS_BIGENDIAN
put_long (addr + i * 4, p.longs[i]);
#else
put_long (addr + i * 4, p.longs[n - 1 - i]);
#endif
}
}
# endif
#endif
STATIC_INLINE uae_u8 *get_real_address(uaecptr addr)
bool real_address_allowed(void);
uae_u8* memory_get_real_address(uaecptr);
int memory_valid_address(uaecptr, uae_u32);
STATIC_INLINE uae_u8 *get_real_address (uaecptr addr)
{
return get_mem_bank(addr).xlateaddr(addr);
return memory_get_real_address(addr);
}
STATIC_INLINE int valid_address (uaecptr addr, uae_u32 size)
{
return get_mem_bank(addr).check(addr, size);
return memory_valid_address(addr, size);
}
STATIC_INLINE void put_quad_host(void *addr, uae_u64 v)
{
do_put_mem_long((uae_u32*)addr, v >> 32);
do_put_mem_long(((uae_u32*)addr) + 1, (uae_u32)v);
}
STATIC_INLINE void put_long_host(void *addr, uae_u32 v)
{
do_put_mem_long((uae_u32*)addr, v);
@ -631,24 +826,38 @@ extern void REGPARAM3 chipmem_lput (uaecptr, uae_u32) REGPARAM;
extern void REGPARAM3 chipmem_wput (uaecptr, uae_u32) REGPARAM;
extern void REGPARAM3 chipmem_bput (uaecptr, uae_u32) REGPARAM;
extern uae_u32 REGPARAM3 chipmem_agnus_wget (uaecptr) REGPARAM;
extern void REGPARAM3 chipmem_agnus_wput (uaecptr, uae_u32) REGPARAM;
extern uae_u32 chipmem_full_mask;
extern addrbank dummy_bank;
STATIC_INLINE uae_u32 chipmem_lget_indirect(uae_u32 PT) {
return do_get_mem_long((uae_u32 *)&chipmem_bank.baseaddr[PT & chipmem_bank.mask]);
}
STATIC_INLINE uae_u32 chipmem_wget_indirect (uae_u32 PT) {
return do_get_mem_word((uae_u16 *)&chipmem_bank.baseaddr[PT & chipmem_full_mask]);
}
/* 68020+ Chip RAM DMA contention emulation */
extern void REGPARAM3 chipmem_bput_c2 (uaecptr, uae_u32) REGPARAM;
#define chipmem_wput_indirect chipmem_agnus_wput
extern uae_u32 (REGPARAM3 *chipmem_lget_indirect)(uaecptr) REGPARAM;
extern uae_u32 (REGPARAM3 *chipmem_wget_indirect)(uaecptr) REGPARAM;
extern uae_u32 (REGPARAM3 *chipmem_bget_indirect)(uaecptr) REGPARAM;
extern void (REGPARAM3 *chipmem_lput_indirect)(uaecptr, uae_u32) REGPARAM;
extern void (REGPARAM3 *chipmem_wput_indirect)(uaecptr, uae_u32) REGPARAM;
extern void (REGPARAM3 *chipmem_bput_indirect)(uaecptr, uae_u32) REGPARAM;
extern int (REGPARAM3 *chipmem_check_indirect)(uaecptr, uae_u32) REGPARAM;
extern uae_u8 *(REGPARAM3 *chipmem_xlate_indirect)(uaecptr) REGPARAM;
extern bool mapped_malloc (addrbank*);
extern void mapped_free (addrbank*);
//STATIC_INLINE uae_u32 chipmem_lget_indirect(uae_u32 PT) {
// return do_get_mem_long((uae_u32*)&chipmem_bank.baseaddr[PT & chipmem_bank.mask]);
//}
//STATIC_INLINE uae_u32 chipmem_wget_indirect(uae_u32 PT) {
// return do_get_mem_word((uae_u16*)&chipmem_bank.baseaddr[PT & chipmem_full_mask]);
//}
//#define chipmem_wput_indirect chipmem_agnus_wput
extern bool mapped_malloc(addrbank*);
extern void mapped_free(addrbank*);
extern void a3000_fakekick(int);
extern uaecptr strcpyha_safe (uaecptr dst, const uae_char *src);
extern uae_char *strcpyah_safe (uae_char *dst, uaecptr src, int maxsize);
extern void memcpyha_safe (uaecptr dst, const uae_u8 *src, int size);
extern void memcpyha (uaecptr dst, const uae_u8 *src, int size);
extern void memcpyah_safe (uae_u8 *dst, uaecptr src, int size);

1
src/include/newcpu.h
View file

@ -342,6 +342,7 @@ extern void setdivsoverflowflags(uae_s32 dividend, uae_s16 divisor);
extern void setchkundefinedflags(uae_s32 src, uae_s32 dst, int size);
extern void setchk2undefinedflags(uae_u32 lower, uae_u32 upper, uae_u32 val, int size);
extern void protect_roms (bool);
extern bool is_hardreset(void);
extern void Exception_build_stack_frame_common(uae_u32 oldpc, uae_u32 currpc, int nr);
extern void Exception_build_stack_frame(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr, int format);
extern void Exception_build_68000_address_error_stack_frame(uae_u16 mode, uae_u16 opcode, uaecptr fault_addr, uaecptr pc);

1962
src/memory.cpp
View file

File diff suppressed because it is too large Load diff

5
src/newcpu.cpp
View file

@ -1950,6 +1950,11 @@ static int in_m68k_go = 0;
static bool cpu_hardreset;
bool is_hardreset(void)
{
return cpu_hardreset;
}
#ifdef USE_JIT_FPU
static uae_u8 fp_buffer[9 * 16];
#endif

57
src/osdep/amiberry_mem.cpp
View file

@ -471,7 +471,10 @@ bool mapped_malloc(addrbank* ab)
write_log(_T("mapped_malloc with memory bank '%s' already allocated!?\n"), ab->name);
}
ab->allocated_size = 0;
ab->baseaddr_direct_r = NULL;
ab->baseaddr_direct_w = NULL;
ab->flags &= ~ABFLAG_MAPPED;
if (ab->label && ab->label[0] == '*')
{
if (ab->start == 0 || ab->start == 0xffffffff)
@ -482,12 +485,15 @@ bool mapped_malloc(addrbank* ab)
}
struct uae_mman_data md = {0};
uaecptr start = ab->start;
if (uae_mman_info(ab, &md))
{
const auto start = md.start;
start = md.start;
ab->baseaddr = regs.natmem_offset + start;
}
ab->startmask = start;
ab->startaccessmask = start & ab->mask;
if (ab->baseaddr)
{
if (md.hasbarrier)
@ -502,7 +508,7 @@ bool mapped_malloc(addrbank* ab)
}
ab->flags |= ABFLAG_DIRECTMAP;
return (ab->baseaddr != nullptr);
return ab->baseaddr != nullptr;
}
void mapped_free(addrbank* ab)
@ -520,38 +526,36 @@ void mapped_free(addrbank* ab)
void protect_roms(bool protect)
{
/*
If this code is enabled, we can't switch back from JIT to nonJIT emulation...
if (protect) {
// protect only if JIT enabled, always allow unprotect
if (!currprefs.cachesize || currprefs.comptrustbyte || currprefs.comptrustword || currprefs.comptrustlong)
return;
}
if (protect) {
// protect only if JIT enabled, always allow unprotect
if (!currprefs.cachesize)
return;
}
// Protect all regions, which contains ROM
if (extendedkickmem_bank.baseaddr != NULL)
mprotect(extendedkickmem_bank.baseaddr, 0x80000, protect ? PROT_READ : PROT_READ | PROT_WRITE);
if (extendedkickmem2_bank.baseaddr != NULL)
mprotect(extendedkickmem2_bank.baseaddr, 0x80000, protect ? PROT_READ : PROT_READ | PROT_WRITE);
if (kickmem_bank.baseaddr != NULL)
mprotect(kickmem_bank.baseaddr, 0x80000, protect ? PROT_READ : PROT_READ | PROT_WRITE);
//if (rtarea_bank.baseaddr != NULL)
// mprotect(rtarea_bank.baseaddr, RTAREA_SIZE, protect ? PROT_READ : PROT_READ | PROT_WRITE);
//if (filesysory != NULL)
// mprotect(filesysory, 0x10000, protect ? PROT_READ : PROT_READ | PROT_WRITE);
// Protect all regions, which contains ROM
if(extendedkickmem_bank.baseaddr != NULL)
mprotect(extendedkickmem_bank.baseaddr, 0x80000, protect ? PROT_READ : PROT_READ | PROT_WRITE);
if(extendedkickmem2_bank.baseaddr != NULL)
mprotect(extendedkickmem2_bank.baseaddr, 0x80000, protect ? PROT_READ : PROT_READ | PROT_WRITE);
if(kickmem_bank.baseaddr != NULL)
mprotect(kickmem_bank.baseaddr, 0x80000, protect ? PROT_READ : PROT_READ | PROT_WRITE);
if(rtarea != NULL)
mprotect(rtarea, RTAREA_SIZE, protect ? PROT_READ : PROT_READ | PROT_WRITE);
if(filesysory != NULL)
mprotect(filesysory, 0x10000, protect ? PROT_READ : PROT_READ | PROT_WRITE);
*/
}
static int doinit_shm(void)
{
changed_prefs.z3autoconfig_start = currprefs.z3autoconfig_start = 0;
expansion_scan_autoconfig(&currprefs, true);
return 1;
}
static uae_u32 oz3fastmem_size[MAX_RAM_BOARDS];
static uae_u32 ofastmem_size[MAX_RAM_BOARDS];
static uae_u32 oz3chipmem_size;
static uae_u32 ortgmem_size[MAX_RTG_BOARDS];
static int ortgmem_type[MAX_RTG_BOARDS];
@ -573,7 +577,7 @@ bool init_shm(void)
if (ortgmem_type[i] != changed_prefs.rtgboards[i].rtgmem_type)
changed = true;
}
if (!changed)
if (!changed && oz3chipmem_size == changed_prefs.z3chipmem_size)
return true;
for (auto i = 0; i < MAX_RAM_BOARDS; i++)
@ -586,7 +590,8 @@ bool init_shm(void)
ortgmem_size[i] = changed_prefs.rtgboards[i].rtgmem_size;
ortgmem_type[i] = changed_prefs.rtgboards[i].rtgmem_type;
}
oz3chipmem_size = changed_prefs.z3chipmem_size;
if (doinit_shm() < 0)
return false;

6
src/osdep/picasso96.cpp
View file

@ -3964,9 +3964,9 @@ MEMORY_FUNCTIONS(gfxmem);
addrbank gfxmem_bank = {
gfxmem_lget, gfxmem_wget, gfxmem_bget,
gfxmem_lput, gfxmem_wput, gfxmem_bput,
gfxmem_xlate, gfxmem_check, nullptr, nullptr, _T("RTG RAM"),
dummy_wgeti,
ABFLAG_RAM | ABFLAG_RTG, 0, 0
gfxmem_xlate, gfxmem_check, NULL, NULL, _T("RTG RAM"),
dummy_lgeti, dummy_wgeti,
ABFLAG_RAM | ABFLAG_RTG | ABFLAG_DIRECTACCESS, 0, 0
};
addrbank* gfxmem_banks[MAX_RTG_BOARDS];