pandory500/redquark-amiberry-rb
2
0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

JIT bugfixes - merged from TomB

Browse source
This commit is contained in:
Dimitris Panokostas 2018-03-11 10:56:43 +01:00
parent a9e8b14ea0
commit 86686ca7fd
12 changed files with 21816 additions and 29457 deletions
Download patch file Download diff file Expand all files Collapse all files

349
src/jit/codegen_arm.cpp
View file

@ -158,238 +158,6 @@ STATIC_INLINE void SIGNED16_REG_2_REG(W4 d, RR4 s) {
#define SIGN_EXTEND_16_REG_2_REG(d,s) SIGNED16_REG_2_REG(d,s)
LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, RR4 s))
{
ADD_rrr(d, d, s);
}
LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, RR4 s))
LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
{
if(CHECK32(i)) {
ADD_rri(d, d, i);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, i);
if(i >> 16)
MOVT_ri16(REG_WORK1, i >> 16);
#else
uae_s32 offs = data_long_offs(i);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
ADD_rrr(d, d, REG_WORK1);
}
}
LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, RR4 s, IMM offset))
{
if(CHECK32(offset)) {
ADD_rri(d, s, offset);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, offset);
if(offset >> 16)
MOVT_ri16(REG_WORK1, offset >> 16);
#else
uae_s32 offs = data_long_offs(offset);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
ADD_rrr(d, s, REG_WORK1);
}
}
LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, RR4 s, IMM offset))
LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
{
int shft;
switch(factor) {
case 1: shft=0; break;
case 2: shft=1; break;
case 4: shft=2; break;
case 8: shft=3; break;
default: abort();
}
SIGNED8_IMM_2_REG(REG_WORK1, offset);
ADD_rrr(REG_WORK1, s, REG_WORK1);
ADD_rrrLSLi(d, REG_WORK1, index, shft);
}
LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
{
int shft;
switch(factor) {
case 1: shft=0; break;
case 2: shft=1; break;
case 4: shft=2; break;
case 8: shft=3; break;
default: abort();
}
ADD_rrrLSLi(d, s, index, shft);
}
LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
{
BIC_rri(d, d, 0xff);
ORR_rri(d, d, (s & 0xff));
}
LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, RR1 s))
{
#ifdef ARMV6T2
BFI_rrii(d, s, 0, 7);
#else
AND_rri(REG_WORK1, s, 0xff);
BIC_rri(d, d, 0xff);
ORR_rrr(d, d, REG_WORK1);
#endif
}
LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, RR1 s))
LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
{
#ifdef ARMV6T2
if(d >= (uae_u32) &regs && d < ((uae_u32) &regs) + sizeof(struct regstruct)) {
MOVW_ri16(REG_WORK2, s);
if(s >> 16)
MOVT_ri16(REG_WORK2, s >> 16);
uae_s32 idx = d - (uae_u32) &regs;
STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
} else {
MOVW_ri16(REG_WORK1, d);
MOVT_ri16(REG_WORK1, d >> 16);
MOVW_ri16(REG_WORK2, s);
if(s >> 16)
MOVT_ri16(REG_WORK2, s >> 16);
STR_rR(REG_WORK2, REG_WORK1);
}
#else
if(d >= (uae_u32) &regs && d < ((uae_u32) &regs) + sizeof(struct regstruct)) {
uae_s32 offs = data_long_offs(s);
LDR_rRI(REG_WORK2, RPC_INDEX, offs);
uae_s32 idx = d - (uae_u32) & regs;
STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
} else {
data_check_end(8, 12);
uae_s32 offs = data_long_offs(d);
LDR_rRI(REG_WORK1, RPC_INDEX, offs); // ldr r2, [pc, #offs] ; d
offs = data_long_offs(s);
LDR_rRI(REG_WORK2, RPC_INDEX, offs); // ldr r3, [pc, #offs] ; s
STR_rR(REG_WORK2, REG_WORK1); // str r3, [r2]
}
#endif
}
LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
{
if(CHECK32(s)) {
MOV_ri(REG_WORK2, s);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK2, s);
#else
uae_s32 offs = data_word_offs(s);
LDR_rRI(REG_WORK2, RPC_INDEX, offs);
#endif
}
PKHBT_rrr(d, REG_WORK2, d);
}
LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, RR4 s))
{
if(d >= (uae_u32) &regs && d < ((uae_u32) &regs) + sizeof(struct regstruct)) {
uae_s32 idx = d - (uae_u32) &regs;
STR_rRI(s, R_REGSTRUCT, idx);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, d);
MOVT_ri16(REG_WORK1, d >> 16);
#else
uae_s32 offs = data_long_offs(d);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
STR_rR(s, REG_WORK1);
}
}
LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, RR4 s))
LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
{
if(s >= (uae_u32) &regs && s < ((uae_u32) &regs) + sizeof(struct regstruct)) {
uae_s32 idx = s - (uae_u32) & regs;
LDR_rRI(d, R_REGSTRUCT, idx);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, s);
MOVT_ri16(REG_WORK1, s >> 16);
#else
uae_s32 offs = data_long_offs(s);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
LDR_rR(d, REG_WORK1);
}
}
LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, RR2 s))
{
PKHBT_rrr(d, s, d);
}
LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, RR2 s))
LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
{
LSL_rri(r,r, i & 0x1f);
}
LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
{
if(CHECK32(i)) {
SUB_rri(d, d, i);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, i);
if(i >> 16)
MOVT_ri16(REG_WORK1, i >> 16);
#else
uae_s32 offs = data_long_offs(i);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
SUB_rrr(d, d, REG_WORK1);
}
}
LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
{
// This function is only called with i = 1
// Caller needs flags...
LSL_rri(REG_WORK2, d, 16);
SUBS_rri(REG_WORK2, REG_WORK2, (i & 0xff) << 16);
PKHTB_rrrASRi(d, d, REG_WORK2, 16);
MRS_CPSR(REG_WORK1);
EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
MSR_CPSRf_r(REG_WORK1);
}
LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
STATIC_INLINE void raw_push_regs_to_preserve(void) {
PUSH_REGS(PRESERVE_MASK);
}
@ -422,62 +190,9 @@ STATIC_INLINE void raw_reg_to_flags(int r)
MSR_CPSRf_r(r);
}
//
// Arm instructions
//
LOWFUNC(WRITE,NONE,2,raw_ADD_l_rr,(RW4 d, RR4 s))
{
ADD_rrr(d, d, s);
}
LENDFUNC(WRITE,NONE,2,raw_ADD_l_rr,(RW4 d, RR4 s))
LOWFUNC(WRITE,NONE,2,raw_ADD_l_rri,(RW4 d, RR4 s, IMM i))
{
ADD_rri(d, s, i);
}
LENDFUNC(WRITE,NONE,2,raw_ADD_l_rri,(RW4 d, RR4 s, IMM i))
LOWFUNC(WRITE,NONE,2,raw_SUB_l_rri,(RW4 d, RR4 s, IMM i))
{
SUB_rri(d, s, i);
}
LENDFUNC(WRITE,NONE,2,raw_SUB_l_rri,(RW4 d, RR4 s, IMM i))
LOWFUNC(WRITE,NONE,2,raw_LDR_l_ri,(RW4 d, IMM i))
{
#ifdef ARMV6T2
MOVW_ri16(d, i);
if(i >> 16)
MOVT_ri16(d, i >> 16);
#else
uae_s32 offs = data_long_offs(i);
LDR_rRI(d, RPC_INDEX, offs);
#endif
}
LENDFUNC(WRITE,NONE,2,raw_LDR_l_ri,(RW4 d, IMM i))
//
// compuemu_support used raw calls
//
LOWFUNC(WRITE,NONE,2,compemu_raw_MERGE_rr,(RW4 d, RR4 s))
{
PKHBT_rrr(d, d, s);
}
LENDFUNC(WRITE,NONE,2,compemu_raw_MERGE_rr,(RW4 d, RR4 s))
LOWFUNC(WRITE,NONE,2,compemu_raw_MERGE8_rr,(RW4 d, RR4 s))
{
#ifdef ARMV6T2
UBFX_rrii(REG_WORK1, s, 8, 24);
BFI_rrii(d, REG_WORK1, 8, 31);
#else
BIC_rri(REG_WORK1, s, 0xff);
AND_rri(d, d, 0xff);
ORR_rrr(d, d, REG_WORK1);
#endif
}
LENDFUNC(WRITE,NONE,2,compemu_raw_MERGE8_rr,(RW4 d, RR4 s))
LOWFUNC(WRITE,RMW,2,compemu_raw_add_l_mi,(IMM d, IMM s))
{
#ifdef ARMV6T2
@ -578,24 +293,6 @@ LOWFUNC(NONE,NONE,3,compemu_raw_lea_l_brr,(W4 d, RR4 s, IMM offset))
}
LENDFUNC(NONE,NONE,3,compemu_raw_lea_l_brr,(W4 d, RR4 s, IMM offset))
LOWFUNC(NONE,WRITE,2,compemu_raw_mov_b_mr,(MEMW d, RR1 s))
{
if(d >= (uae_u32) &regs && d < ((uae_u32) &regs) + sizeof(struct regstruct)) {
uae_s32 idx = d - (uae_u32) & regs;
STRB_rRI(s, R_REGSTRUCT, idx);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, d);
MOVT_ri16(REG_WORK1, d >> 16);
#else
uae_s32 offs = data_long_offs(d);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
STRB_rR(s, REG_WORK1);
}
}
LENDFUNC(NONE,WRITE,2,compemu_raw_mov_b_mr,(MEMW d, RR1 s))
LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mi,(MEMW d, IMM s))
{
#ifdef ARMV6T2
@ -686,24 +383,6 @@ LOWFUNC(NONE,NONE,2,compemu_raw_mov_l_rr,(W4 d, RR4 s))
}
LENDFUNC(NONE,NONE,2,compemu_raw_mov_l_rr,(W4 d, RR4 s))
LOWFUNC(NONE,WRITE,2,compemu_raw_mov_w_mr,(IMM d, RR2 s))
{
if(d >= (uae_u32) &regs && d < ((uae_u32) &regs) + sizeof(struct regstruct)) {
uae_s32 idx = d - (uae_u32) & regs;
STRH_rRI(s, R_REGSTRUCT, idx);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, d);
MOVT_ri16(REG_WORK1, d >> 16);
#else
uae_s32 offs = data_long_offs(d);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
STRH_rR(s, REG_WORK1);
}
}
LENDFUNC(NONE,WRITE,2,compemu_raw_mov_w_mr,(IMM d, RR2 s))
LOWFUNC(WRITE,RMW,2,compemu_raw_sub_l_mi,(MEMRW d, IMM s))
{
clobber_flags();
@ -1180,21 +859,37 @@ LOWFUNC(NONE,NONE,2,raw_fmov_to_s_rr,(W4 d, FR s))
}
LENDFUNC(NONE,NONE,2,raw_fmov_to_s_rr,(W4 d, FR s))
LOWFUNC(NONE,NONE,2,raw_fmov_to_w_rr,(W4 d, FR s))
LOWFUNC(NONE,NONE,2,raw_fmov_to_w_rr,(W4 d, FR s, int targetIsReg))
{
VCVTR64toI_sd(SCRATCH_F32_1, s);
VMOV32_rs(REG_WORK1, SCRATCH_F32_1);
SSAT_rir(d, 15, REG_WORK1);
if(targetIsReg) {
SSAT_rir(REG_WORK1, 15, REG_WORK1);
PKHTB_rrr(d, d, REG_WORK1);
} else {
SSAT_rir(d, 15, REG_WORK1);
}
}
LENDFUNC(NONE,NONE,2,raw_fmov_to_w_rr,(W4 d, FR s))
LENDFUNC(NONE,NONE,2,raw_fmov_to_w_rr,(W4 d, FR s, int targetIsReg))
LOWFUNC(NONE,NONE,2,raw_fmov_to_b_rr,(W4 d, FR s))
LOWFUNC(NONE,NONE,3,raw_fmov_to_b_rr,(W4 d, FR s, int targetIsReg))
{
VCVTR64toI_sd(SCRATCH_F32_1, s);
VMOV32_rs(REG_WORK1, SCRATCH_F32_1);
SSAT_rir(d, 7, REG_WORK1);
if(targetIsReg) {
SSAT_rir(REG_WORK1, 7, REG_WORK1);
#ifdef ARMV6T2
BFI_rrii(d, REG_WORK1, 0, 7);
#else
AND_rri(REG_WORK1, REG_WORK1, 0xff);
BIC_rri(d, d, 0xff);
ORR_rrr(d, d, REG_WORK1);
#endif
} else {
SSAT_rir(d, 7, REG_WORK1);
}
}
LENDFUNC(NONE,NONE,2,raw_fmov_to_b_rr,(W4 d, FR s))
LENDFUNC(NONE,NONE,3,raw_fmov_to_b_rr,(W4 d, FR s, int targetIsReg))
LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_0,(FW r))
{

200
src/jit/codegen_arm.h
View file

@ -66,46 +66,46 @@
/* --- ENCODINGS ----------------------------------------------------------- */
/* ========================================================================= */
#define IMM32(c) ((c & 0xffffff00) == 0 ? c : \
(c & 0x3fffffc0) == 0 ? (0x100 | ((c >> 30) & 0x3) | ((c << 2) & 0xfc)) : \
(c & 0x0ffffff0) == 0 ? (0x200 | ((c >> 28) & 0xf) | ((c << 4) & 0xf0)) : \
(c & 0x03fffffc) == 0 ? (0x300 | ((c >> 26) & 0x3f) | ((c << 6) & 0xc0) ) : \
(c & 0x00ffffff) == 0 ? (0x400 | ((c >> 24) & 0xff)) : \
(c & 0xc03fffff) == 0 ? (0x500 | (c >> 22)) : \
(c & 0xf00fffff) == 0 ? (0x600 | (c >> 20)) : \
(c & 0xfc03ffff) == 0 ? (0x700 | (c >> 18)) : \
(c & 0xff00ffff) == 0 ? (0x800 | (c >> 16)) : \
(c & 0xffc03fff) == 0 ? (0x900 | (c >> 14)) : \
(c & 0xfff00fff) == 0 ? (0xa00 | (c >> 12)) : \
(c & 0xfffc03ff) == 0 ? (0xb00 | (c >> 10)) : \
(c & 0xffff00ff) == 0 ? (0xc00 | (c >> 8)) : \
(c & 0xffffc03f) == 0 ? (0xd00 | (c >> 6)) : \
(c & 0xfffff00f) == 0 ? (0xe00 | (c >> 4)) : \
(c & 0xfffffc03) == 0 ? (0xf00 | (c >> 2)) : \
#define IMM32(c) (((c) & 0xffffff00) == 0 ? c : \
((c) & 0x3fffffc0) == 0 ? (0x100 | (((c) >> 30) & 0x3) | (((c) << 2) & 0xfc)) : \
((c) & 0x0ffffff0) == 0 ? (0x200 | (((c) >> 28) & 0xf) | (((c) << 4) & 0xf0)) : \
((c) & 0x03fffffc) == 0 ? (0x300 | (((c) >> 26) & 0x3f) | (((c) << 6) & 0xc0) ) : \
((c) & 0x00ffffff) == 0 ? (0x400 | (((c) >> 24) & 0xff)) : \
((c) & 0xc03fffff) == 0 ? (0x500 | ((c) >> 22)) : \
((c) & 0xf00fffff) == 0 ? (0x600 | ((c) >> 20)) : \
((c) & 0xfc03ffff) == 0 ? (0x700 | ((c) >> 18)) : \
((c) & 0xff00ffff) == 0 ? (0x800 | ((c) >> 16)) : \
((c) & 0xffc03fff) == 0 ? (0x900 | ((c) >> 14)) : \
((c) & 0xfff00fff) == 0 ? (0xa00 | ((c) >> 12)) : \
((c) & 0xfffc03ff) == 0 ? (0xb00 | ((c) >> 10)) : \
((c) & 0xffff00ff) == 0 ? (0xc00 | ((c) >> 8)) : \
((c) & 0xffffc03f) == 0 ? (0xd00 | ((c) >> 6)) : \
((c) & 0xfffff00f) == 0 ? (0xe00 | ((c) >> 4)) : \
((c) & 0xfffffc03) == 0 ? (0xf00 | ((c) >> 2)) : \
0\
)
#define CHECK32(c) ((c & 0xffffff00) == 0 || \
(c & 0x3fffffc0) == 0 || \
(c & 0x0ffffff0) == 0 || \
(c & 0x03fffffc) == 0 || \
(c & 0x00ffffff) == 0 || \
(c & 0xc03fffff) == 0 || \
(c & 0xf00fffff) == 0 || \
(c & 0xfc03ffff) == 0 || \
(c & 0xff00ffff) == 0 || \
(c & 0xffc03fff) == 0 || \
(c & 0xfff00fff) == 0 || \
(c & 0xfffc03ff) == 0 || \
(c & 0xffff00ff) == 0 || \
(c & 0xffffc03f) == 0 || \
(c & 0xfffff00f) == 0 || \
(c & 0xfffffc03) == 0)
#define CHECK32(c) (((c) & 0xffffff00) == 0 || \
((c) & 0x3fffffc0) == 0 || \
((c) & 0x0ffffff0) == 0 || \
((c) & 0x03fffffc) == 0 || \
((c) & 0x00ffffff) == 0 || \
((c) & 0xc03fffff) == 0 || \
((c) & 0xf00fffff) == 0 || \
((c) & 0xfc03ffff) == 0 || \
((c) & 0xff00ffff) == 0 || \
((c) & 0xffc03fff) == 0 || \
((c) & 0xfff00fff) == 0 || \
((c) & 0xfffc03ff) == 0 || \
((c) & 0xffff00ff) == 0 || \
((c) & 0xffffc03f) == 0 || \
((c) & 0xfffff00f) == 0 || \
((c) & 0xfffffc03) == 0)
#define SHIFT_IMM(c) (0x02000000 | (IMM32((c))))
#define UNSHIFTED_IMM8(c) (0x02000000 | (c))
#define SHIFT_IMM8_ROR(c,r) (0x02000000 | (c) | ((r >> 1) << 8))
#define SHIFT_IMM8_ROR(c,r) (0x02000000 | (c) | (((r) >> 1) << 8))
#define SHIFT_REG(Rm) (Rm)
#define SHIFT_LSL_i(Rm,s) ((Rm) | ((s) << 7))
@ -149,8 +149,8 @@
#define ADD_RRX(Rm) ADR_ADD(ADR_REG(Rm) | (3 << 5))
#define SUB_RRX(Rm) ADR_SUB(ADR_REG(Rm) | (3 << 5))
#define ADD2_IMM(i) ADR_ADD(i | (1 << 22))
#define SUB2_IMM(i) ADR_SUB(i | (1 << 22))
#define ADD2_IMM(i) ADR_ADD((i) | (1 << 22))
#define SUB2_IMM(i) ADR_SUB((i) | (1 << 22))
#define ADD2_REG(Rm) ADR_ADD(Rm)
#define SUB2_REG(Rm) ADR_SUB(Rm)
@ -935,8 +935,8 @@ enum {
#define BICS_rrrRRX(Rd,Rn,Rm) CC_BICS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
/* Branch instructions */
#define CC_B_i(cc,i) _W(((cc) << 28) | (10 << 24) | (i & 0x00ffffff))
#define CC_BL_i(cc,i) _W(((cc) << 28) | (11 << 24) | (i & 0x00ffffff))
#define CC_B_i(cc,i) _W(((cc) << 28) | (10 << 24) | ((i) & 0x00ffffff))
#define CC_BL_i(cc,i) _W(((cc) << 28) | (11 << 24) | ((i) & 0x00ffffff))
#define CC_BLX_r(cc,r) _W(((cc) << 28) | (0x12 << 20) | (3 << 4) | (0xfff << 8) | (r))
#define CC_BX_r(cc,r) _W(((cc) << 28) | (0x12 << 20) | (1 << 4) | (0xfff << 8) | (r))
#define CC_BXJ_r(cc,r) _W(((cc) << 28) | (0x12 << 20) | (2 << 4) | (0xfff << 8) | (r))
@ -1266,91 +1266,91 @@ enum {
#define SXTH_rr_ROR24(Rd,Rm) CC_SXTH_rr_ROR24(NATIVE_CC_AL,Rd,Rm)
#define CC_UXTB_rr(cc,Rd,Rm) _W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define UXTB_rr(Rd,Rm) CC_UXTB_rr(NATIVE_CC_AL,Rd,Rm)
#define UXTB_rr(Rd,Rm) CC_UXTB_rr(NATIVE_CC_AL,Rd,Rm)
#define CC_UXTB_rr_ROR8(cc,Rd,Rm) _W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (1 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define CC_UXTB_rr_ROR8(cc,Rd,Rm) _W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (1 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define UXTB_rr_ROR8(Rd,Rm) CC_UXTB_rr_ROR8(NATIVE_CC_AL,Rd,Rm)
#define CC_UXTB_rr_ROR16(cc,Rd,Rm) _W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (2 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define CC_UXTB_rr_ROR16(cc,Rd,Rm) _W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (2 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define UXTB_rr_ROR16(Rd,Rm) CC_UXTB_rr_ROR16(NATIVE_CC_AL,Rd,Rm)
#define CC_UXTB_rr_ROR24(cc,Rd,Rm) _W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (3 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define CC_UXTB_rr_ROR24(cc,Rd,Rm) _W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (3 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define UXTB_rr_ROR24(Rd,Rm) CC_UXTB_rr_ROR24(NATIVE_CC_AL,Rd,Rm)
#define CC_UXTH_rr(cc,Rd,Rm) _W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define UXTH_rr(Rd,Rm) CC_UXTH_rr(NATIVE_CC_AL,Rd,Rm)
#define UXTH_rr(Rd,Rm) CC_UXTH_rr(NATIVE_CC_AL,Rd,Rm)
#define CC_UXTH_rr_ROR8(cc,Rd,Rm) _W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (1 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define CC_UXTH_rr_ROR8(cc,Rd,Rm) _W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (1 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define UXTH_rr_ROR8(Rd,Rm) CC_UXTH_rr_ROR8(NATIVE_CC_AL,Rd,Rm)
#define CC_UXTH_rr_ROR16(cc,Rd,Rm) _W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (2 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define CC_UXTH_rr_ROR16(cc,Rd,Rm) _W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (2 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define UXTH_rr_ROR16(Rd,Rm) CC_UXTH_rr_ROR16(NATIVE_CC_AL,Rd,Rm)
#define CC_UXTH_rr_ROR24(cc,Rd,Rm) _W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (3 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define CC_UXTH_rr_ROR24(cc,Rd,Rm) _W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (3 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
#define UXTH_rr_ROR24(Rd,Rm) CC_UXTH_rr_ROR24(NATIVE_CC_AL,Rd,Rm)
#define CC_REV_rr(cc,Rd,Rm) _W(((cc) << 28) | (0x6b << 20) | (0xf << 16) | (0xf << 8) | ((Rd) << 12) | (0x3 << 4) | SHIFT_REG(Rm))
#define REV_rr(Rd,Rm) CC_REV_rr(NATIVE_CC_AL,Rd,Rm)
#define REV_rr(Rd,Rm) CC_REV_rr(NATIVE_CC_AL,Rd,Rm)
#define CC_REV16_rr(cc,Rd,Rm) _W(((cc) << 28) | (0x6b << 20) | (0xf << 16) | (0xf << 8) | ((Rd) << 12) | (0xB << 4) | SHIFT_REG(Rm))
#define REV16_rr(Rd,Rm) CC_REV16_rr(NATIVE_CC_AL,Rd,Rm)
#define REV16_rr(Rd,Rm) CC_REV16_rr(NATIVE_CC_AL,Rd,Rm)
#define CC_REVSH_rr(cc,Rd,Rm) _W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | (0xf << 8) | ((Rd) << 12) | (0xB << 4) | SHIFT_REG(Rm))
#define REVSH_rr(Rd,Rm) CC_REVSH_rr(NATIVE_CC_AL,Rd,Rm)
#define REVSH_rr(Rd,Rm) CC_REVSH_rr(NATIVE_CC_AL,Rd,Rm)
#define CC_PKHBT_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x68 << 20) | (Rn << 16) | (Rd << 12) | (0x1 << 4) | (Rm))
#define CC_PKHBT_rrrLSLi(cc,Rd,Rn,Rm,s) _W(((cc) << 28) | (0x68 << 20) | (Rn << 16) | (Rd << 12) | (0x1 << 4) | SHIFT_PK(Rm, s))
#define CC_PKHBT_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x68 << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x1 << 4) | (Rm))
#define CC_PKHBT_rrrLSLi(cc,Rd,Rn,Rm,s) _W(((cc) << 28) | (0x68 << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x1 << 4) | SHIFT_PK(Rm, s))
#define PKHBT_rrr(Rd,Rn,Rm) CC_PKHBT_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define PKHBT_rrrLSLi(Rd,Rn,Rm,s) CC_PKHBT_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,s)
#define PKHBT_rrrLSLi(Rd,Rn,Rm,s) CC_PKHBT_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,s)
#define CC_PKHTB_rrrASRi(cc,Rd,Rn,Rm,s) _W(((cc) << 28) | (0x68 << 20) | (Rn << 16) | (Rd << 12) | (0x5 << 4) | SHIFT_PK(Rm, s))
#define PKHTB_rrrASRi(Rd,Rn,Rm,s) CC_PKHTB_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,s)
#define CC_PKHTB_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x68 << 20) | (Rn << 16) | (Rd << 12) | (0x5 << 4) | (Rm))
#define PKHTB_rrr(Rd,Rn,Rm) CC_PKHTB_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_PKHTB_rrrASRi(cc,Rd,Rn,Rm,s) _W(((cc) << 28) | (0x68 << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x5 << 4) | SHIFT_PK(Rm, s))
#define PKHTB_rrrASRi(Rd,Rn,Rm,s) CC_PKHTB_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,s)
#define CC_PKHTB_rrr(cc,Rd,Rn,Rm) CC_PKHBT_rrr(cc,Rd,Rm,Rn)
#define PKHTB_rrr(Rd,Rn,Rm) PKHBT_rrr(Rd,Rm,Rn)
#define CC_SADD16_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x61 << 20) | (Rn << 16) | (Rd << 12) | (0xf1 << 4) | (Rm))
#define SADD16_rrr(Rd,Rn,Rm) CC_SADD16_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_SADD16_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x61 << 20) | ((Rn) << 16) | ((Rd) << 12) | (0xf1 << 4) | (Rm))
#define SADD16_rrr(Rd,Rn,Rm) CC_SADD16_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_SXTAB_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x6a << 20) | (Rn << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define SXTAB_rrr(Rd,Rn,Rm) CC_SXTAB_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_SXTAB_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x6a << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define SXTAB_rrr(Rd,Rn,Rm) CC_SXTAB_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_SXTAH_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x6b << 20) | (Rn << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define SXTAH_rrr(Rd,Rn,Rm) CC_SXTAH_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_SXTAH_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x6b << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
#define SXTAH_rrr(Rd,Rn,Rm) CC_SXTAH_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_STM_Ri(cc,Rn,i) _W(((cc) << 28) | (0x8 << 24) | (0x8 << 20) | ((Rn) << 16) | i)
#define CC_STM_Ri(cc,Rn,i) _W(((cc) << 28) | (0x8 << 24) | (0x8 << 20) | ((Rn) << 16) | (i))
#define STM_Ri(Rn,i) CC_STM_Ri(NATIVE_CC_AL,Rn,i)
#define CC_MLS_rrrr(cc,Rd,Rn,Rm,Ra) _W(((cc) << 28) | (0x0 << 24) | (0x6 << 20) | (Rd << 16) | (Ra << 12) | (Rm << 8) | (0x9 << 4) | Rn)
#define CC_MLS_rrrr(cc,Rd,Rn,Rm,Ra) _W(((cc) << 28) | (0x0 << 24) | (0x6 << 20) | ((Rd) << 16) | ((Ra) << 12) | ((Rm) << 8) | (0x9 << 4) | (Rn))
#define MLS_rrrr(Rd,Rn,Rm,Ra) CC_MLS_rrrr(NATIVE_CC_AL,Rd,Rn,Rm,Ra)
#define CC_SMULxy_rrr(cc,Rd,Rn,Rm,x,y) _W(((cc) << 28) | (0x1 << 24) | (0x6 << 20) | (Rd << 16) | (0x0 << 12) | (Rm << 8) | (0x8 << 4) | (Rn) | (x << 5) | (y << 6))
#define CC_SMULxy_rrr(cc,Rd,Rn,Rm,x,y) _W(((cc) << 28) | (0x1 << 24) | (0x6 << 20) | ((Rd) << 16) | (0x0 << 12) | ((Rm) << 8) | (0x8 << 4) | (Rn) | ((x) << 5) | ((y) << 6))
#define SMULxy_rrr(Rd,Rn,Rm,x,y) CC_SMULxy_rrr(NATIVE_CC_AL,Rd,Rn,Rm,x,y)
// ARMv6T2
#ifdef ARMV6T2
#define CC_BFI_rrii(cc,Rd,Rn,lsb,msb) _W(((cc) << 28) | (0x3e << 21) | ((msb) << 16) | (Rd << 12) | ((lsb) << 7) | (0x1 << 4) | (Rn))
#define CC_BFI_rrii(cc,Rd,Rn,lsb,msb) _W(((cc) << 28) | (0x3e << 21) | ((msb) << 16) | ((Rd) << 12) | ((lsb) << 7) | (0x1 << 4) | (Rn))
#define BFI_rrii(Rd,Rn,lsb,msb) CC_BFI_rrii(NATIVE_CC_AL,Rd,Rn,lsb,msb)
#define CC_BFC_rii(cc,Rd,lsb,msb) _W(((cc) << 28) | (0x3e << 21) | ((msb) << 16) | (Rd << 12) | ((lsb) << 7) | (0x1 << 4) | 15)
#define CC_BFC_rii(cc,Rd,lsb,msb) _W(((cc) << 28) | (0x3e << 21) | ((msb) << 16) | ((Rd) << 12) | ((lsb) << 7) | (0x1 << 4) | 15)
#define BFC_rii(Rd,lsb,msb) CC_BFC_rii(NATIVE_CC_AL,Rd,lsb,msb)
#define CC_UBFX_rrii(cc,Rd,Rn,lsb,width) _W(((cc) << 28) | (0x3f << 21) | ((width-1) << 16) | (Rd << 12) | ((lsb) << 7) | (0x5 << 4) | (Rn))
#define CC_UBFX_rrii(cc,Rd,Rn,lsb,width) _W(((cc) << 28) | (0x3f << 21) | ((width-1) << 16) | ((Rd) << 12) | ((lsb) << 7) | (0x5 << 4) | (Rn))
#define UBFX_rrii(Rd,Rn,lsb,width) CC_UBFX_rrii(NATIVE_CC_AL,Rd,Rn,lsb,width)
#define CC_MOVW_ri16(cc,Rd,i) _W(((cc) << 28) | (0x30 << 20) | (((i >> 12) & 0xf) << 16) | (Rd << 12) | (i & 0x0fff))
#define MOVW_ri16(Rd,i) CC_MOVW_ri16(NATIVE_CC_AL,Rd,i)
#define CC_MOVW_ri16(cc,Rd,i) _W(((cc) << 28) | (0x30 << 20) | ((((i) >> 12) & 0xf) << 16) | ((Rd) << 12) | ((i) & 0x0fff))
#define MOVW_ri16(Rd,i) CC_MOVW_ri16(NATIVE_CC_AL,Rd,i)
#define CC_MOVT_ri16(cc,Rd,i) _W(((cc) << 28) | (0x34 << 20) | (((i >> 12) & 0xf) << 16) | (Rd << 12) | (i & 0x0fff))
#define MOVT_ri16(Rd,i) CC_MOVT_ri16(NATIVE_CC_AL,Rd,i)
#define CC_MOVT_ri16(cc,Rd,i) _W(((cc) << 28) | (0x34 << 20) | ((((i) >> 12) & 0xf) << 16) | ((Rd) << 12) | ((i) & 0x0fff))
#define MOVT_ri16(Rd,i) CC_MOVT_ri16(NATIVE_CC_AL,Rd,i)
#define CC_SSAT_rir(cc,Rd,i,Rn) _W(((cc) << 28) | (0x6a << 20) | (i << 16) | (Rd << 12) | (0x1 << 4) | (Rn))
#define CC_SSAT_rir(cc,Rd,i,Rn) _W(((cc) << 28) | (0x6a << 20) | ((i) << 16) | ((Rd) << 12) | (0x1 << 4) | (Rn))
#define SSAT_rir(Rd,i,Rn) CC_SSAT_rir(NATIVE_CC_AL,Rd,i,Rn)
#define CC_SDIV_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x7 << 24) | (0x1 << 20) | (Rd << 16) | (0xf << 12) | (Rm << 8) | (0x1 << 4) | (Rn))
#define CC_SDIV_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x7 << 24) | (0x1 << 20) | ((Rd) << 16) | (0xf << 12) | ((Rm) << 8) | (0x1 << 4) | (Rn))
#define SDIV_rrr(Rd,Rn,Rm) CC_SDIV_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#define CC_UDIV_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x7 << 24) | (0x3 << 20) | (Rd << 16) | (0xf << 12) | (Rm << 8) | (0x1 << 4) | (Rn))
#define CC_UDIV_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x7 << 24) | (0x3 << 20) | ((Rd) << 16) | (0xf << 12) | ((Rm) << 8) | (0x1 << 4) | (Rn))
#define UDIV_rrr(Rd,Rn,Rm) CC_UDIV_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
#endif
@ -1358,24 +1358,24 @@ enum {
// Floatingpoint
#define FADR_ADD(offs) ((1 << 23) | (offs) >> 2)
#define FADR_SUB(offs) ((0 << 23) | (offs) >> 2)
#define FOFFSET8(offs) (offs >= 0 ? FADR_ADD(offs) : FADR_SUB(-offs))
#define FOFFSET8(offs) ((offs) >= 0 ? FADR_ADD(offs) : FADR_SUB(-offs))
#define MAKE_Dd(Dd) (((Dd & 0x10) << 18) | ((Dd & 0x0f) << 12))
#define MAKE_Dm(Dm) (((Dm & 0x10) << 1) | ((Dm & 0x0f) << 0))
#define MAKE_Dn(Dn) (((Dn & 0x10) << 3) | ((Dn & 0x0f) << 16))
#define MAKE_Sd(Sd) (((Sd & 0x01) << 22) | ((Sd & 0x1e) << 11))
#define MAKE_Sm(Sm) (((Sm & 0x01) << 5) | ((Sm & 0x1e) >> 1))
#define MAKE_Sn(Sn) (((Sn & 0x01) << 7) | ((Sn & 0x1e) << 15))
#define MAKE_Dd(Dd) ((((Dd) & 0x10) << 18) | (((Dd) & 0x0f) << 12))
#define MAKE_Dm(Dm) ((((Dm) & 0x10) << 1) | (((Dm) & 0x0f) << 0))
#define MAKE_Dn(Dn) ((((Dn) & 0x10) << 3) | (((Dn) & 0x0f) << 16))
#define MAKE_Sd(Sd) ((((Sd) & 0x01) << 22) | (((Sd) & 0x1e) << 11))
#define MAKE_Sm(Sm) ((((Sm) & 0x01) << 5) | (((Sm) & 0x1e) >> 1))
#define MAKE_Sn(Sn) ((((Sn) & 0x01) << 7) | (((Sn) & 0x1e) << 15))
#define CC_VLDR64_dRi(cc,Dd,Rn,offs) _W(((cc) << 28) | (0xd << 24) | (0x1 << 20) | (Rn << 16) | (0xb << 8) | FOFFSET8(offs) | MAKE_Dd(Dd))
#define CC_VLDR64_dRi(cc,Dd,Rn,offs) _W(((cc) << 28) | (0xd << 24) | (0x1 << 20) | ((Rn) << 16) | (0xb << 8) | FOFFSET8(offs) | MAKE_Dd(Dd))
#define VLDR64_dRi(Dd,Rn,offs) CC_VLDR64_dRi(NATIVE_CC_AL,Dd,Rn,offs)
#define CC_VLDR32_sRi(cc,Sd,Rn,offs) _W(((cc) << 28) | (0xd << 24) | (0x1 << 20) | (Rn << 16) | (0xa << 8) | FOFFSET8(offs) | MAKE_Sd(Sd))
#define CC_VLDR32_sRi(cc,Sd,Rn,offs) _W(((cc) << 28) | (0xd << 24) | (0x1 << 20) | ((Rn) << 16) | (0xa << 8) | FOFFSET8(offs) | MAKE_Sd(Sd))
#define VLDR32_sRi(Sd,Rn,offs) CC_VLDR32_sRi(NATIVE_CC_AL,Sd,Rn,offs)
#define CC_VSTR64_dRi(cc,Dd,Rn,offs) _W(((cc) << 28) | (0xd << 24) | (0x0 << 20) | (Rn << 16) | (0xb << 8) | FOFFSET8(offs) | MAKE_Dd(Dd))
#define CC_VSTR64_dRi(cc,Dd,Rn,offs) _W(((cc) << 28) | (0xd << 24) | (0x0 << 20) | ((Rn) << 16) | (0xb << 8) | FOFFSET8(offs) | MAKE_Dd(Dd))
#define VSTR64_dRi(Dd,Rn,offs) CC_VSTR64_dRi(NATIVE_CC_AL,Dd,Rn,offs)
#define CC_VSTR32_sRi(cc,Sd,Rn,offs) _W(((cc) << 28) | (0xd << 24) | (0x0 << 20) | (Rn << 16) | (0xa << 8) | FOFFSET8(offs) | MAKE_Sd(Sd))
#define CC_VSTR32_sRi(cc,Sd,Rn,offs) _W(((cc) << 28) | (0xd << 24) | (0x0 << 20) | ((Rn) << 16) | (0xa << 8) | FOFFSET8(offs) | MAKE_Sd(Sd))
#define VSTR32_sRi(Sd,Rn,offs) CC_VSTR32_sRi(NATIVE_CC_AL,Sd,Rn,offs)
#define CC_VMOV64_dd(cc,Dd,Dm) _W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xb << 8) | (0x4 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm))
@ -1383,19 +1383,19 @@ enum {
#define CC_VMOV32_ss(cc,Sd,Sm) _W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xa << 8) | (0x4 << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
#define VMOV32_ss(Sd,Sm) CC_VMOV32_ss(NATIVE_CC_AL,Sd,Sm)
#define CC_VMOV32_rs(cc,Rt,Sn) _W(((cc) << 28) | (0xe << 24) | (0x1 << 20) | (Rt << 12) | (0xa << 8) | (0x1 << 4) | MAKE_Sn(Sn))
#define CC_VMOV32_rs(cc,Rt,Sn) _W(((cc) << 28) | (0xe << 24) | (0x1 << 20) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4) | MAKE_Sn(Sn))
#define VMOV32_rs(Rt,Sn) CC_VMOV32_rs(NATIVE_CC_AL,Rt,Sn)
#define CC_VMOV32_sr(cc,Sn,Rt) _W(((cc) << 28) | (0xe << 24) | (0x0 << 20) | (Rt << 12) | (0xa << 8) | (0x1 << 4) | MAKE_Sn(Sn))
#define CC_VMOV32_sr(cc,Sn,Rt) _W(((cc) << 28) | (0xe << 24) | (0x0 << 20) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4) | MAKE_Sn(Sn))
#define VMOV32_sr(Sn,Rt) CC_VMOV32_sr(NATIVE_CC_AL,Sn,Rt)
#define CC_VMOVi_from_ARM_dr(cc,Dn,Rt,x) _W(((cc) << 28) | (0xe << 24) | (0x0 << 20) | (Rt << 12) | (0xb << 8) | (0x1 << 4) | ((x) << 21) | MAKE_Dn(Dn))
#define CC_VMOVi_from_ARM_dr(cc,Dn,Rt,x) _W(((cc) << 28) | (0xe << 24) | (0x0 << 20) | ((Rt) << 12) | (0xb << 8) | (0x1 << 4) | ((x) << 21) | MAKE_Dn(Dn))
#define VMOVi_from_ARM_dr(Dn,Rt,x) CC_VMOVi_from_ARM_dr(NATIVE_CC_AL,Dn,Rt,x)
#define CC_VMOVi_to_ARM_rd(cc,Rt,Dn,x) _W(((cc) << 28) | (0xe << 24) | (0x1 << 20) | (Rt << 12) | (0xb << 8) | (0x1 << 4) | ((x) << 21) | MAKE_Dn(Dn))
#define CC_VMOVi_to_ARM_rd(cc,Rt,Dn,x) _W(((cc) << 28) | (0xe << 24) | (0x1 << 20) | ((Rt) << 12) | (0xb << 8) | (0x1 << 4) | ((x) << 21) | MAKE_Dn(Dn))
#define VMOVi_to_ARM_rd(Rt,Dn,x) CC_VMOVi_to_ARM_rd(NATIVE_CC_AL,Rt,Dn,x)
#define CC_VMOV64_rrd(cc,Rt,Rt2,Dm) _W(((cc) << 28) | (0xc << 24) | (0x5 << 20) | (Rt2 << 16) | (Rt << 12) | (0xb << 8) | (0x1 << 4) | MAKE_Dm(Dm))
#define CC_VMOV64_rrd(cc,Rt,Rt2,Dm) _W(((cc) << 28) | (0xc << 24) | (0x5 << 20) | ((Rt2) << 16) | ((Rt) << 12) | (0xb << 8) | (0x1 << 4) | MAKE_Dm(Dm))
#define VMOV64_rrd(Rt,Rt2,Dm) CC_VMOV64_rrd(NATIVE_CC_AL,Rt,Rt2,Dm)
#define CC_VMOV64_drr(cc,Dm,Rt,Rt2) _W(((cc) << 28) | (0xc << 24) | (0x4 << 20) | (Rt2 << 16) | (Rt << 12) | (0xb << 8) | (0x1 << 4) | MAKE_Dm(Dm))
#define CC_VMOV64_drr(cc,Dm,Rt,Rt2) _W(((cc) << 28) | (0xc << 24) | (0x4 << 20) | ((Rt2) << 16) | ((Rt) << 12) | (0xb << 8) | (0x1 << 4) | MAKE_Dm(Dm))
#define VMOV64_drr(Dm,Rt,Rt2) CC_VMOV64_drr(NATIVE_CC_AL,Dm,Rt,Rt2)
#define CC_VCVT64to32_sd(cc,Sd,Dm) _W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x7 << 16) | (0xb << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Dm(Dm))
@ -1467,26 +1467,26 @@ enum {
#define CC_VCMP64_d0(cc,Dd) _W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x5 << 16) | (0xb << 8) | (0xc << 4) | MAKE_Dd(Dd))
#define VCMP64_d0(Dd) CC_VCMP64_d0(NATIVE_CC_AL,Dd)
#define CC_VMRS_r(cc,Rt) _W(((cc) << 28) | (0xe << 24) | (0xf << 20) | (0x1 << 16) | (Rt << 12) | (0xa << 8) | (0x1 << 4))
#define CC_VMRS_r(cc,Rt) _W(((cc) << 28) | (0xe << 24) | (0xf << 20) | (0x1 << 16) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4))
#define VMRS_r(Rt) CC_VMRS_r(NATIVE_CC_AL,Rt)
#define VMRS_CPSR() VMRS_r(15)
#define CC_VMSR_r(cc,Rt) _W(((cc) << 28) | (0xe << 24) | (0xe << 20) | (0x1 << 16) | (Rt << 12) | (0xa << 8) | (0x1 << 4))
#define CC_VMSR_r(cc,Rt) _W(((cc) << 28) | (0xe << 24) | (0xe << 20) | (0x1 << 16) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4))
#define VMSR_r(Rt) CC_VMSR_r(NATIVE_CC_AL,Rt)
// Immediate values for VBIC, VMOV (I32), VMVN (I32) and VORR
#define FIMMVAL(imm) (((imm & 0x80) << 17) | ((imm & 0x70) << 12) | ((imm & 0x0f) << 0))
#define FIMM32(imm) ((imm & 0xffffff00) == 0 ? (FIMMVAL(imm >> 0) | (0x0 << 8)) : \
(imm & 0xffff00ff) == 0 ? (FIMMVAL(imm >> 8) | (0x1 << 8)) : \
(imm & 0xff00ffff) == 0 ? (FIMMVAL(imm >> 16) | (0x2 << 8)) : \
(FIMMVAL(imm >> 24) | (0x3 << 8))
#define FIMMVAL(imm) ((((imm) & 0x80) << 17) | (((imm) & 0x70) << 12) | (((imm) & 0x0f) << 0))
#define FIMM32(imm) (((imm) & 0xffffff00) == 0 ? (FIMMVAL((imm) >> 0) | (0x0 << 8)) : \
((imm) & 0xffff00ff) == 0 ? (FIMMVAL((imm) >> 8) | (0x1 << 8)) : \
((imm) & 0xff00ffff) == 0 ? (FIMMVAL((imm) >> 16) | (0x2 << 8)) : \
(FIMMVAL((imm) >> 24) | (0x3 << 8))
// VMOV I64: each bit of imm defines the value for an entire byte
// imm <abcdefgh> -> aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
#define VMOV_I64_dimmI(Dd,imm) _W((0xf << 28) | (0x2 << 24) | (0x8 << 20) | (0x0 << 16) | (0xe << 8) | (0x3 << 4) | MAKE_Dd(Dd) | FIMMVAL(imm))
// VMOV F64: imm <abcdefgh> -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = not b)
#define FIMMF64(imm) (((imm & 0xf0) << 12) | ((imm & 0x0f) << 0))
#define FIMMF64(imm) ((((imm) & 0xf0) << 12) | (((imm) & 0x0f) << 0))
#define CC_VMOV_F64_dimmF(cc,Dd,imm) _W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xb << 8) | MAKE_Dd(Dd) | FIMMF64(imm))
#define VMOV_F64_dimmF(Dd,imm) CC_VMOV_F64_dimmF(NATIVE_CC_AL,Dd,imm)
@ -1497,7 +1497,7 @@ enum {
// Immediate value for shift
#define FIMM6(imm) ((imm) << 16)
#define VSHL64_ddi(Dd,Dm,imm) _W((0xf << 28) | (0x2 << 24) | (0x8 << 20) | (0x5 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(imm))
#define VSHR64_ddi(Dd,Dm,imm) _W((0xf << 28) | (0x3 << 24) | (0x8 << 20) | (0x0 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(64-imm))
#define VSHR64_ddi(Dd,Dm,imm) _W((0xf << 28) | (0x3 << 24) | (0x8 << 20) | (0x0 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(64-(imm)))
#define VSLI64_ddi(Dd,Dm,i) _W((0xf << 28) | (0x3 << 24) | (0x8 << 20) | (0x5 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(i))
#define VORR_ddd(Dd,Dn,Dm) _W((0xf << 28) | (0x2 << 24) | (0x2 << 20) | (0x1 << 8) | (0x1 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))

43186
src/jit/compemu.cpp
View file

File diff suppressed because it is too large Load diff

1
src/jit/compemu.h
View file

@ -178,7 +178,6 @@ typedef struct {
uae_s8 realreg; /* gb-- realreg can hold -1 */
uae_u8 realind; /* The index in the holds[] array */
uae_u8 validsize;
uae_u8 dirtysize;
} reg_status;
typedef struct {

12
src/jit/compemu_fpp.cpp
View file

@ -245,7 +245,7 @@ STATIC_INLINE int comp_fp_put (uae_u32 opcode, uae_u16 extra)
{
uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
mov_l_rr (S1, reg + 8);
add_l_ri (S1, off);
arm_ADD_l_ri (S1, off);
break;
}
case 6: /* (d8,An,Xn) or (bd,An,Xn) or ([bd,An,Xn],od) or ([bd,An],Xn,od) */
@ -318,7 +318,7 @@ STATIC_INLINE int comp_fp_adr (uae_u32 opcode)
case 5:
off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
mov_l_rr (S1, 8 + reg);
add_l_ri (S1, off);
arm_ADD_l_ri (S1, off);
return S1;
case 7:
switch (reg) {
@ -428,8 +428,8 @@ void comp_fbcc_opp (uae_u32 opcode)
mov_l_ri(PC_P, (uintptr) comp_pc_p);
/* Now they are both constant. Might as well fold in m68k_pc_offset */
add_l_ri (S1, m68k_pc_offset);
add_l_ri (PC_P, m68k_pc_offset);
arm_ADD_l_ri (S1, m68k_pc_offset);
arm_ADD_l_ri (PC_P, m68k_pc_offset);
m68k_pc_offset = 0;
v1 = get_const (PC_P);
@ -622,7 +622,7 @@ void comp_fpp_opp (uae_u32 opcode, uae_u16 extra)
for (reg = 0; reg <= 7; reg++) {
if (list & 0x80) {
fp_from_exten_mr (ad, reg);
add_l_ri (ad, 12);
arm_ADD_l_ri (ad, 12);
}
list <<= 1;
}
@ -678,7 +678,7 @@ void comp_fpp_opp (uae_u32 opcode, uae_u16 extra)
for (reg = 0; reg <= 7; reg++) {
if (list & 0x80) {
fp_to_exten_rm(reg, ad);
add_l_ri (ad, 12);
arm_ADD_l_ri (ad, 12);
}
list <<= 1;
}

487
src/jit/compemu_midfunc_arm.cpp
View file

@ -52,6 +52,96 @@
* - 5th unlock2 all registers that were locked
*/
#define INIT_REGS_b(d,s) \
int targetIsReg = (d < 16); \
int s_is_d = (s == d); \
if(!s_is_d) \
s = readreg(s); \
d = rmw(d); \
if(s_is_d) \
s = d;
#define INIT_RREGS_b(d,s) \
int targetIsReg = (d < 16); \
int s_is_d = (s == d); \
if(!s_is_d) \
s = readreg(s); \
d = readreg(d); \
if(s_is_d) \
s = d;
#define INIT_REG_b(d) \
int targetIsReg = (d < 16); \
d = rmw(d);
#define INIT_RREG_b(d) \
int targetIsReg = (d < 16); \
d = readreg(d);
#define INIT_WREG_b(d) \
int targetIsReg = (d < 16); \
if(targetIsReg) \
d = rmw(d); \
else \
d = writereg(d);
#define INIT_REGS_w(d,s) \
int targetIsReg = (d < 16); \
int s_is_d = (s == d); \
if(!s_is_d) \
s = readreg(s); \
d = rmw(d); \
if(s_is_d) \
s = d;
#define INIT_RREGS_w(d,s) \
int targetIsReg = (d < 16); \
int s_is_d = (s == d); \
if(!s_is_d) \
s = readreg(s); \
d = readreg(d); \
if(s_is_d) \
s = d;
#define INIT_REG_w(d) \
int targetIsReg = (d < 16); \
d = rmw(d);
#define INIT_RREG_w(d) \
int targetIsReg = (d < 16); \
d = readreg(d);
#define INIT_WREG_w(d) \
int targetIsReg = (d < 16); \
if(targetIsReg) \
d = rmw(d); \
else \
d = writereg(d);
#define INIT_REGS_l(d,s) \
int targetIsReg = (d < 16); \
int s_is_d = (s == d); \
if(!s_is_d) \
s = readreg(s); \
d = rmw(d); \
if(s_is_d) \
s = d;
#define INIT_RREGS_l(d,s) \
int targetIsReg = (d < 16); \
int s_is_d = (s == d); \
if(!s_is_d) \
s = readreg(s); \
d = readreg(d); \
if(s_is_d) \
s = d;
#define EXIT_REGS(d,s) \
unlock2(d); \
if(!s_is_d) \
unlock2(s);
MIDFUNC(0,live_flags,(void))
{
live.flags_on_stack = TRASH;
@ -74,7 +164,39 @@ MENDFUNC(0,make_flags_live,(void))
MIDFUNC(2,mov_l_mi,(IMM d, IMM s))
{
raw_mov_l_mi(d, s);
#ifdef ARMV6T2
if(d >= (uae_u32) &regs && d < ((uae_u32) &regs) + sizeof(struct regstruct)) {
MOVW_ri16(REG_WORK2, s);
if(s >> 16)
MOVT_ri16(REG_WORK2, s >> 16);
uae_s32 idx = d - (uae_u32) &regs;
STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
} else {
MOVW_ri16(REG_WORK1, d);
MOVT_ri16(REG_WORK1, d >> 16);
MOVW_ri16(REG_WORK2, s);
if(s >> 16)
MOVT_ri16(REG_WORK2, s >> 16);
STR_rR(REG_WORK2, REG_WORK1);
}
#else
if(d >= (uae_u32) &regs && d < ((uae_u32) &regs) + sizeof(struct regstruct)) {
uae_s32 offs = data_long_offs(s);
LDR_rRI(REG_WORK2, RPC_INDEX, offs);
uae_s32 idx = d - (uae_u32) & regs;
STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
} else {
data_check_end(8, 12);
uae_s32 offs = data_long_offs(d);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
offs = data_long_offs(s);
LDR_rRI(REG_WORK2, RPC_INDEX, offs);
STR_rR(REG_WORK2, REG_WORK1);
}
#endif
}
MENDFUNC(2,mov_l_mi,(IMM d, IMM s))
@ -84,12 +206,14 @@ MIDFUNC(2,shll_l_ri,(RW4 r, IMM i))
if (!i)
return;
if (isconst(r)) {
live.state[r].val<<=i;
live.state[r].val <<= i;
return;
}
r = rmw(r, 4, 4);
raw_shll_l_ri(r, i);
r = rmw(r);
LSL_rri(r,r, i & 0x1f);
unlock2(r);
}
MENDFUNC(2,shll_l_ri,(RW4 r, IMM i))
@ -97,66 +221,25 @@ MENDFUNC(2,shll_l_ri,(RW4 r, IMM i))
MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
{
// Only used in calc_disp_ea_020() -> flags not relevant and never modified
int isrmw;
if (isconst(s)) {
set_const(d, (uae_s32)(uae_s16)live.state[s].val);
return;
}
isrmw = (s == d);
if (!isrmw) {
s = readreg(s, 2);
d = writereg(d, 4);
}
else { /* If we try to lock this twice, with different sizes, we are in trouble! */
s = d = rmw(s, 4, 2);
int s_is_d = (s == d);
if (!s_is_d) {
s = readreg(s);
d = writereg(d);
} else {
s = d = rmw(s);
}
SIGNED16_REG_2_REG(d, s);
if (!isrmw) {
if (!s_is_d)
unlock2(d);
unlock2(s);
}
else {
unlock2(s);
}
unlock2(s);
}
MENDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
MIDFUNC(2,mov_b_rr,(W1 d, RR1 s))
{
if (d == s)
return;
if (isconst(s)) {
COMPCALL(mov_b_ri)(d, (uae_u8)live.state[s].val);
return;
}
s = readreg(s, 1);
d = writereg(d, 1);
raw_mov_b_rr(d, s);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,mov_b_rr,(W1 d, RR1 s))
MIDFUNC(2,mov_w_rr,(W2 d, RR2 s))
{
if (d == s)
return;
if (isconst(s)) {
COMPCALL(mov_w_ri)(d, (uae_u16)live.state[s].val);
return;
}
s = readreg(s, 2);
d = writereg(d, 2);
raw_mov_w_rr(d, s);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,mov_w_rr,(W2 d, RR2 s))
MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset))
{
if (isconst(s)) {
@ -164,11 +247,29 @@ MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset))
return;
}
s = readreg(s, 4);
d = writereg(d, 4);
raw_lea_l_brr(d, s, offset);
unlock2(d);
unlock2(s);
int s_is_d = (s == d);
if(s_is_d) {
s = d = rmw(d);
} else {
s = readreg(s);
d = writereg(d);
}
if(CHECK32(offset)) {
ADD_rri(d, s, offset);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, offset);
if(offset >> 16)
MOVT_ri16(REG_WORK1, offset >> 16);
#else
uae_s32 offs = data_long_offs(offset);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
ADD_rrr(d, s, REG_WORK1);
}
EXIT_REGS(d,s);
}
MENDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset))
@ -179,10 +280,23 @@ MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
return;
}
s = readreg(s, 4);
index = readreg(index, 4);
d = writereg(d, 4);
raw_lea_l_brr_indexed(d, s, index, factor, offset);
s = readreg(s);
index = readreg(index);
d = writereg(d);
int shft;
switch(factor) {
case 1: shft=0; break;
case 2: shft=1; break;
case 4: shft=2; break;
case 8: shft=3; break;
default: abort();
}
SIGNED8_IMM_2_REG(REG_WORK1, offset);
ADD_rrr(REG_WORK1, s, REG_WORK1);
ADD_rrrLSLi(d, REG_WORK1, index, shft);
unlock2(d);
unlock2(index);
unlock2(s);
@ -191,10 +305,21 @@ MENDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
{
s = readreg(s, 4);
index = readreg(index, 4);
d = writereg(d, 4);
raw_lea_l_rr_indexed(d, s, index, factor);
s = readreg(s);
index = readreg(index);
d = writereg(d);
int shft;
switch(factor) {
case 1: shft=0; break;
case 2: shft=1; break;
case 4: shft=2; break;
case 8: shft=3; break;
default: abort();
}
ADD_rrrLSLi(d, s, index, shft);
unlock2(d);
unlock2(index);
unlock2(s);
@ -214,12 +339,11 @@ MIDFUNC(2,mov_l_rr,(W4 d, RR4 s))
}
olds = s;
disassociate(d);
s = readreg(s, 4);
s = readreg(s);
live.state[d].realreg = s;
live.state[d].realind = live.nat[s].nholds;
live.state[d].val = live.state[olds].val;
live.state[d].validsize = 4;
live.state[d].dirtysize = 4;
set_status(d, DIRTY);
live.nat[s].holds[live.nat[s].nholds] = d;
@ -235,16 +359,46 @@ MIDFUNC(2,mov_l_mr,(IMM d, RR4 s))
return;
}
s = readreg(s, 4);
raw_mov_l_mr(d, s);
s = readreg(s);
if(d >= (uae_u32) &regs && d < ((uae_u32) &regs) + sizeof(struct regstruct)) {
uae_s32 idx = d - (uae_u32) &regs;
STR_rRI(s, R_REGSTRUCT, idx);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, d);
if(d >> 16)
MOVT_ri16(REG_WORK1, d >> 16);
#else
uae_s32 offs = data_long_offs(d);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
STR_rR(s, REG_WORK1);
}
unlock2(s);
}
MENDFUNC(2,mov_l_mr,(IMM d, RR4 s))
MIDFUNC(2,mov_l_rm,(W4 d, IMM s))
{
d = writereg(d, 4);
raw_mov_l_rm(d, s);
d = writereg(d);
if(s >= (uae_u32) &regs && s < ((uae_u32) &regs) + sizeof(struct regstruct)) {
uae_s32 idx = s - (uae_u32) & regs;
LDR_rRI(d, R_REGSTRUCT, idx);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, s);
if(s >> 16)
MOVT_ri16(REG_WORK1, s >> 16);
#else
uae_s32 offs = data_long_offs(s);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
LDR_rR(d, REG_WORK1);
}
unlock2(d);
}
MENDFUNC(2,mov_l_rm,(W4 d, IMM s))
@ -252,41 +406,28 @@ MENDFUNC(2,mov_l_rm,(W4 d, IMM s))
MIDFUNC(2,mov_l_ri,(W4 d, IMM s))
{
set_const(d, s);
return;
}
MENDFUNC(2,mov_l_ri,(W4 d, IMM s))
MIDFUNC(2,mov_w_ri,(W2 d, IMM s))
{
d = writereg(d, 2);
raw_mov_w_ri(d, s);
unlock2(d);
}
MENDFUNC(2,mov_w_ri,(W2 d, IMM s))
MIDFUNC(2,mov_b_ri,(W1 d, IMM s))
{
d = writereg(d, 1);
raw_mov_b_ri(d, s);
unlock2(d);
if(d < 16) {
if (isconst(d)) {
set_const(d, (live.state[d].val & 0xffffff00) | (s & 0x000000ff));
return;
}
d = rmw(d);
BIC_rri(d, d, 0xff);
ORR_rri(d, d, (s & 0xff));
unlock2(d);
} else {
set_const(d, s & 0xff);
}
}
MENDFUNC(2,mov_b_ri,(W1 d, IMM s))
MIDFUNC(2,add_l,(RW4 d, RR4 s))
{
if (isconst(s)) {
COMPCALL(add_l_ri)(d, live.state[s].val);
return;
}
s = readreg(s, 4);
d = rmw(d, 4, 4);
raw_add_l(d, s);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,add_l,(RW4 d, RR4 s))
MIDFUNC(2,sub_l_ri,(RW4 d, IMM i))
{
if (!i)
@ -296,44 +437,53 @@ MIDFUNC(2,sub_l_ri,(RW4 d, IMM i))
return;
}
d = rmw(d, 4, 4);
raw_sub_l_ri(d, i);
d = rmw(d);
if(CHECK32(i)) {
SUB_rri(d, d, i);
} else {
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, i);
if(i >> 16)
MOVT_ri16(REG_WORK1, i >> 16);
#else
uae_s32 offs = data_long_offs(i);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
SUB_rrr(d, d, REG_WORK1);
}
unlock2(d);
}
MENDFUNC(2,sub_l_ri,(RW4 d, IMM i))
MIDFUNC(2,sub_w_ri,(RW2 d, IMM i))
{
// This function is only called with i = 1
// Caller needs flags...
clobber_flags();
d = rmw(d, 2, 2);
raw_sub_w_ri(d, i);
d = rmw(d);
LSL_rri(REG_WORK2, d, 16);
SUBS_rri(REG_WORK2, REG_WORK2, (i & 0xff) << 16);
PKHTB_rrrASRi(d, d, REG_WORK2, 16);
MRS_CPSR(REG_WORK1);
EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
MSR_CPSRf_r(REG_WORK1);
unlock2(d);
}
MENDFUNC(2,sub_w_ri,(RW2 d, IMM i))
MIDFUNC(2,add_l_ri,(RW4 d, IMM i))
{
if (!i)
return;
if (isconst(d)) {
live.state[d].val += i;
return;
}
d = rmw(d, 4, 4);
raw_add_l_ri(d, i);
unlock2(d);
}
MENDFUNC(2,add_l_ri,(RW4 d, IMM i))
MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2))
MIDFUNC(3,call_r_02,(RR4 r, RR4 in1, RR4 in2))
{
clobber_flags();
in1 = readreg_specific(in1, isize1, REG_PAR1);
in2 = readreg_specific(in2, isize2, REG_PAR2);
r = readreg(r, 4);
in1 = readreg_specific(in1, REG_PAR1);
in2 = readreg_specific(in2, REG_PAR2);
r = readreg(r);
prepare_for_call_1();
unlock2(r);
unlock2(in1);
@ -341,22 +491,17 @@ MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2))
prepare_for_call_2();
compemu_raw_call_r(r);
}
MENDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2))
MENDFUNC(3,call_r_02,(RR4 r, RR4 in1, RR4 in2))
MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize))
MIDFUNC(3,call_r_11,(W4 out1, RR4 r, RR4 in1))
{
clobber_flags();
if (osize == 4) {
if (out1 != in1 && out1 != r) {
COMPCALL(forget_about)(out1);
}
}
else {
tomem_c(out1);
if (out1 != in1 && out1 != r) {
COMPCALL(forget_about)(out1);
}
in1 = readreg_specific(in1, isize, REG_PAR1);
r = readreg(r, 4);
in1 = readreg_specific(in1, REG_PAR1);
r = readreg(r);
prepare_for_call_1();
unlock2(in1);
@ -372,11 +517,10 @@ MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize))
live.state[out1].realreg = REG_RESULT;
live.state[out1].realind = 0;
live.state[out1].val = 0;
live.state[out1].validsize = osize;
live.state[out1].dirtysize = osize;
live.state[out1].validsize = 4;
set_status(out1, DIRTY);
}
MENDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize))
MENDFUNC(3,call_r_11,(W4 out1, RR4 r, RR4 in1))
/* forget_about() takes a mid-layer register */
MIDFUNC(1,forget_about,(W4 r))
@ -398,9 +542,9 @@ MIDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
return;
}
s = readreg(s, 4);
d = rmw(d, 4, 4);
raw_ADD_l_rr(d, s);
s = readreg(s);
d = rmw(d);
ADD_rrr(d, d, s);
unlock2(d);
unlock2(s);
}
@ -415,13 +559,20 @@ MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i))
return;
}
d = rmw(d, 4, 4);
d = rmw(d);
if(CHECK32(i)) {
raw_ADD_l_rri(d, d, i);
ADD_rri(d, d, i);
} else {
raw_LDR_l_ri(REG_WORK1, i);
raw_ADD_l_rr(d, REG_WORK1);
#ifdef ARMV6T2
MOVW_ri16(REG_WORK1, i);
if(i >> 16)
MOVT_ri16(REG_WORK1, i >> 16);
#else
uae_s32 offs = data_long_offs(i);
LDR_rRI(REG_WORK1, RPC_INDEX, offs);
#endif
ADD_rrr(d, d, REG_WORK1);
}
unlock2(d);
@ -437,8 +588,8 @@ MIDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i))
return;
}
d = rmw(d, 4, 4);
raw_ADD_l_rri(d, d, i);
d = rmw(d);
ADD_rri(d, d, i);
unlock2(d);
}
MENDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i))
@ -452,8 +603,8 @@ MIDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i))
return;
}
d = rmw(d, 4, 4);
raw_SUB_l_rri(d, d, i);
d = rmw(d);
SUB_rri(d, d, i);
unlock2(d);
}
MENDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i))
@ -494,7 +645,7 @@ MIDFUNC(1,f_forget_about,(FW r))
{
if (f_isinreg(r))
f_disassociate(r);
live.fate[r].status=UNDEF;
live.fate[r].status = UNDEF;
}
MENDFUNC(1,f_forget_about,(FW r))
@ -519,7 +670,7 @@ MENDFUNC(2,fmov_rr,(FW d, FR s))
MIDFUNC(2,fmov_l_rr,(FW d, RR4 s))
{
s = readreg(s, 4);
s = readreg(s);
d = f_writereg(d);
raw_fmov_l_rr(d, s);
f_unlock(d);
@ -529,7 +680,7 @@ MENDFUNC(2,fmov_l_rr,(FW d, RR4 s))
MIDFUNC(2,fmov_s_rr,(FW d, RR4 s))
{
s = readreg(s, 4);
s = readreg(s);
d = f_writereg(d);
raw_fmov_s_rr(d, s);
f_unlock(d);
@ -539,7 +690,7 @@ MENDFUNC(2,fmov_s_rr,(FW d, RR4 s))
MIDFUNC(2,fmov_w_rr,(FW d, RR2 s))
{
s = readreg(s, 2);
s = readreg(s);
d = f_writereg(d);
raw_fmov_w_rr(d, s);
f_unlock(d);
@ -549,7 +700,7 @@ MENDFUNC(2,fmov_w_rr,(FW d, RR2 s))
MIDFUNC(2,fmov_b_rr,(FW d, RR1 s))
{
s = readreg(s, 1);
s = readreg(s);
d = f_writereg(d);
raw_fmov_b_rr(d, s);
f_unlock(d);
@ -559,8 +710,8 @@ MENDFUNC(2,fmov_b_rr,(FW d, RR1 s))
MIDFUNC(3,fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
{
s1 = readreg(s1, 4);
s2 = readreg(s2, 4);
s1 = readreg(s1);
s2 = readreg(s2);
d = f_writereg(d);
raw_fmov_d_rrr(d, s1, s2);
f_unlock(d);
@ -605,7 +756,7 @@ MENDFUNC(2,fmov_s_ri,(FW d, IMM i))
MIDFUNC(2,fmov_to_l_rr,(W4 d, FR s))
{
s = f_readreg(s);
d = writereg(d, 4);
d = writereg(d);
raw_fmov_to_l_rr(d, s);
unlock2(d);
f_unlock(s);
@ -615,7 +766,7 @@ MENDFUNC(2,fmov_to_l_rr,(W4 d, FR s))
MIDFUNC(2,fmov_to_s_rr,(W4 d, FR s))
{
s = f_readreg(s);
d = writereg(d, 4);
d = writereg(d);
raw_fmov_to_s_rr(d, s);
unlock2(d);
f_unlock(s);
@ -625,8 +776,9 @@ MENDFUNC(2,fmov_to_s_rr,(W4 d, FR s))
MIDFUNC(2,fmov_to_w_rr,(W4 d, FR s))
{
s = f_readreg(s);
d = writereg(d, 2);
raw_fmov_to_w_rr(d, s);
INIT_WREG_w(d);
raw_fmov_to_w_rr(d, s, targetIsReg);
unlock2(d);
f_unlock(s);
}
@ -635,8 +787,9 @@ MENDFUNC(2,fmov_to_w_rr,(W4 d, FR s))
MIDFUNC(2,fmov_to_b_rr,(W4 d, FR s))
{
s = f_readreg(s);
d = writereg(d, 1);
raw_fmov_to_b_rr(d, s);
INIT_WREG_b(d);
raw_fmov_to_b_rr(d, s, targetIsReg);
unlock2(d);
f_unlock(s);
}
@ -701,8 +854,8 @@ MENDFUNC(2,fmov_rm,(FW r, MEMR m))
MIDFUNC(3,fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
{
s = f_readreg(s);
d1 = writereg(d1, 4);
d2 = writereg(d2, 4);
d1 = writereg(d1);
d2 = writereg(d2);
raw_fmov_to_d_rrr(d1, d2, s);
unlock2(d2);
unlock2(d1);
@ -917,7 +1070,7 @@ MIDFUNC(2,fp_from_exten_mr,(RR4 adr, FR s))
{
clobber_flags();
adr = readreg(adr, 4);
adr = readreg(adr);
s = f_readreg(s);
raw_fp_from_exten_mr(adr, s);
f_unlock(s);
@ -929,7 +1082,7 @@ MIDFUNC(2,fp_to_exten_rm,(FW d, RR4 adr))
{
clobber_flags();
adr = readreg(adr, 4);
adr = readreg(adr);
d = f_writereg(d);
raw_fp_to_exten_rm(d, adr);
unlock2(adr);
@ -939,7 +1092,7 @@ MENDFUNC(2,fp_to_exten_rm,(FW d, RR4 adr))
MIDFUNC(2,fp_from_double_mr,(RR4 adr, FR s))
{
adr = readreg(adr, 4);
adr = readreg(adr);
s = f_readreg(s);
raw_fp_from_double_mr(adr, s);
f_unlock(s);
@ -949,7 +1102,7 @@ MENDFUNC(2,fp_from_double_mr,(RR4 adr, FR s))
MIDFUNC(2,fp_to_double_rm,(FW d, RR4 adr))
{
adr = readreg(adr, 4);
adr = readreg(adr);
d = f_writereg(d);
raw_fp_to_double_rm(d, adr);
unlock2(adr);
@ -959,7 +1112,7 @@ MENDFUNC(2,fp_to_double_rm,(FW d, RR4 adr))
MIDFUNC(2,fp_fscc_ri,(RW4 d, int cc))
{
d = rmw(d, 4, 4);
d = rmw(d);
raw_fp_fscc_ri(d, cc);
unlock2(d);
}

9
src/jit/compemu_midfunc_arm.h
View file

@ -43,8 +43,6 @@ DECLARE_MIDFUNC(shll_l_ri(RW4 r, IMM i));
DECLARE_MIDFUNC(pop_l(W4 d));
DECLARE_MIDFUNC(push_l(RR4 s));
DECLARE_MIDFUNC(sign_extend_16_rr(W4 d, RR2 s));
DECLARE_MIDFUNC(mov_b_rr(W1 d, RR1 s));
DECLARE_MIDFUNC(mov_w_rr(W2 d, RR2 s));
DECLARE_MIDFUNC(lea_l_brr(W4 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(lea_l_brr_indexed(W4 d, RR4 s, RR4 index, IMM factor, IMM offset));
DECLARE_MIDFUNC(lea_l_rr_indexed(W4 d, RR4 s, RR4 index, IMM factor));
@ -53,14 +51,11 @@ DECLARE_MIDFUNC(mov_l_mr(IMM d, RR4 s));
DECLARE_MIDFUNC(mov_l_rm(W4 d, IMM s));
DECLARE_MIDFUNC(mov_b_rm(W1 d, IMM s));
DECLARE_MIDFUNC(mov_l_ri(W4 d, IMM s));
DECLARE_MIDFUNC(mov_w_ri(W2 d, IMM s));
DECLARE_MIDFUNC(mov_b_ri(W1 d, IMM s));
DECLARE_MIDFUNC(add_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(sub_l_ri(RW4 d, IMM i));
DECLARE_MIDFUNC(sub_w_ri(RW2 d, IMM i));
DECLARE_MIDFUNC(add_l_ri(RW4 d, IMM i));
DECLARE_MIDFUNC(call_r_02(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2));
DECLARE_MIDFUNC(call_r_11(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize));
DECLARE_MIDFUNC(call_r_02(RR4 r, RR4 in1, RR4 in2));
DECLARE_MIDFUNC(call_r_11(W4 out1, RR4 r, RR4 in1));
DECLARE_MIDFUNC(live_flags(void));
DECLARE_MIDFUNC(dont_care_flags(void));
DECLARE_MIDFUNC(make_flags_live(void));

5408
src/jit/compemu_midfunc_arm2.cpp
View file

File diff suppressed because it is too large Load diff

391
src/jit/compemu_midfunc_arm2.h
View file

@ -35,114 +35,122 @@
extern const uae_u32 ARM_CCR_MAP[];
// ADD
DECLARE_MIDFUNC(jnf_ADD(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_ADD_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_ADD_im8(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jff_ADD_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_ADD_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_ADD_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_ADD_b_imm(W4 d, RR1 s, IMM v));
DECLARE_MIDFUNC(jff_ADD_w_imm(W4 d, RR2 s, IMM v));
DECLARE_MIDFUNC(jff_ADD_l_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_ADD_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jnf_ADD_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jnf_ADD_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jnf_ADD_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_ADD_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_ADD_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_ADD_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jff_ADD_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jff_ADD_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jff_ADD_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_ADD_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_ADD_l(RW4 d, RR4 s));
// ADDA
DECLARE_MIDFUNC(jnf_ADDA_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jnf_ADDA_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ADDA_w(RW4 d, RR2 s));
DECLARE_MIDFUNC(jnf_ADDA_l(RW4 d, RR4 s));
// ADDX
DECLARE_MIDFUNC(jnf_ADDX(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_ADDX_b(W4 d, RR1 s, RR4 v));
DECLARE_MIDFUNC(jff_ADDX_w(W4 d, RR2 s, RR4 v));
DECLARE_MIDFUNC(jff_ADDX_l(W4 d, RR4 s, RR4 v));
// AND
DECLARE_MIDFUNC(jnf_AND(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_AND_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_AND_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_AND_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_ADDX_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_ADDX_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_ADDX_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_ADDX_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_ADDX_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_ADDX_l(RW4 d, RR4 s));
// ANDSR
DECLARE_MIDFUNC(jff_ANDSR(IMM s, IMM x));
// AND
DECLARE_MIDFUNC(jnf_AND_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jnf_AND_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jnf_AND_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jnf_AND_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_AND_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_AND_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_AND_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jff_AND_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jff_AND_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jff_AND_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_AND_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_AND_l(RW4 d, RR4 s));
// ASL
DECLARE_MIDFUNC(jff_ASL_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASL_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASL_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASL_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASL_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASL_l_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASL_b_imm(RW1 d, IMM i));
DECLARE_MIDFUNC(jff_ASL_w_imm(RW2 d, IMM i));
DECLARE_MIDFUNC(jff_ASL_l_imm(RW4 d, IMM i));
DECLARE_MIDFUNC(jff_ASL_b_reg(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ASL_w_reg(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ASL_l_reg(RW4 d, RR4 i));
// ASLW
DECLARE_MIDFUNC(jff_ASLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ASLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_ASLW(RW2 d));
DECLARE_MIDFUNC(jnf_ASLW(RW2 d));
// ASR
DECLARE_MIDFUNC(jnf_ASR_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_ASR_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_ASR_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASR_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASR_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASR_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_ASR_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ASR_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ASR_l_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASR_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASR_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASR_l_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ASR_b_imm(RW1 d, IMM i));
DECLARE_MIDFUNC(jnf_ASR_w_imm(RW2 d, IMM i));
DECLARE_MIDFUNC(jnf_ASR_l_imm(RW4 d, IMM i));
DECLARE_MIDFUNC(jff_ASR_b_imm(RW1 d, IMM i));
DECLARE_MIDFUNC(jff_ASR_w_imm(RW2 d, IMM i));
DECLARE_MIDFUNC(jff_ASR_l_imm(RW4 d, IMM i));
DECLARE_MIDFUNC(jnf_ASR_b_reg(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_ASR_w_reg(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_ASR_l_reg(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_ASR_b_reg(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ASR_w_reg(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ASR_l_reg(RW4 d, RR4 i));
// ASRW
DECLARE_MIDFUNC(jff_ASRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ASRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_ASRW(RW2 d));
DECLARE_MIDFUNC(jnf_ASRW(RW2 d));
// BCHG
DECLARE_MIDFUNC(jnf_BCHG_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BCHG_b_imm(RW1 d, IMM s));
DECLARE_MIDFUNC(jnf_BCHG_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BCHG_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BCHG_b_imm(RW1 d, IMM s));
DECLARE_MIDFUNC(jff_BCHG_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BCHG_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jnf_BCHG_b(RW1 d, RR4 s));
DECLARE_MIDFUNC(jnf_BCHG_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BCHG_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BCHG_b(RW1 d, RR4 s));
DECLARE_MIDFUNC(jff_BCHG_l(RW4 d, RR4 s));
// BCLR
DECLARE_MIDFUNC(jnf_BCLR_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BCLR_b_imm(RW1 d, IMM s));
DECLARE_MIDFUNC(jnf_BCLR_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BCLR_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jnf_BCLR_b(RW1 d, RR4 s));
DECLARE_MIDFUNC(jnf_BCLR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BCLR_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BCLR_b_imm(RW1 d, IMM s));
DECLARE_MIDFUNC(jff_BCLR_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BCLR_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BCLR_b(RW1 d, RR4 s));
DECLARE_MIDFUNC(jff_BCLR_l(RW4 d, RR4 s));
// BSET
DECLARE_MIDFUNC(jnf_BSET_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BSET_b_imm(RW1 d, IMM s));
DECLARE_MIDFUNC(jnf_BSET_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BSET_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jnf_BSET_b(RW1 d, RR4 s));
DECLARE_MIDFUNC(jnf_BSET_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BSET_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BSET_b_imm(RW1 d, IMM s));
DECLARE_MIDFUNC(jff_BSET_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BSET_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BSET_b(RW1 d, RR4 s));
DECLARE_MIDFUNC(jff_BSET_l(RW4 d, RR4 s));
// BTST
DECLARE_MIDFUNC(jff_BTST_b_imm(RR4 d, IMM s));
DECLARE_MIDFUNC(jff_BTST_b_imm(RR1 d, IMM s));
DECLARE_MIDFUNC(jff_BTST_l_imm(RR4 d, IMM s));
DECLARE_MIDFUNC(jff_BTST_b(RR4 d, RR4 s));
DECLARE_MIDFUNC(jff_BTST_b(RR1 d, RR4 s));
DECLARE_MIDFUNC(jff_BTST_l(RR4 d, RR4 s));
// CLR
DECLARE_MIDFUNC (jnf_CLR(W4 d));
DECLARE_MIDFUNC (jff_CLR(W4 d));
DECLARE_MIDFUNC (jnf_CLR_b(W1 d));
DECLARE_MIDFUNC (jnf_CLR_w(W2 d));
DECLARE_MIDFUNC (jnf_CLR_l(W4 d));
DECLARE_MIDFUNC (jff_CLR_b(W1 d));
DECLARE_MIDFUNC (jff_CLR_w(W2 d));
DECLARE_MIDFUNC (jff_CLR_l(W4 d));
// CMP
DECLARE_MIDFUNC(jff_CMP_b(RR1 d, RR1 s));
@ -154,15 +162,15 @@ DECLARE_MIDFUNC(jff_CMPA_w(RR2 d, RR2 s));
DECLARE_MIDFUNC(jff_CMPA_l(RR4 d, RR4 s));
// DBCC
DECLARE_MIDFUNC(jff_DBCC(RR2 d, IMM cc));
DECLARE_MIDFUNC(jff_DBCC(RW4 d, IMM cc));
// DIVU
DECLARE_MIDFUNC(jnf_DIVU(W4 d, RR4 s1, RR4 s2));
DECLARE_MIDFUNC(jff_DIVU(W4 d, RR4 s1, RR4 s2));
DECLARE_MIDFUNC(jnf_DIVU(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_DIVU(RW4 d, RR4 s));
// DIVS
DECLARE_MIDFUNC(jnf_DIVS(W4 d, RR4 s1, RR4 s2));
DECLARE_MIDFUNC(jff_DIVS(W4 d, RR4 s1, RR4 s2));
DECLARE_MIDFUNC(jnf_DIVS(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_DIVS(RW4 d, RR4 s));
// DIVL
DECLARE_MIDFUNC(jnf_DIVLU32(RW4 d, RR4 s1, W4 rem));
@ -171,56 +179,73 @@ DECLARE_MIDFUNC(jnf_DIVLS32(RW4 d, RR4 s1, W4 rem));
DECLARE_MIDFUNC(jff_DIVLS32(RW4 d, RR4 s1, W4 rem));
// EOR
DECLARE_MIDFUNC(jnf_EOR(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_EOR_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_EOR_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_EOR_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_EOR_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jnf_EOR_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jnf_EOR_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jnf_EOR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_EOR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_EOR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_EOR_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jff_EOR_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jff_EOR_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jff_EOR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_EOR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_EOR_l(RW4 d, RR4 s));
// EORSR
DECLARE_MIDFUNC(jff_EORSR(IMM s, IMM x));
// EXT
DECLARE_MIDFUNC(jnf_EXT_b(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_EXT_w(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_EXT_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_EXT_b(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_EXT_w(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_EXT_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_EXT_b(RW4 d));
DECLARE_MIDFUNC(jnf_EXT_w(RW4 d));
DECLARE_MIDFUNC(jnf_EXT_l(RW4 d));
DECLARE_MIDFUNC(jff_EXT_b(RW4 d));
DECLARE_MIDFUNC(jff_EXT_w(RW4 d));
DECLARE_MIDFUNC(jff_EXT_l(RW4 d));
// LSL
DECLARE_MIDFUNC(jnf_LSL_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_LSL_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSL_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSL_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSL_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSL_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSL_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSL_l_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_LSL_b_imm(RW1 d, IMM i));
DECLARE_MIDFUNC(jnf_LSL_w_imm(RW2 d, IMM i));
DECLARE_MIDFUNC(jnf_LSL_l_imm(RW4 d, IMM i));
DECLARE_MIDFUNC(jnf_LSL_b_reg(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_LSL_w_reg(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_LSL_l_reg(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_LSL_b_imm(RW1 d, IMM i));
DECLARE_MIDFUNC(jff_LSL_w_imm(RW2 d, IMM i));
DECLARE_MIDFUNC(jff_LSL_l_imm(RW4 d, IMM i));
DECLARE_MIDFUNC(jff_LSL_b_reg(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_LSL_w_reg(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_LSL_l_reg(RW4 d, RR4 i));
// LSLW
DECLARE_MIDFUNC(jff_LSLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_LSLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_LSLW(RW2 d));
DECLARE_MIDFUNC(jnf_LSLW(RW2 d));
// LSR
DECLARE_MIDFUNC(jnf_LSR_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_LSR_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_LSR_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSR_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSR_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSR_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_LSR_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_LSR_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_LSR_l_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSR_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSR_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSR_l_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_LSR_b_imm(RW1 d, IMM i));
DECLARE_MIDFUNC(jnf_LSR_w_imm(RW2 d, IMM i));
DECLARE_MIDFUNC(jnf_LSR_l_imm(RW4 d, IMM i));
DECLARE_MIDFUNC(jff_LSR_b_imm(RW1 d, IMM i));
DECLARE_MIDFUNC(jff_LSR_w_imm(RW2 d, IMM i));
DECLARE_MIDFUNC(jff_LSR_l_imm(RW4 d, IMM i));
DECLARE_MIDFUNC(jnf_LSR_b_reg(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_LSR_w_reg(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_LSR_l_reg(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_LSR_b_reg(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_LSR_w_reg(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_LSR_l_reg(RW4 d, RR4 i));
// LSRW
DECLARE_MIDFUNC(jff_LSRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_LSRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_LSRW(RW2 d));
DECLARE_MIDFUNC(jnf_LSRW(RW2 d));
// MOVE
DECLARE_MIDFUNC(jnf_MOVE(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_MOVE_b_imm(W4 d, IMM i));
DECLARE_MIDFUNC(jnf_MOVE_w_imm(W4 d, IMM i));
DECLARE_MIDFUNC(jnf_MOVE_l_imm(W4 d, IMM i));
DECLARE_MIDFUNC(jnf_MOVE_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jnf_MOVE_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jnf_MOVE_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_MOVE_b_imm(W4 d, IMM i));
DECLARE_MIDFUNC(jff_MOVE_w_imm(W4 d, IMM i));
DECLARE_MIDFUNC(jff_MOVE_l_imm(W4 d, IMM i));
@ -260,110 +285,106 @@ DECLARE_MIDFUNC (jnf_MULU64(RW4 d, RW4 s));
DECLARE_MIDFUNC (jff_MULU64(RW4 d, RW4 s));
// NEG
DECLARE_MIDFUNC(jnf_NEG_b(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_NEG_w(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_NEG_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_NEG_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jff_NEG_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jff_NEG_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_NEG_b(RW1 d));
DECLARE_MIDFUNC(jnf_NEG_w(RW2 d));
DECLARE_MIDFUNC(jnf_NEG_l(RW4 d));
DECLARE_MIDFUNC(jff_NEG_b(RW1 d));
DECLARE_MIDFUNC(jff_NEG_w(RW2 d));
DECLARE_MIDFUNC(jff_NEG_l(RW4 d));
// NEGX
DECLARE_MIDFUNC(jnf_NEGX_b(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_NEGX_w(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_NEGX_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_NEGX_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jff_NEGX_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jff_NEGX_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_NEGX_b(RW1 d));
DECLARE_MIDFUNC(jnf_NEGX_w(RW2 d));
DECLARE_MIDFUNC(jnf_NEGX_l(RW4 d));
DECLARE_MIDFUNC(jff_NEGX_b(RW1 d));
DECLARE_MIDFUNC(jff_NEGX_w(RW2 d));
DECLARE_MIDFUNC(jff_NEGX_l(RW4 d));
// NOT
DECLARE_MIDFUNC(jnf_NOT(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_NOT_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jff_NOT_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jff_NOT_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_NOT_b(RW1 d));
DECLARE_MIDFUNC(jnf_NOT_w(RW2 d));
DECLARE_MIDFUNC(jnf_NOT_l(RW4 d));
DECLARE_MIDFUNC(jff_NOT_b(RW1 d));
DECLARE_MIDFUNC(jff_NOT_w(RW2 d));
DECLARE_MIDFUNC(jff_NOT_l(RW4 d));
// OR
DECLARE_MIDFUNC(jnf_OR(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_OR_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_OR_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_OR_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_OR_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jnf_OR_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jnf_OR_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jnf_OR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_OR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_OR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_OR_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jff_OR_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jff_OR_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jff_OR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_OR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_OR_l(RW4 d, RR4 s));
// ORSR
DECLARE_MIDFUNC(jff_ORSR(IMM s, IMM x));
// ROL
DECLARE_MIDFUNC(jnf_ROL_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROL_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROL_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROL_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_l(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_ROL_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ROL_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ROL_l(RW4 d, RR4 i));
// ROLW
DECLARE_MIDFUNC(jff_ROLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ROLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_ROLW(RW2 d));
DECLARE_MIDFUNC(jnf_ROLW(RW2 d));
// RORW
DECLARE_MIDFUNC(jff_RORW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_RORW(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_RORW(RW2 d));
DECLARE_MIDFUNC(jnf_RORW(RW2 d));
// ROXL
DECLARE_MIDFUNC(jnf_ROXL_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROXL_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROXL_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_l(W4 d, RR4 s, RR4 i));
// ROXLW
DECLARE_MIDFUNC(jff_ROXLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ROXLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ROXL_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROXL_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROXL_l(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_l(RW4 d, RR4 i));
// ROR
DECLARE_MIDFUNC(jnf_ROR_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROR_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROR_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROR_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROR_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROR_l(W4 d, RR4 s, RR4 i));
// ROXR
DECLARE_MIDFUNC(jnf_ROXR_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROXR_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROXR_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_l(W4 d, RR4 s, RR4 i));
// ROXRW
DECLARE_MIDFUNC(jff_ROXRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ROXRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ROR_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROR_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROR_l(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_ROR_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ROR_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ROR_l(RW4 d, RR4 i));
// Scc
DECLARE_MIDFUNC(jnf_SCC(W4 d, IMM cc));
DECLARE_MIDFUNC(jnf_SCC(W1 d, IMM cc));
// SUB
DECLARE_MIDFUNC(jnf_SUB_b_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_SUB_b(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_SUB_w_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_SUB_w(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_SUB_l_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_SUB_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_SUB_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_SUB_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_SUB_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_SUB_b_imm(W4 d, RR1 s, IMM v));
DECLARE_MIDFUNC(jff_SUB_w_imm(W4 d, RR2 s, IMM v));
DECLARE_MIDFUNC(jff_SUB_l_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_SUB_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jnf_SUB_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jnf_SUB_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jnf_SUB_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_SUB_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_SUB_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_SUB_b_imm(RW1 d, IMM v));
DECLARE_MIDFUNC(jff_SUB_w_imm(RW2 d, IMM v));
DECLARE_MIDFUNC(jff_SUB_l_imm(RW4 d, IMM v));
DECLARE_MIDFUNC(jff_SUB_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_SUB_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_SUB_l(RW4 d, RR4 s));
// SUBA
DECLARE_MIDFUNC(jnf_SUBA_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jnf_SUBA_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_SUBA_w(RW4 d, RR2 s));
DECLARE_MIDFUNC(jnf_SUBA_l(RW4 d, RR4 s));
// SUBX
DECLARE_MIDFUNC(jnf_SUBX(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_SUBX_b(W4 d, RR1 s, RR4 v));
DECLARE_MIDFUNC(jff_SUBX_w(W4 d, RR2 s, RR4 v));
DECLARE_MIDFUNC(jff_SUBX_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_SUBX_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_SUBX_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_SUBX_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_SUBX_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_SUBX_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_SUBX_l(RW4 d, RR4 s));
// SWAP
DECLARE_MIDFUNC (jnf_SWAP(RW4 d));

157
src/jit/compemu_support.cpp
View file

@ -178,10 +178,10 @@ extern const struct comptbl op_smalltbl_0_comp_ff[];
static bigstate live;
static int writereg(int r, int size);
static int writereg(int r);
static void unlock2(int r);
static void setlock(int r);
static int readreg_specific(int r, int size, int spec);
static int readreg_specific(int r, int spec);
static void prepare_for_call_1(void);
static void prepare_for_call_2(void);
@ -751,7 +751,7 @@ static void make_flags_live_internal(void)
return;
if (live.flags_on_stack == VALID) {
int tmp;
tmp = readreg_specific(FLAGTMP, 4, -1);
tmp = readreg_specific(FLAGTMP, -1);
raw_reg_to_flags(tmp);
unlock2(tmp);
@ -772,7 +772,7 @@ static void flags_to_stack(void)
}
{
int tmp;
tmp = writereg(FLAGTMP, 4);
tmp = writereg(FLAGTMP);
raw_flags_to_reg(tmp);
unlock2(tmp);
}
@ -822,14 +822,8 @@ static void tomem(int r)
int rr = live.state[r].realreg;
if (live.state[r].status == DIRTY) {
switch (live.state[r].dirtysize) {
case 1: compemu_raw_mov_b_mr((uintptr)live.state[r].mem, rr); break;
case 2: compemu_raw_mov_w_mr((uintptr)live.state[r].mem, rr); break;
case 4: compemu_raw_mov_l_mr((uintptr)live.state[r].mem, rr); break;
default: abort();
}
compemu_raw_mov_l_mr((uintptr)live.state[r].mem, rr);
set_status(r, CLEAN);
live.state[r].dirtysize = 0;
}
}
@ -897,7 +891,6 @@ STATIC_INLINE void isclean(int r)
if (!isinreg(r))
return;
live.state[r].validsize = 4;
live.state[r].dirtysize = 0;
live.state[r].val = 0;
set_status(r, CLEAN);
}
@ -915,7 +908,7 @@ STATIC_INLINE void set_const(int r, uae_u32 val)
set_status(r, ISCONST);
}
static int alloc_reg_hinted(int r, int size, int willclobber, int hint)
static int alloc_reg_hinted(int r, int willclobber, int hint)
{
int bestreg;
uae_s32 when;
@ -947,23 +940,6 @@ static int alloc_reg_hinted(int r, int size, int willclobber, int hint)
int rr = live.state[r].realreg;
/* This will happen if we read a partially dirty register at a
bigger size */
if (size == 4 && live.state[r].validsize == 2) {
compemu_raw_mov_l_rm(bestreg, (uintptr)live.state[r].mem);
compemu_raw_MERGE_rr(rr, bestreg);
live.state[r].validsize = 4;
live.nat[rr].touched = touchcnt++;
return rr;
}
if (live.state[r].validsize == 1) {
if(size == 4) {
compemu_raw_mov_l_rm(bestreg, (uintptr)live.state[r].mem);
compemu_raw_MERGE8_rr(rr, bestreg);
live.state[r].validsize = 4;
live.nat[rr].touched = touchcnt++;
return rr;
}
/* Nothing yet for size == 2 */
}
evict(r);
}
@ -972,38 +948,23 @@ static int alloc_reg_hinted(int r, int size, int willclobber, int hint)
if (isconst(r)) {
compemu_raw_mov_l_ri(bestreg, live.state[r].val);
live.state[r].val = 0;
live.state[r].dirtysize = 4;
set_status(r, DIRTY);
}
else {
do_load_reg(bestreg, r);
live.state[r].dirtysize = 0;
set_status(r, CLEAN);
}
}
else {
live.state[r].val = 0;
live.state[r].dirtysize = 0;
set_status(r, CLEAN);
}
live.state[r].validsize = 4;
}
else { /* this is the easiest way, but not optimal. FIXME! */
/* Now it's trickier, but hopefully still OK */
if (!isconst(r) || size == 4) {
live.state[r].validsize = size;
live.state[r].dirtysize = size;
live.state[r].val = 0;
set_status(r, DIRTY);
}
else {
if (live.state[r].status != UNDEF)
compemu_raw_mov_l_ri(bestreg, live.state[r].val);
live.state[r].val = 0;
live.state[r].validsize = 4;
live.state[r].dirtysize = 4;
set_status(r, DIRTY);
}
else { /* this is the easiest way, but not optimal. */
live.state[r].validsize = 4;
live.state[r].val = 0;
set_status(r, DIRTY);
}
live.state[r].realreg = bestreg;
live.state[r].realind = live.nat[bestreg].nholds;
@ -1089,15 +1050,7 @@ STATIC_INLINE void make_exclusive(int r, int size)
/* Forget about r being in the register rr */
disassociate(r);
/* Get a new register, that we will clobber completely */
if (oldstate.status == DIRTY) {
/* If dirtysize is <4, we need a register that can handle the
eventual smaller memory store! Thanks to Quake68k for exposing
this detail ;-) */
nr = alloc_reg_hinted(r, oldstate.dirtysize, 1, -1);
}
else {
nr = alloc_reg_hinted(r, 4, 1, -1);
}
nr = alloc_reg_hinted(r, 1, -1);
nind = live.state[r].realind;
live.state[r] = oldstate; /* Keep all the old state info */
live.state[r].realreg = nr;
@ -1108,7 +1061,6 @@ STATIC_INLINE void make_exclusive(int r, int size)
/* Might as well compensate for the offset now */
compemu_raw_lea_l_brr(nr,rr,oldstate.val);
live.state[r].val = 0;
live.state[r].dirtysize = 4;
set_status(r, DIRTY);
}
else
@ -1117,7 +1069,7 @@ STATIC_INLINE void make_exclusive(int r, int size)
unlock2(rr);
}
STATIC_INLINE int readreg_general(int r, int size, int spec)
STATIC_INLINE int readreg_general(int r, int spec)
{
int n;
int answer = -1;
@ -1126,7 +1078,7 @@ STATIC_INLINE int readreg_general(int r, int size, int spec)
jit_log("WARNING: Unexpected read of undefined register %d", r);
}
if (isinreg(r) && live.state[r].validsize >= size) {
if (isinreg(r) && live.state[r].validsize >= 4) {
n = live.state[r].realreg;
answer = n;
@ -1137,7 +1089,7 @@ STATIC_INLINE int readreg_general(int r, int size, int spec)
/* either the value was in memory to start with, or it was evicted and
is in memory now */
if (answer < 0) {
answer = alloc_reg_hinted(r, spec >= 0 ? 4 : size, 0, spec);
answer = alloc_reg_hinted(r, 0, spec);
}
if (spec >= 0 && spec != answer) {
@ -1151,39 +1103,34 @@ STATIC_INLINE int readreg_general(int r, int size, int spec)
}
static int readreg(int r, int size)
static int readreg(int r)
{
return readreg_general(r, size, -1);
return readreg_general(r, -1);
}
static int readreg_specific(int r, int size, int spec)
static int readreg_specific(int r, int spec)
{
return readreg_general(r, size, spec);
return readreg_general(r, spec);
}
/* writereg(r, size, spec)
/* writereg(r)
*
* INPUT
* - r : mid-layer register
* - size : requested size (1/2/4)
*
* OUTPUT
* - hard (physical, x86 here) register allocated to virtual register r
*/
static int writereg(int r, int size)
static int writereg(int r)
{
int n;
int answer = -1;
make_exclusive(r, size);
make_exclusive(r, 4);
if (isinreg(r)) {
int nvsize = size > live.state[r].validsize ? size : live.state[r].validsize;
int ndsize = size > live.state[r].dirtysize ? size : live.state[r].dirtysize;
n = live.state[r].realreg;
live.state[r].dirtysize = ndsize;
live.state[r].validsize = nvsize;
live.state[r].validsize = 4;
answer = n;
if (answer < 0)
@ -1192,23 +1139,18 @@ static int writereg(int r, int size)
/* either the value was in memory to start with, or it was evicted and
is in memory now */
if (answer < 0) {
answer = alloc_reg_hinted(r, size, 1, -1);
answer = alloc_reg_hinted(r, 1, -1);
}
if (live.state[r].status == UNDEF)
live.state[r].validsize = 4;
live.state[r].dirtysize = size > live.state[r].dirtysize ? size : live.state[r].dirtysize;
live.state[r].validsize = size > live.state[r].validsize ? size : live.state[r].validsize;
live.state[r].validsize = 4;
live.nat[answer].locked++;
live.nat[answer].touched = touchcnt++;
if (size == 4) {
live.state[r].val = 0;
}
live.state[r].val = 0;
set_status(r, DIRTY);
return answer;
}
static int rmw(int r, int wsize, int rsize)
static int rmw(int r)
{
int n;
int answer = -1;
@ -1218,7 +1160,7 @@ static int rmw(int r, int wsize, int rsize)
}
make_exclusive(r, 0);
if (isinreg(r) && live.state[r].validsize >= rsize) {
if (isinreg(r) && live.state[r].validsize >= 4) {
n = live.state[r].realreg;
answer = n;
@ -1228,13 +1170,10 @@ static int rmw(int r, int wsize, int rsize)
/* either the value was in memory to start with, or it was evicted and
is in memory now */
if (answer < 0) {
answer = alloc_reg_hinted(r, rsize, 0, -1);
answer = alloc_reg_hinted(r, 0, -1);
}
if (wsize > live.state[r].dirtysize)
live.state[r].dirtysize = wsize;
if (wsize > live.state[r].validsize)
live.state[r].validsize = wsize;
live.state[r].validsize = 4;
set_status(r, DIRTY);
live.nat[answer].locked++;
@ -1405,7 +1344,7 @@ uae_u32 get_const(int r)
void sync_m68k_pc(void)
{
if (m68k_pc_offset) {
add_l_ri(PC_P, m68k_pc_offset);
arm_ADD_l_ri(PC_P, m68k_pc_offset);
comp_pc_p += m68k_pc_offset;
m68k_pc_offset = 0;
}
@ -1724,18 +1663,18 @@ static void writemem_real(int address, int source, int size)
}
}
STATIC_INLINE void writemem_special(int address, int source, int offset, int size, int tmp)
STATIC_INLINE void writemem_special(int address, int source, int offset, int tmp)
{
jnf_MEM_GETBANKFUNC(tmp, address, offset);
/* Now tmp holds the address of the b/w/lput function */
call_r_02(tmp, address, source, 4, size);
call_r_02(tmp, address, source);
forget_about(tmp);
}
void writebyte(int address, int source, int tmp)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 20, 1, tmp);
writemem_special(address, source, 20, tmp);
else
writemem_real(address, source, 1);
}
@ -1743,7 +1682,7 @@ void writebyte(int address, int source, int tmp)
void writeword(int address, int source, int tmp)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 16, 2, tmp);
writemem_special(address, source, 16, tmp);
else
writemem_real(address, source, 2);
}
@ -1751,7 +1690,7 @@ void writeword(int address, int source, int tmp)
void writelong(int address, int source, int tmp)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 12, 4, tmp);
writemem_special(address, source, 12, tmp);
else
writemem_real(address, source, 4);
}
@ -1781,7 +1720,7 @@ STATIC_INLINE void writemem_real_clobber(int address, int source, int size)
void writeword_clobber(int address, int source, int tmp)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 16, 2, tmp);
writemem_special(address, source, 16, tmp);
else
writemem_real_clobber(address, source, 2);
}
@ -1789,7 +1728,7 @@ void writeword_clobber(int address, int source, int tmp)
void writelong_clobber(int address, int source, int tmp)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 12, 4, tmp);
writemem_special(address, source, 12, tmp);
else
writemem_real_clobber(address, source, 4);
}
@ -1819,18 +1758,18 @@ static void readmem_real(int address, int dest, int size)
}
}
STATIC_INLINE void readmem_special(int address, int dest, int offset, int size, int tmp)
STATIC_INLINE void readmem_special(int address, int dest, int offset, int tmp)
{
jnf_MEM_GETBANKFUNC(tmp, address, offset);
/* Now tmp holds the address of the b/w/lget function */
call_r_11(dest, tmp, address, size, 4);
call_r_11(dest, tmp, address);
forget_about(tmp);
}
void readbyte(int address, int dest, int tmp)
{
if (special_mem & S_READ)
readmem_special(address, dest, 8, 1, tmp);
readmem_special(address, dest, 8, tmp);
else
readmem_real(address, dest, 1);
}
@ -1838,7 +1777,7 @@ void readbyte(int address, int dest, int tmp)
void readword(int address, int dest, int tmp)
{
if (special_mem & S_READ)
readmem_special(address, dest, 4, 2, tmp);
readmem_special(address, dest, 4, tmp);
else
readmem_real(address, dest, 2);
}
@ -1846,7 +1785,7 @@ void readword(int address, int dest, int tmp)
void readlong(int address, int dest, int tmp)
{
if (special_mem & S_READ)
readmem_special(address, dest, 0, 4, tmp);
readmem_special(address, dest, 0, tmp);
else
readmem_real(address, dest, 4);
}
@ -1854,7 +1793,7 @@ void readlong(int address, int dest, int tmp)
/* This one might appear a bit odd... */
STATIC_INLINE void get_n_addr_old(int address, int dest, int tmp)
{
readmem_special(address, dest, 24, 4, tmp);
readmem_special(address, dest, 24, tmp);
}
STATIC_INLINE void get_n_addr_real(int address, int dest)
@ -1915,13 +1854,13 @@ void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
/* target is now regd */
if (!ignorebase)
add_l(target, base);
add_l_ri(target, addbase);
arm_ADD_l(target, base);
arm_ADD_l_ri(target, addbase);
if (dp&0x03) readlong(target, target, tmp);
} else { /* do the getlong first, then add regd */
if (!ignorebase) {
mov_l_rr(target, base);
add_l_ri(target, addbase);
arm_ADD_l_ri(target, addbase);
}
else
mov_l_ri(target, addbase);
@ -1934,10 +1873,10 @@ void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
mov_l_rr(tmp, reg);
shll_l_ri(tmp, regd_shift);
/* tmp is now regd */
add_l(target, tmp);
arm_ADD_l(target, tmp);
}
}
add_l_ri(target, outer);
arm_ADD_l_ri(target, outer);
}
else { /* 68000 version */
if ((dp & 0x800) == 0) { /* Sign extend */

1071
src/jit/gencomp_arm.cpp
View file

File diff suppressed because it is too large Load diff

2
src/osdep/amiberry_mem.cpp
View file

@ -42,7 +42,7 @@ void free_AmigaMem(void)
#ifdef AMIBERRY
munmap(regs.natmem_offset, natmem_size + BARRIER);
#else
free(regs.natmem_offset);
free(regs.natmem_offset);
#endif
regs.natmem_offset = nullptr;
}