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WIP - merge from Pandora's port

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This commit is contained in:
Dimitris Panokostas 2017-09-18 10:41:47 +02:00
parent 546562cff3
commit a2850730e0
309 changed files with 239342 additions and 114388 deletions
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1165
src/jit/codegen_arm.cpp
View file

File diff suppressed because it is too large Load diff

42
src/jit/codegen_arm.h
View file

@ -2,7 +2,7 @@
* compiler/codegen_arm.h - IA-32 and AMD64 code generator
*
* Copyright (c) 2013 Jens Heitmann of ARAnyM dev team (see AUTHORS)
*
*
* Inspired by Christian Bauer's Basilisk II
*
* This file is part of the ARAnyM project which builds a new and powerful
@ -174,31 +174,29 @@
/* Branch instructions */
#ifndef __ANDROID__
enum
{
_B, _BL, _BLX, _BX, _BXJ
enum {
_B, _BL, _BLX, _BX, _BXJ
};
#endif
/* Data processing instructions */
enum
{
_AND = 0,
_EOR,
_SUB,
_RSB,
_ADD,
_ADC,
_SBC,
_RSC,
_TST,
_TEQ,
_CMP,
_CMN,
_ORR,
_MOV,
_BIC,
_MVN
enum {
_AND = 0,
_EOR,
_SUB,
_RSB,
_ADD,
_ADC,
_SBC,
_RSC,
_TST,
_TEQ,
_CMP,
_CMN,
_ORR,
_MOV,
_BIC,
_MVN
};
/* Single instruction Multiple Data (SIMD) instructions */

147
src/jit/compemu.cpp
View file

@ -6,7 +6,6 @@
#include "newcpu.h"
#include "custom.h"
#include "comptbl.h"
#include "debug.h"
#include "compemu.h"
#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
@ -8531,9 +8530,6 @@ uae_u32 REGPARAM2 op_2190_0_comp_ff(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_3
/* MOVE.L (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2198_0_comp_ff(uae_u32 opcode)
{
@ -8557,6 +8553,9 @@ uae_u32 REGPARAM2 op_2198_0_comp_ff(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_3
/* MOVE.L -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21a0_0_comp_ff(uae_u32 opcode)
{
@ -12697,9 +12696,6 @@ uae_u32 REGPARAM2 op_42b9_0_comp_ff(uae_u32 opcode)
}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_4
/* NEG.B Dn */
uae_u32 REGPARAM2 op_4400_0_comp_ff(uae_u32 opcode)
{
@ -12718,6 +12714,9 @@ uae_u32 REGPARAM2 op_4400_0_comp_ff(uae_u32 opcode)
}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_4
/* NEG.B (An) */
uae_u32 REGPARAM2 op_4410_0_comp_ff(uae_u32 opcode)
{
@ -14475,6 +14474,21 @@ uae_u32 REGPARAM2 op_4a3b_0_comp_ff(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.B #<data>.B */
uae_u32 REGPARAM2 op_4a3c_0_comp_ff(uae_u32 opcode)
{
uae_u32 dodgy=0;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
{ uae_u8 scratchie=S1;
{ int src = scratchie++;
mov_l_ri(src,(uae_s32)(uae_s8)comp_get_ibyte((m68k_pc_offset+=2)-2));
dont_care_flags();
{ jff_TST_b(src);
live_flags();
}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.W Dn */
uae_u32 REGPARAM2 op_4a40_0_comp_ff(uae_u32 opcode)
{
@ -14675,6 +14689,21 @@ uae_u32 REGPARAM2 op_4a7b_0_comp_ff(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.W #<data>.W */
uae_u32 REGPARAM2 op_4a7c_0_comp_ff(uae_u32 opcode)
{
uae_u32 dodgy=0;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
{ uae_u8 scratchie=S1;
{ int src = scratchie++;
mov_l_ri(src,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
dont_care_flags();
{ jff_TST_w(src);
live_flags();
}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.L Dn */
uae_u32 REGPARAM2 op_4a80_0_comp_ff(uae_u32 opcode)
{
@ -14875,6 +14904,21 @@ uae_u32 REGPARAM2 op_4abb_0_comp_ff(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.L #<data>.L */
uae_u32 REGPARAM2 op_4abc_0_comp_ff(uae_u32 opcode)
{
uae_u32 dodgy=0;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
{ uae_u8 scratchie=S1;
{ int src = scratchie++;
mov_l_ri(src,comp_get_ilong((m68k_pc_offset+=4)-4));
dont_care_flags();
{ jff_TST_l(src);
live_flags();
}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* MULL.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_4c00_0_comp_ff(uae_u32 opcode)
{
@ -16700,6 +16744,9 @@ uae_u32 REGPARAM2 op_50a0_0_comp_ff(uae_u32 opcode)
}}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_5
/* ADDQ.L #<data>,(d16,An) */
uae_u32 REGPARAM2 op_50a8_0_comp_ff(uae_u32 opcode)
{
@ -16725,9 +16772,6 @@ uae_u32 REGPARAM2 op_50a8_0_comp_ff(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_5
/* ADDQ.L #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_50b0_0_comp_ff(uae_u32 opcode)
{
@ -20297,6 +20341,9 @@ uae_u32 REGPARAM2 op_6301_0_comp_ff(uae_u32 opcode)
}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_6
/* Bcc.L #<data>.L */
uae_u32 REGPARAM2 op_63ff_0_comp_ff(uae_u32 opcode)
{
@ -20320,9 +20367,6 @@ uae_u32 REGPARAM2 op_63ff_0_comp_ff(uae_u32 opcode)
}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_6
/* Bcc.W #<data>.W */
uae_u32 REGPARAM2 op_6400_0_comp_ff(uae_u32 opcode)
{
@ -24876,6 +24920,9 @@ uae_u32 REGPARAM2 op_b0a0_0_comp_ff(uae_u32 opcode)
}}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_7
/* CMP.L (d16,An),Dn */
uae_u32 REGPARAM2 op_b0a8_0_comp_ff(uae_u32 opcode)
{
@ -24898,9 +24945,6 @@ uae_u32 REGPARAM2 op_b0a8_0_comp_ff(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_7
/* CMP.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b0b0_0_comp_ff(uae_u32 opcode)
{
@ -39751,9 +39795,6 @@ uae_u32 REGPARAM2 op_2190_0_comp_nf(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_3
/* MOVE.L (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2198_0_comp_nf(uae_u32 opcode)
{
@ -39775,6 +39816,9 @@ uae_u32 REGPARAM2 op_2198_0_comp_nf(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_3
/* MOVE.L -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21a0_0_comp_nf(uae_u32 opcode)
{
@ -43575,9 +43619,6 @@ uae_u32 REGPARAM2 op_42b9_0_comp_nf(uae_u32 opcode)
}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_4
/* NEG.B Dn */
uae_u32 REGPARAM2 op_4400_0_comp_nf(uae_u32 opcode)
{
@ -43594,6 +43635,9 @@ uae_u32 REGPARAM2 op_4400_0_comp_nf(uae_u32 opcode)
}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_4
/* NEG.B (An) */
uae_u32 REGPARAM2 op_4410_0_comp_nf(uae_u32 opcode)
{
@ -45256,6 +45300,19 @@ uae_u32 REGPARAM2 op_4a3b_0_comp_nf(uae_u32 opcode)
}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.B #<data>.B */
uae_u32 REGPARAM2 op_4a3c_0_comp_nf(uae_u32 opcode)
{
uae_u32 dodgy=0;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
{ uae_u8 scratchie=S1;
{ int src = scratchie++;
mov_l_ri(src,(uae_s32)(uae_s8)comp_get_ibyte((m68k_pc_offset+=2)-2));
dont_care_flags();
}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.W Dn */
uae_u32 REGPARAM2 op_4a40_0_comp_nf(uae_u32 opcode)
{
@ -45434,6 +45491,19 @@ uae_u32 REGPARAM2 op_4a7b_0_comp_nf(uae_u32 opcode)
}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.W #<data>.W */
uae_u32 REGPARAM2 op_4a7c_0_comp_nf(uae_u32 opcode)
{
uae_u32 dodgy=0;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
{ uae_u8 scratchie=S1;
{ int src = scratchie++;
mov_l_ri(src,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
dont_care_flags();
}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.L Dn */
uae_u32 REGPARAM2 op_4a80_0_comp_nf(uae_u32 opcode)
{
@ -45612,6 +45682,19 @@ uae_u32 REGPARAM2 op_4abb_0_comp_nf(uae_u32 opcode)
}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* TST.L #<data>.L */
uae_u32 REGPARAM2 op_4abc_0_comp_nf(uae_u32 opcode)
{
uae_u32 dodgy=0;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
{ uae_u8 scratchie=S1;
{ int src = scratchie++;
mov_l_ri(src,comp_get_ilong((m68k_pc_offset+=4)-4));
dont_care_flags();
}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* MULL.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_4c00_0_comp_nf(uae_u32 opcode)
{
@ -47386,6 +47469,9 @@ uae_u32 REGPARAM2 op_50a0_0_comp_nf(uae_u32 opcode)
}}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_5
/* ADDQ.L #<data>,(d16,An) */
uae_u32 REGPARAM2 op_50a8_0_comp_nf(uae_u32 opcode)
{
@ -47409,9 +47495,6 @@ uae_u32 REGPARAM2 op_50a8_0_comp_nf(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_5
/* ADDQ.L #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_50b0_0_comp_nf(uae_u32 opcode)
{
@ -50927,6 +51010,9 @@ uae_u32 REGPARAM2 op_6301_0_comp_nf(uae_u32 opcode)
}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_6
/* Bcc.L #<data>.L */
uae_u32 REGPARAM2 op_63ff_0_comp_nf(uae_u32 opcode)
{
@ -50950,9 +51036,6 @@ uae_u32 REGPARAM2 op_63ff_0_comp_nf(uae_u32 opcode)
}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_6
/* Bcc.W #<data>.W */
uae_u32 REGPARAM2 op_6400_0_comp_nf(uae_u32 opcode)
{
@ -55265,6 +55348,9 @@ uae_u32 REGPARAM2 op_b0a0_0_comp_nf(uae_u32 opcode)
}}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_7
/* CMP.L (d16,An),Dn */
uae_u32 REGPARAM2 op_b0a8_0_comp_nf(uae_u32 opcode)
{
@ -55285,9 +55371,6 @@ uae_u32 REGPARAM2 op_b0a8_0_comp_nf(uae_u32 opcode)
}}}}} if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
#endif
#ifdef PART_7
/* CMP.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b0b0_0_comp_nf(uae_u32 opcode)
{
@ -61823,4 +61906,4 @@ return 0;
}
#endif
#endif
#endif

145
src/jit/compemu.h
View file

@ -2,7 +2,7 @@
* compiler/compemu.h - Public interface and definitions
*
* Copyright (c) 2001-2004 Milan Jurik of ARAnyM dev team (see AUTHORS)
*
*
* Inspired by Christian Bauer's Basilisk II
*
* This file is part of the ARAnyM project which builds a new and powerful
@ -29,12 +29,16 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
typedef uae_u32 uintptr;
#ifndef COMPEMU_H
#define COMPEMU_H
#define panicbug printf
typedef uae_u32 uintptr;
/* Flags for Bernie during development/debugging. Should go away eventually */
#define DISTRUST_CONSISTENT_MEM 0
/* Now that we do block chaining, and also have linked lists on each tag,
TAGMASK can be much smaller and still do its job. Saves several megs
of memory! */
#define TAGMASK 0x0000ffff
#define TAGSIZE (TAGMASK+1)
#define MAXRUN 1024
@ -45,15 +49,13 @@ extern uae_u32 start_pc;
struct blockinfo_t;
typedef struct
{
uae_u16* location;
uae_u8 cycles;
uae_u8 specmem;
typedef struct {
uae_u16* location;
uae_u8 cycles;
uae_u8 specmem;
} cpu_history;
typedef union
{
typedef union {
cpuop_func* handler;
struct blockinfo_t* bi;
} cacheline;
@ -75,8 +77,6 @@ typedef union
#define USE_CHECKSUM_INFO 1
#endif
#define USE_ALIAS 1
#define USE_F_ALIAS 1
#define COMP_DEBUG 0
#if COMP_DEBUG
@ -131,7 +131,6 @@ typedef union
/* Functions exposed to newcpu, or to what was moved from newcpu.c to
* compemu_support.c */
extern void compiler_init(void);
extern void compiler_exit(void);
extern void init_comp(void);
extern void flush(int save_regs);
@ -143,7 +142,8 @@ extern void set_cache_state(int enabled);
extern int get_cache_state(void);
extern uae_u32 get_jitted_size(void);
#ifdef JIT
extern void (*flush_icache)(uaecptr ptr, int n);
extern void flush_icache(int n);
extern void flush_icache_hard(int n);
#endif
extern void alloc_cache(void);
extern void compile_block(cpu_history* pc_hist, int blocklen, int totcyles);
@ -156,9 +156,6 @@ extern uae_u8* comp_pc_p;
extern void* pushall_call_handler;
#define VREGS 32
#ifdef USE_JIT_FPU
#define VFREGS 16
#endif
#define INMEM 1
#define CLEAN 2
@ -166,42 +163,28 @@ extern void* pushall_call_handler;
#define UNDEF 4
#define ISCONST 5
typedef struct
{
uae_u32* mem;
uae_u32 val;
uae_u8 status;
uae_s8 realreg; /* gb-- realreg can hold -1 */
uae_u8 realind; /* The index in the holds[] array */
uae_u8 validsize;
uae_u8 dirtysize;
typedef struct {
uae_u32* mem;
uae_u32 val;
uae_u8 status;
uae_s8 realreg; /* gb-- realreg can hold -1 */
uae_u8 realind; /* The index in the holds[] array */
uae_u8 validsize;
uae_u8 dirtysize;
} reg_status;
#ifdef USE_JIT_FPU
typedef struct
{
uae_u32* mem;
double val;
uae_u8 status;
uae_s8 realreg; /* gb-- realreg can hold -1 */
uae_u8 realind;
uae_u8 needflush;
} freg_status;
#endif
typedef struct
{
typedef struct {
uae_u8 use_flags;
uae_u8 set_flags;
uae_u8 is_addx;
uae_u8 cflow;
uae_u8 cflow;
} op_properties;
extern op_properties prop[65536];
STATIC_INLINE int end_block(uae_u16 opcode)
{
return (prop[opcode].cflow & fl_end_block);
return (prop[opcode].cflow & fl_end_block);
}
#define PC_P 16
@ -226,24 +209,13 @@ STATIC_INLINE int end_block(uae_u16 opcode)
#define FS2 10
#define FS3 11
typedef struct
{
uae_u32 touched;
uae_s8 holds[VREGS];
uae_u8 nholds;
uae_u8 locked;
typedef struct {
uae_u32 touched;
uae_s8 holds[VREGS];
uae_u8 nholds;
uae_u8 locked;
} n_status;
#ifdef USE_JIT_FPU
typedef struct
{
uae_u32 touched;
uae_s8 holds[VFREGS];
uae_u8 nholds;
uae_u8 locked;
} fn_status;
#endif
/* For flag handling */
#define NADA 1
#define TRASH 2
@ -254,31 +226,23 @@ typedef struct
#define NF_TOMEM 1
#define NF_HANDLER 2
typedef struct
{
typedef struct {
/* Integer part */
reg_status state[VREGS];
n_status nat[N_REGS];
uae_u32 flags_on_stack;
uae_u32 flags_in_flags;
uae_u32 flags_are_important;
#ifdef USE_JIT_FPU
/* FPU part */
freg_status fate[VFREGS];
fn_status fat[N_FREGS];
#endif
} bigstate;
typedef struct
{
typedef struct {
/* Integer part */
uae_s8 virt[VREGS];
uae_s8 nat[N_REGS];
uae_s8 virt[VREGS];
uae_s8 nat[N_REGS];
} smallstate;
extern int touchcnt;
#define IMM uae_s32
#define RR1 uae_u32
#define RR2 uae_u32
@ -310,7 +274,9 @@ extern int touchcnt;
#if defined(CPU_arm)
#include "compemu_midfunc_arm.h"
#include "compemu_midfunc_arm2.h"
#else
#endif
#if defined(CPU_i386) || defined(CPU_x86_64)
#include "compemu_midfunc_x86.h"
#endif
@ -343,24 +309,21 @@ extern void register_branch(uae_u32 not_taken, uae_u32 taken, uae_u8 cond);
struct blockinfo_t;
typedef struct dep_t
{
uae_u32* jmp_off;
struct blockinfo_t* target;
struct blockinfo_t* source;
struct dep_t** prev_p;
struct dep_t* next;
typedef struct dep_t {
uae_u32* jmp_off;
struct blockinfo_t* target;
struct blockinfo_t* source;
struct dep_t** prev_p;
struct dep_t* next;
} dependency;
typedef struct checksum_info_t
{
uae_u8 *start_p;
uae_u32 length;
struct checksum_info_t *next;
typedef struct checksum_info_t {
uae_u8 *start_p;
uae_u32 length;
struct checksum_info_t *next;
} checksum_info;
typedef struct blockinfo_t
{
typedef struct blockinfo_t {
uae_s32 count;
cpuop_func* direct_handler_to_use;
cpuop_func* handler_to_use;
@ -372,6 +335,7 @@ typedef struct blockinfo_t
cpuop_func* direct_pen;
cpuop_func* direct_pcc;
uae_u8* nexthandler;
uae_u8* pc_p;
uae_u32 c1;
@ -396,11 +360,6 @@ typedef struct blockinfo_t
dependency dep[2]; /* Holds things we depend on */
dependency* deplist; /* List of things that depend on this */
smallstate env;
#ifdef JIT_DEBUG
/* (gb) size of the compiled block (direct handler) */
uae_u32 direct_handler_size;
#endif
} blockinfo;
#define BI_INVALID 0
@ -422,3 +381,9 @@ void comp_fbcc_opp (uae_u32 opcode);
void comp_fsave_opp (uae_u32 opcode);
void comp_frestore_opp (uae_u32 opcode);
void comp_fpp_opp (uae_u32 opcode, uae_u16 extra);
void jit_abort(const TCHAR *format,...);
#define uae_p32(x) ((uae_u32)(x))
#endif /* COMPEMU_H */

50
src/jit/compemu_fpp.cpp
View file

@ -17,57 +17,9 @@
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "ersatz.h"
#include "compemu.h"
#if defined(JIT)
uae_u32 temp_fp[] = {0,0,0}; /* To convert between FP and <EA> */
/* 128 words, indexed through the low byte of the 68k fpu control word */
static const uae_u16 x86_fpucw[]={
0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, /* E-RN */
0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, /* E-RZ */
0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, /* E-RD */
0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, /* E-RU */
0x107f, 0x107f, 0x107f, 0x107f, 0x107f, 0x107f, 0x107f, 0x107f, /* S-RN */
0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, /* S-RZ */
0x147f, 0x147f, 0x147f, 0x147f, 0x147f, 0x147f, 0x147f, 0x147f, /* S-RD */
0x187f, 0x187f, 0x187f, 0x187f, 0x187f, 0x187f, 0x187f, 0x187f, /* S-RU */
0x127f, 0x127f, 0x127f, 0x127f, 0x127f, 0x127f, 0x127f, 0x127f, /* D-RN */
0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, /* D-RZ */
0x167f, 0x167f, 0x167f, 0x167f, 0x167f, 0x167f, 0x167f, 0x167f, /* D-RD */
0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, /* D-RU */
0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, /* ?-RN */
0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, /* ?-RZ */
0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, /* ?-RD */
0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f /* ?-RU */
};
static const int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
static const int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
/* return the required floating point precision or -1 for failure, 0=E, 1=S, 2=D */
STATIC_INLINE int comp_fp_get (uae_u32 opcode, uae_u16 extra, int treg)
{
printf("comp_fp_get not yet implemented\n");
return -1;
}
/* return of -1 means failure, >=0 means OK */
STATIC_INLINE int comp_fp_put (uae_u32 opcode, uae_u16 extra)
{
printf("comp_fp_put not yet implemented\n");
return -1;
}
/* return -1 for failure, or register number for success */
STATIC_INLINE int comp_fp_adr (uae_u32 opcode)
{
printf("comp_fp_adr not yet implemented\n");
return -1;
}
void comp_fdbcc_opp (uae_u32 opcode, uae_u16 extra)
{
@ -103,4 +55,4 @@ void comp_fpp_opp (uae_u32 opcode, uae_u16 extra)
{
printf("comp_fpp_opp not yet implemented\n");
}
#endif
#endif

548
src/jit/compemu_midfunc_arm.cpp
View file

@ -54,436 +54,402 @@
MIDFUNC(0,live_flags,(void))
{
live.flags_on_stack = TRASH;
live.flags_in_flags = VALID;
live.flags_are_important = 1;
live.flags_on_stack = TRASH;
live.flags_in_flags = VALID;
live.flags_are_important = 1;
}
MENDFUNC(0,live_flags,(void))
MIDFUNC(0,dont_care_flags,(void))
{
live.flags_are_important = 0;
live.flags_are_important = 0;
}
MENDFUNC(0,dont_care_flags,(void))
MIDFUNC(0,make_flags_live,(void))
{
make_flags_live_internal();
make_flags_live_internal();
}
MENDFUNC(0,make_flags_live,(void))
MIDFUNC(2,mov_l_mi,(IMM d, IMM s))
{
raw_mov_l_mi(d, s);
raw_mov_l_mi(d, s);
}
MENDFUNC(2,mov_l_mi,(IMM d, IMM s))
MIDFUNC(2,shll_l_ri,(RW4 r, IMM i))
{
// Only used in calc_disp_ea_020() -> flags not relevant and never modified
if (!i)
return;
if (isconst(r))
{
live.state[r].val<<=i;
return;
}
// Only used in calc_disp_ea_020() -> flags not relevant and never modified
if (!i)
return;
if (isconst(r)) {
live.state[r].val<<=i;
return;
}
r = rmw(r, 4, 4);
raw_shll_l_ri(r, i);
unlock2(r);
r = rmw(r, 4, 4);
raw_shll_l_ri(r, i);
unlock2(r);
}
MENDFUNC(2,shll_l_ri,(RW4 r, IMM i))
MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
{
// Only used in calc_disp_ea_020() -> flags not relevant and never modified
int isrmw;
// Only used in calc_disp_ea_020() -> flags not relevant and never modified
int isrmw;
if (isconst(s))
{
set_const(d, (uae_s32)(uae_s16)live.state[s].val);
return;
}
if (isconst(s)) {
set_const(d, (uae_s32)(uae_s16)live.state[s].val);
return;
}
isrmw = (s == d);
if (!isrmw)
{
s = readreg(s, 2);
d = writereg(d, 4);
}
else /* If we try to lock this twice, with different sizes, we are int trouble! */
{
s = d = rmw(s, 4, 2);
}
SIGNED16_REG_2_REG(d, s);
if (!isrmw)
{
unlock2(d);
unlock2(s);
}
else
{
unlock2(s);
}
isrmw = (s == d);
if (!isrmw) {
s = readreg(s, 2);
d = writereg(d, 4);
}
else { /* If we try to lock this twice, with different sizes, we are int trouble! */
s = d = rmw(s, 4, 2);
}
SIGNED16_REG_2_REG(d, s);
if (!isrmw) {
unlock2(d);
unlock2(s);
}
else {
unlock2(s);
}
}
MENDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
MIDFUNC(2,mov_b_rr,(W1 d, RR1 s))
{
if (d == s)
return;
if (isconst(s))
{
COMPCALL(mov_b_ri)(d, (uae_u8)live.state[s].val);
return;
}
if (d == s)
return;
if (isconst(s)) {
COMPCALL(mov_b_ri)(d, (uae_u8)live.state[s].val);
return;
}
s = readreg(s, 1);
d = writereg(d, 1);
raw_mov_b_rr(d, s);
unlock2(d);
unlock2(s);
s = readreg(s, 1);
d = writereg(d, 1);
raw_mov_b_rr(d, s);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,mov_b_rr,(W1 d, RR1 s))
MIDFUNC(2,mov_w_rr,(W2 d, RR2 s))
{
if (d == s)
return;
if (isconst(s))
{
COMPCALL(mov_w_ri)(d, (uae_u16)live.state[s].val);
return;
}
if (d == s)
return;
if (isconst(s)) {
COMPCALL(mov_w_ri)(d, (uae_u16)live.state[s].val);
return;
}
s = readreg(s, 2);
d = writereg(d, 2);
raw_mov_w_rr(d, s);
unlock2(d);
unlock2(s);
s = readreg(s, 2);
d = writereg(d, 2);
raw_mov_w_rr(d, s);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,mov_w_rr,(W2 d, RR2 s))
MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset))
{
if (isconst(s))
{
COMPCALL(mov_l_ri)(d, live.state[s].val+offset);
return;
}
if (isconst(s)) {
COMPCALL(mov_l_ri)(d, live.state[s].val+offset);
return;
}
s = readreg(s, 4);
d = writereg(d, 4);
raw_lea_l_brr(d, s, offset);
unlock2(d);
unlock2(s);
s = readreg(s, 4);
d = writereg(d, 4);
raw_lea_l_brr(d, s, offset);
unlock2(d);
unlock2(s);
}
MENDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset))
MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
{
if (!offset)
{
COMPCALL(lea_l_rr_indexed)(d, s, index, factor);
return;
}
s = readreg(s, 4);
index = readreg(index, 4);
d = writereg(d, 4);
raw_lea_l_brr_indexed(d, s, index, factor, offset);
unlock2(d);
unlock2(index);
unlock2(s);
if (!offset) {
COMPCALL(lea_l_rr_indexed)(d, s, index, factor);
return;
}
s = readreg(s, 4);
index = readreg(index, 4);
d = writereg(d, 4);
raw_lea_l_brr_indexed(d, s, index, factor, offset);
unlock2(d);
unlock2(index);
unlock2(s);
}
MENDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
{
s = readreg(s, 4);
index = readreg(index, 4);
d = writereg(d, 4);
raw_lea_l_rr_indexed(d, s, index, factor);
unlock2(d);
unlock2(index);
unlock2(s);
s = readreg(s, 4);
index = readreg(index, 4);
d = writereg(d, 4);
raw_lea_l_rr_indexed(d, s, index, factor);
unlock2(d);
unlock2(index);
unlock2(s);
}
MENDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
MIDFUNC(2,mov_l_rr,(W4 d, RR4 s))
{
int olds;
int olds;
if (d == s) /* How pointless! */
{
return;
}
if (isconst(s))
{
COMPCALL(mov_l_ri)(d, live.state[s].val);
return;
}
olds = s;
disassociate(d);
s = readreg(s, 4);
live.state[d].realreg = s;
live.state[d].realind = live.nat[s].nholds;
live.state[d].val = live.state[olds].val;
live.state[d].validsize = 4;
live.state[d].dirtysize = 4;
set_status(d, DIRTY);
if (d == s) { /* How pointless! */
return;
}
if (isconst(s)) {
COMPCALL(mov_l_ri)(d, live.state[s].val);
return;
}
olds = s;
disassociate(d);
s = readreg(s, 4);
live.state[d].realreg = s;
live.state[d].realind = live.nat[s].nholds;
live.state[d].val = live.state[olds].val;
live.state[d].validsize = 4;
live.state[d].dirtysize = 4;
set_status(d, DIRTY);
live.nat[s].holds[live.nat[s].nholds] = d;
live.nat[s].nholds++;
D2(panicbug("Added %d to nreg %d(%d), now holds %d regs", d, s, live.state[d].realind, live.nat[s].nholds));
unlock2(s);
live.nat[s].holds[live.nat[s].nholds] = d;
live.nat[s].nholds++;
#if defined(DEBUG) && DEBUG > 1
jit_log("Added %d to nreg %d(%d), now holds %d regs", d, s, live.state[d].realind, live.nat[s].nholds);
#endif
unlock2(s);
}
MENDFUNC(2,mov_l_rr,(W4 d, RR4 s))
MIDFUNC(2,mov_l_mr,(IMM d, RR4 s))
{
if (isconst(s))
{
COMPCALL(mov_l_mi)(d, live.state[s].val);
return;
}
s = readreg(s, 4);
raw_mov_l_mr(d, s);
unlock2(s);
if (isconst(s)) {
COMPCALL(mov_l_mi)(d, live.state[s].val);
return;
}
s = readreg(s, 4);
raw_mov_l_mr(d, s);
unlock2(s);
}
MENDFUNC(2,mov_l_mr,(IMM d, RR4 s))
MIDFUNC(2,mov_l_ri,(W4 d, IMM s))
{
set_const(d, s);
return;
set_const(d, s);
return;
}
MENDFUNC(2,mov_l_ri,(W4 d, IMM s))
MIDFUNC(2,mov_w_ri,(W2 d, IMM s))
{
d = writereg(d, 2);
raw_mov_w_ri(d, s);
unlock2(d);
d = writereg(d, 2);
raw_mov_w_ri(d, s);
unlock2(d);
}
MENDFUNC(2,mov_w_ri,(W2 d, IMM s))
MIDFUNC(2,mov_b_ri,(W1 d, IMM s))
{
d = writereg(d, 1);
raw_mov_b_ri(d, s);
unlock2(d);
d = writereg(d, 1);
raw_mov_b_ri(d, s);
unlock2(d);
}
MENDFUNC(2,mov_b_ri,(W1 d, IMM s))
MIDFUNC(2,add_l,(RW4 d, RR4 s))
{
if (isconst(s))
{
COMPCALL(add_l_ri)(d, live.state[s].val);
return;
}
if (isconst(s)) {
COMPCALL(add_l_ri)(d, live.state[s].val);
return;
}
s = readreg(s, 4);
d = rmw(d, 4, 4);
raw_add_l(d, s);
unlock2(d);
unlock2(s);
s = readreg(s, 4);
d = rmw(d, 4, 4);
raw_add_l(d, s);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,add_l,(RW4 d, RR4 s))
MIDFUNC(2,sub_l_ri,(RW4 d, IMM i))
{
if (!i)
return;
if (isconst(d))
{
live.state[d].val -= i;
return;
}
if (!i)
return;
if (isconst(d)) {
live.state[d].val -= i;
return;
}
d = rmw(d, 4, 4);
raw_sub_l_ri(d, i);
unlock2(d);
d = rmw(d, 4, 4);
raw_sub_l_ri(d, i);
unlock2(d);
}
MENDFUNC(2,sub_l_ri,(RW4 d, IMM i))
MIDFUNC(2,sub_w_ri,(RW2 d, IMM i))
{
// Caller needs flags...
clobber_flags();
// Caller needs flags...
clobber_flags();
d = rmw(d, 2, 2);
raw_sub_w_ri(d, i);
unlock2(d);
d = rmw(d, 2, 2);
raw_sub_w_ri(d, i);
unlock2(d);
}
MENDFUNC(2,sub_w_ri,(RW2 d, IMM i))
MIDFUNC(2,add_l_ri,(RW4 d, IMM i))
{
if (!i)
return;
if (isconst(d))
{
live.state[d].val += i;
return;
}
if (!i)
return;
if (isconst(d)) {
live.state[d].val += i;
return;
}
d = rmw(d, 4, 4);
raw_add_l_ri(d, i);
unlock2(d);
d = rmw(d, 4, 4);
raw_add_l_ri(d, i);
unlock2(d);
}
MENDFUNC(2,add_l_ri,(RW4 d, IMM i))
MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2))
{
clobber_flags();
in1 = readreg_specific(in1, isize1, REG_PAR1);
in2 = readreg_specific(in2, isize2, REG_PAR2);
r = readreg(r, 4);
prepare_for_call_1();
unlock2(r);
unlock2(in1);
unlock2(in2);
prepare_for_call_2();
compemu_raw_call_r(r);
clobber_flags();
in1 = readreg_specific(in1, isize1, REG_PAR1);
in2 = readreg_specific(in2, isize2, REG_PAR2);
r = readreg(r, 4);
prepare_for_call_1();
unlock2(r);
unlock2(in1);
unlock2(in2);
prepare_for_call_2();
compemu_raw_call_r(r);
}
MENDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2))
MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize))
{
clobber_flags();
if (osize == 4)
{
if (out1 != in1 && out1 != r)
{
COMPCALL(forget_about)(out1);
}
}
else
{
tomem_c(out1);
clobber_flags();
if (osize == 4) {
if (out1 != in1 && out1 != r) {
COMPCALL(forget_about)(out1);
}
}
else {
tomem_c(out1);
}
in1 = readreg_specific(in1, isize, REG_PAR1);
r = readreg(r, 4);
prepare_for_call_1();
in1 = readreg_specific(in1, isize, REG_PAR1);
r = readreg(r, 4);
prepare_for_call_1();
unlock2(in1);
unlock2(r);
unlock2(in1);
unlock2(r);
prepare_for_call_2();
compemu_raw_call_r(r);
prepare_for_call_2();
compemu_raw_call_r(r);
live.nat[REG_RESULT].holds[0] = out1;
live.nat[REG_RESULT].nholds = 1;
live.nat[REG_RESULT].touched = touchcnt++;
live.nat[REG_RESULT].holds[0] = out1;
live.nat[REG_RESULT].nholds = 1;
live.nat[REG_RESULT].touched = touchcnt++;
live.state[out1].realreg = REG_RESULT;
live.state[out1].realind = 0;
live.state[out1].val = 0;
live.state[out1].validsize = osize;
live.state[out1].dirtysize = osize;
set_status(out1, DIRTY);
live.state[out1].realreg = REG_RESULT;
live.state[out1].realind = 0;
live.state[out1].val = 0;
live.state[out1].validsize = osize;
live.state[out1].dirtysize = osize;
set_status(out1, DIRTY);
}
MENDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize))
/* forget_about() takes a mid-layer register */
MIDFUNC(1,forget_about,(W4 r))
{
if (isinreg(r))
disassociate(r);
live.state[r].val = 0;
set_status(r, UNDEF);
if (isinreg(r))
disassociate(r);
live.state[r].val = 0;
set_status(r, UNDEF);
}
MENDFUNC(1,forget_about,(W4 r))
#ifdef USE_JIT_FPU
MIDFUNC(1,f_forget_about,(FW r))
{
if (f_isinreg(r))
f_disassociate(r);
live.fate[r].status=UNDEF;
}
MENDFUNC(1,f_forget_about,(FW r))
#endif
// ARM optimized functions
MIDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
{
if (isconst(s))
{
COMPCALL(arm_ADD_l_ri)(d,live.state[s].val);
return;
}
if (isconst(s)) {
COMPCALL(arm_ADD_l_ri)(d,live.state[s].val);
return;
}
s = readreg(s, 4);
d = rmw(d, 4, 4);
raw_ADD_l_rr(d, s);
unlock2(d);
unlock2(s);
s = readreg(s, 4);
d = rmw(d, 4, 4);
raw_ADD_l_rr(d, s);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i))
{
if (!i)
return;
if (isconst(d))
{
live.state[d].val += i;
return;
}
if (!i)
return;
if (isconst(d)) {
live.state[d].val += i;
return;
}
d = rmw(d, 4, 4);
d = rmw(d, 4, 4);
if(CHECK32(i))
{
raw_ADD_l_rri(d, d, i);
}
else
{
raw_LDR_l_ri(REG_WORK1, i);
raw_ADD_l_rr(d, REG_WORK1);
}
unlock2(d);
if(CHECK32(i)) {
raw_ADD_l_rri(d, d, i);
} else {
raw_LDR_l_ri(REG_WORK1, i);
raw_ADD_l_rr(d, REG_WORK1);
}
unlock2(d);
}
MENDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i))
MIDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i))
{
if (!i)
return;
if (isconst(d))
{
live.state[d].val += i;
return;
}
if (!i)
return;
if (isconst(d)) {
live.state[d].val += i;
return;
}
d = rmw(d, 4, 4);
raw_ADD_l_rri(d, d, i);
unlock2(d);
d = rmw(d, 4, 4);
raw_ADD_l_rri(d, d, i);
unlock2(d);
}
MENDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i))
MIDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i))
{
if (!i)
return;
if (isconst(d))
{
live.state[d].val -= i;
return;
}
if (!i)
return;
if (isconst(d)) {
live.state[d].val -= i;
return;
}
d = rmw(d, 4, 4);
raw_SUB_l_rri(d, d, i);
unlock2(d);
d = rmw(d, 4, 4);
raw_SUB_l_rri(d, d, i);
unlock2(d);
}
MENDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i))
@ -491,28 +457,26 @@ MENDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i))
// Other
STATIC_INLINE void flush_cpu_icache(void *start, void *stop)
{
register void *_beg __asm ("a1") = start;
register void *_end __asm ("a2") = stop;
register void *_flg __asm ("a3") = 0;
#ifdef __ARM_EABI__
register unsigned long _scno __asm ("r7") = 0xf0002;
__asm __volatile ("swi 0x0 @ sys_cacheflush"
: "=r" (_beg)
: "0" (_beg), "r" (_end), "r" (_flg), "r" (_scno));
#else
__asm __volatile ("swi 0x9f0002 @ sys_cacheflush"
: "=r" (_beg)
: "0" (_beg), "r" (_end), "r" (_flg));
#endif
register void *_beg __asm ("a1") = start;
register void *_end __asm ("a2") = stop;
register void *_flg __asm ("a3") = 0;
#ifdef __ARM_EABI__
register unsigned long _scno __asm ("r7") = 0xf0002;
__asm __volatile ("swi 0x0 @ sys_cacheflush"
: "=r" (_beg)
: "0" (_beg), "r" (_end), "r" (_flg), "r" (_scno));
#else
__asm __volatile ("swi 0x9f0002 @ sys_cacheflush"
: "=r" (_beg)
: "0" (_beg), "r" (_end), "r" (_flg));
#endif
}
STATIC_INLINE void write_jmp_target(uae_u32* jmpaddr, cpuop_func* a)
{
*(jmpaddr) = (uae_u32)a;
STATIC_INLINE void write_jmp_target(uae_u32* jmpaddr, cpuop_func* a) {
*(jmpaddr) = (uae_u32)a;
flush_cpu_icache((void *)jmpaddr, (void *)&jmpaddr[1]);
}
STATIC_INLINE void emit_jmp_target(uae_u32 a)
{
emit_long((uae_u32)a);
STATIC_INLINE void emit_jmp_target(uae_u32 a) {
emit_long((uae_u32)a);
}

5696
src/jit/compemu_midfunc_arm2.cpp
View file

File diff suppressed because it is too large Load diff

26
src/jit/compemu_prefs.cpp Normal file
View file

@ -0,0 +1,26 @@
/********************************************************************
* Preferences handling. This is just a convenient place to put it *
********************************************************************/
extern bool have_done_picasso;
bool check_prefs_changed_comp (bool checkonly)
{
bool changed = 0;
if (currprefs.fpu_strict != changed_prefs.fpu_strict ||
currprefs.cachesize != changed_prefs.cachesize)
changed = 1;
if (checkonly)
return changed;
currprefs.fpu_strict = changed_prefs.fpu_strict;
if (currprefs.cachesize != changed_prefs.cachesize) {
currprefs.cachesize = changed_prefs.cachesize;
alloc_cache();
changed = 1;
}
return changed;
}

883
src/jit/compemu_support.cpp
View file

File diff suppressed because it is too large Load diff

9
src/jit/compstbl.cpp
View file

@ -6,7 +6,6 @@
#include "newcpu.h"
#include "custom.h"
#include "comptbl.h"
#include "debug.h"
extern const struct comptbl op_smalltbl_0_comp_ff[] = {
{ op_0_0_comp_ff, 0x00000002, 0 }, /* OR */
{ op_10_0_comp_ff, 0x00000002, 16 }, /* OR */
@ -821,6 +820,7 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
{ op_4a39_0_comp_ff, 0x00000002, 19001 }, /* TST */
{ op_4a3a_0_comp_ff, 0x00000002, 19002 }, /* TST */
{ op_4a3b_0_comp_ff, 0x00000002, 19003 }, /* TST */
{ op_4a3c_0_comp_ff, 0x00000002, 19004 }, /* TST */
{ op_4a40_0_comp_ff, 0x00000000, 19008 }, /* TST */
{ op_4a48_0_comp_ff, 0x00000000, 19016 }, /* TST */
{ op_4a50_0_comp_ff, 0x00000000, 19024 }, /* TST */
@ -832,6 +832,7 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
{ op_4a79_0_comp_ff, 0x00000002, 19065 }, /* TST */
{ op_4a7a_0_comp_ff, 0x00000002, 19066 }, /* TST */
{ op_4a7b_0_comp_ff, 0x00000002, 19067 }, /* TST */
{ op_4a7c_0_comp_ff, 0x00000002, 19068 }, /* TST */
{ op_4a80_0_comp_ff, 0x00000000, 19072 }, /* TST */
{ op_4a88_0_comp_ff, 0x00000000, 19080 }, /* TST */
{ op_4a90_0_comp_ff, 0x00000000, 19088 }, /* TST */
@ -843,6 +844,7 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
{ op_4ab9_0_comp_ff, 0x00000002, 19129 }, /* TST */
{ op_4aba_0_comp_ff, 0x00000002, 19130 }, /* TST */
{ op_4abb_0_comp_ff, 0x00000002, 19131 }, /* TST */
{ op_4abc_0_comp_ff, 0x00000002, 19132 }, /* TST */
{ NULL, 0x00000000, 19136 }, /* TAS */
{ NULL, 0x00000000, 19152 }, /* TAS */
{ NULL, 0x00000000, 19160 }, /* TAS */
@ -2690,6 +2692,7 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
{ op_4a39_0_comp_nf, 0x00000002, 19001 }, /* TST */
{ op_4a3a_0_comp_nf, 0x00000002, 19002 }, /* TST */
{ op_4a3b_0_comp_nf, 0x00000002, 19003 }, /* TST */
{ op_4a3c_0_comp_nf, 0x00000002, 19004 }, /* TST */
{ op_4a40_0_comp_nf, 0x00000000, 19008 }, /* TST */
{ op_4a48_0_comp_nf, 0x00000000, 19016 }, /* TST */
{ op_4a50_0_comp_nf, 0x00000000, 19024 }, /* TST */
@ -2701,6 +2704,7 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
{ op_4a79_0_comp_nf, 0x00000002, 19065 }, /* TST */
{ op_4a7a_0_comp_nf, 0x00000002, 19066 }, /* TST */
{ op_4a7b_0_comp_nf, 0x00000002, 19067 }, /* TST */
{ op_4a7c_0_comp_nf, 0x00000002, 19068 }, /* TST */
{ op_4a80_0_comp_nf, 0x00000000, 19072 }, /* TST */
{ op_4a88_0_comp_nf, 0x00000000, 19080 }, /* TST */
{ op_4a90_0_comp_nf, 0x00000000, 19088 }, /* TST */
@ -2712,6 +2716,7 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
{ op_4ab9_0_comp_nf, 0x00000002, 19129 }, /* TST */
{ op_4aba_0_comp_nf, 0x00000002, 19130 }, /* TST */
{ op_4abb_0_comp_nf, 0x00000002, 19131 }, /* TST */
{ op_4abc_0_comp_nf, 0x00000002, 19132 }, /* TST */
{ NULL, 0x00000000, 19136 }, /* TAS */
{ NULL, 0x00000000, 19152 }, /* TAS */
{ NULL, 0x00000000, 19160 }, /* TAS */
@ -3745,4 +3750,4 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
{ op_f620_0_comp_nf, 0x00000002, 63008 }, /* MOVE16 */
{ NULL, 0x00000001, 63488 }, /* LPSTOP */
{ 0, 0,65536 }};
#endif
#endif

8
src/jit/comptbl.h
View file

@ -667,6 +667,7 @@ extern compop_func op_4a38_0_comp_ff;
extern compop_func op_4a39_0_comp_ff;
extern compop_func op_4a3a_0_comp_ff;
extern compop_func op_4a3b_0_comp_ff;
extern compop_func op_4a3c_0_comp_ff;
extern compop_func op_4a40_0_comp_ff;
extern compop_func op_4a48_0_comp_ff;
extern compop_func op_4a50_0_comp_ff;
@ -678,6 +679,7 @@ extern compop_func op_4a78_0_comp_ff;
extern compop_func op_4a79_0_comp_ff;
extern compop_func op_4a7a_0_comp_ff;
extern compop_func op_4a7b_0_comp_ff;
extern compop_func op_4a7c_0_comp_ff;
extern compop_func op_4a80_0_comp_ff;
extern compop_func op_4a88_0_comp_ff;
extern compop_func op_4a90_0_comp_ff;
@ -689,6 +691,7 @@ extern compop_func op_4ab8_0_comp_ff;
extern compop_func op_4ab9_0_comp_ff;
extern compop_func op_4aba_0_comp_ff;
extern compop_func op_4abb_0_comp_ff;
extern compop_func op_4abc_0_comp_ff;
extern compop_func op_4c00_0_comp_ff;
extern compop_func op_4c10_0_comp_ff;
extern compop_func op_4c18_0_comp_ff;
@ -2111,6 +2114,7 @@ extern compop_func op_4a38_0_comp_nf;
extern compop_func op_4a39_0_comp_nf;
extern compop_func op_4a3a_0_comp_nf;
extern compop_func op_4a3b_0_comp_nf;
extern compop_func op_4a3c_0_comp_nf;
extern compop_func op_4a40_0_comp_nf;
extern compop_func op_4a48_0_comp_nf;
extern compop_func op_4a50_0_comp_nf;
@ -2122,6 +2126,7 @@ extern compop_func op_4a78_0_comp_nf;
extern compop_func op_4a79_0_comp_nf;
extern compop_func op_4a7a_0_comp_nf;
extern compop_func op_4a7b_0_comp_nf;
extern compop_func op_4a7c_0_comp_nf;
extern compop_func op_4a80_0_comp_nf;
extern compop_func op_4a88_0_comp_nf;
extern compop_func op_4a90_0_comp_nf;
@ -2133,6 +2138,7 @@ extern compop_func op_4ab8_0_comp_nf;
extern compop_func op_4ab9_0_comp_nf;
extern compop_func op_4aba_0_comp_nf;
extern compop_func op_4abb_0_comp_nf;
extern compop_func op_4abc_0_comp_nf;
extern compop_func op_4c00_0_comp_nf;
extern compop_func op_4c10_0_comp_nf;
extern compop_func op_4c18_0_comp_nf;
@ -2891,4 +2897,4 @@ extern compop_func op_f600_0_comp_nf;
extern compop_func op_f608_0_comp_nf;
extern compop_func op_f610_0_comp_nf;
extern compop_func op_f618_0_comp_nf;
extern compop_func op_f620_0_comp_nf;
extern compop_func op_f620_0_comp_nf;

35
src/jit/gencomp_arm.cpp
View file

@ -7,6 +7,9 @@
* Adaptation for ARAnyM/ARM, copyright 2001-2015
* Milan Jurik, Jens Heitmann
*
* Adaptation for Basilisk II and improvements, copyright 2000-2005
* Gwenole Beauchesne
*
* Basilisk II (C) 1997-2005 Christian Bauer
*
* This program is free software; you can redistribute it and/or modify
@ -125,7 +128,6 @@
#define DISABLE_I_DIVU // DIVU works, but we have to think about exceptions. No big performance enhancement.
#define RETURN "return 0;"
#define BOOL_TYPE "int"
@ -2069,6 +2071,7 @@ gen_opcode(unsigned long int opcode) {
case i_SBCD:
failure;
/* I don't think so! */
break;
case i_ADD:
@ -2094,6 +2097,7 @@ gen_opcode(unsigned long int opcode) {
case i_ABCD:
failure;
/* No BCD maths for me.... */
break;
case i_NEG:
@ -2112,6 +2116,7 @@ gen_opcode(unsigned long int opcode) {
case i_NBCD:
failure;
/* Nope! */
break;
case i_CLR:
@ -2357,8 +2362,7 @@ gen_opcode(unsigned long int opcode) {
isjump;
genamode(curi->smode, "srcreg", curi->size, "src", 0, 0);
start_brace();
comprintf(
"\tuae_u32 retadd=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
comprintf("\tuae_u32 retadd=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
comprintf("\tint ret=scratchie++;\n"
"\tmov_l_ri(ret,retadd);\n"
"\tsub_l_ri(15,4);\n"
@ -2387,12 +2391,10 @@ gen_opcode(unsigned long int opcode) {
#ifdef DISABLE_I_BSR
failure;
#endif
is_const_jump
;
is_const_jump;
genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
start_brace();
comprintf(
"\tuae_u32 retadd=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
comprintf("\tuae_u32 retadd=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
comprintf("\tint ret=scratchie++;\n"
"\tmov_l_ri(ret,retadd);\n"
"\tsub_l_ri(15,4);\n"
@ -2427,8 +2429,7 @@ gen_opcode(unsigned long int opcode) {
comprintf("\tmake_flags_live();\n"); /* Load the flags */
isjump;
} else {
is_const_jump
;
is_const_jump;
}
switch (curi->cc) {
@ -2857,7 +2858,6 @@ generate_includes(FILE * f)
fprintf(f, "#include \"newcpu.h\"\n");
fprintf (f, "#include \"custom.h\"\n");
fprintf(f, "#include \"comptbl.h\"\n");
fprintf(f, "#include \"debug.h\"\n");
}
static int postfix;
@ -3124,16 +3124,11 @@ generate_one_opcode(int rp, int noflags)
fprintf(stblfile, "{ NULL, 0x%08x, %ld }, /* %s */\n", flags, opcode, name);
com_discard();
} else {
const char *tbl = noflags ? "nf" : "ff";
printf ("/* %s */\n", outopcode (opcode));
if (noflags) {
fprintf(stblfile, "{ op_%lx_%d_comp_nf, 0x%08x, %ld }, /* %s */\n", opcode, postfix, flags, opcode, name);
fprintf(headerfile, "extern compop_func op_%lx_%d_comp_nf;\n", opcode, postfix);
printf("uae_u32 REGPARAM2 op_%lx_%d_comp_nf(uae_u32 opcode)\n{\n", opcode, postfix);
} else {
fprintf(stblfile, "{ op_%lx_%d_comp_ff, 0x%08x, %ld }, /* %s */\n", opcode, postfix, flags, opcode, name);
fprintf(headerfile, "extern compop_func op_%lx_%d_comp_ff;\n", opcode, postfix);
printf("uae_u32 REGPARAM2 op_%lx_%d_comp_ff(uae_u32 opcode)\n{\n", opcode, postfix);
}
fprintf(stblfile, "{ op_%lx_%d_comp_%s, 0x%08x, %ld }, /* %s */\n", opcode, postfix, tbl, flags, opcode, name);
fprintf(headerfile, "extern compop_func op_%lx_%d_comp_%s;\n", opcode, postfix, tbl);
printf("uae_u32 REGPARAM2 op_%lx_%d_comp_%s(uae_u32 opcode)\n{\n", opcode, postfix, tbl);
com_flush();
}
}
@ -3255,4 +3250,4 @@ int main(int argc, char *argv[])
fclose(stblfile);
fclose(headerfile);
return 0;
}
}