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JIT: implemented BFINS

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Merged from TomB's repo
This commit is contained in:
Dimitris Panokostas 2020-02-22 10:06:52 +01:00
parent d143b40692
commit b604306194
15 changed files with 2844 additions and 292 deletions
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2
src/include/newcpu.h
View file

@ -133,7 +133,7 @@ struct regstruct
#ifdef JIT
/* store scratch regs also in this struct to avoid load of mem pointer */
uae_u32 scratchregs[VREGS - 16];
uae_u32 scratchregs[VREGS - S1];
fpu_register scratchfregs[VFREGS - 8];
uae_u32 jit_exception;

18
src/jit/codegen_arm.cpp.in
View file

@ -179,18 +179,6 @@ STATIC_INLINE void raw_pop_preserved_regs(void) {
POP_REGS(PRESERVE_MASK);
}
STATIC_INLINE void raw_flags_evicted(int r)
{
live.state[FLAGTMP].status = INMEM;
live.state[FLAGTMP].realreg = -1;
/* We just "evicted" FLAGTMP. */
if (live.nat[r].nholds != 1) {
/* Huh? */
abort();
}
live.nat[r].nholds = 0;
}
STATIC_INLINE void raw_flags_to_reg(int r)
{
uintptr idx = (uintptr) &(regs.ccrflags.nzcv) - (uintptr) &regs;
@ -201,7 +189,11 @@ STATIC_INLINE void raw_flags_to_reg(int r)
flags_carry_inverted = false;
}
STR_rRI(r, R_REGSTRUCT, idx);
raw_flags_evicted(r);
live.state[FLAGTMP].status = INMEM;
live.state[FLAGTMP].realreg = -1;
/* We just "evicted" FLAGTMP. */
live.nat[r].nholds = 0;
}
STATIC_INLINE void raw_reg_to_flags(int r)

4
src/jit/codegen_arm.h
View file

@ -1474,6 +1474,9 @@ enum {
#define CC_VMSR_r(cc,Rt) _W(((cc) << 28) | (0xe << 24) | (0xe << 20) | (0x1 << 16) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4))
#define VMSR_r(Rt) CC_VMSR_r(NATIVE_CC_AL,Rt)
#define VBIT64_ddd(Dd,Dn,Dm) _W(((0xf) << 28) | (0x3 << 24) | (0x2 << 20) | (0x1 << 8) | (0x1 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
#define VBIF64_ddd(Dd,Dn,Dm) _W(((0xf) << 28) | (0x3 << 24) | (0x3 << 20) | (0x1 << 8) | (0x1 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
// Immediate values for VBIC, VMOV (I32), VMVN (I32) and VORR
#define FIMMVAL(imm) ((((imm) & 0x80) << 17) | (((imm) & 0x70) << 12) | (((imm) & 0x0f) << 0))
#define FIMM32(imm) (((imm) & 0xffffff00) == 0 ? (FIMMVAL((imm) >> 0) | (0x0 << 8)) : \
@ -1499,6 +1502,7 @@ enum {
#define VSHL64_ddi(Dd,Dm,imm) _W((0xf << 28) | (0x2 << 24) | (0x8 << 20) | (0x5 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(imm))
#define VSHR64_ddi(Dd,Dm,imm) _W((0xf << 28) | (0x3 << 24) | (0x8 << 20) | (0x0 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(64-(imm)))
#define VSLI64_ddi(Dd,Dm,i) _W((0xf << 28) | (0x3 << 24) | (0x8 << 20) | (0x5 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(i))
#define VSHL64_ddd(Dd,Dm,Dn) _W((0xf << 28) | (0x3 << 24) | (0x3 << 20) | (0x4 << 8) | (0x0 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
#define VORR_ddd(Dd,Dn,Dm) _W((0xf << 28) | (0x2 << 24) | (0x2 << 20) | (0x1 << 8) | (0x1 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))

18
src/jit/codegen_armA64.cpp.in
View file

@ -174,18 +174,6 @@ STATIC_INLINE void raw_pop_preserved_regs(void) {
LDP_xxXpost(27, 28, RSP_INDEX, 16);
}
STATIC_INLINE void raw_flags_evicted(int r)
{
live.state[FLAGTMP].status = INMEM;
live.state[FLAGTMP].realreg = -1;
/* We just "evicted" FLAGTMP. */
if (live.nat[r].nholds != 1) {
/* Huh? */
abort();
}
live.nat[r].nholds = 0;
}
STATIC_INLINE void raw_flags_to_reg(int r)
{
uintptr idx = (uintptr) &(regs.ccrflags.nzcv) - (uintptr) &regs;
@ -196,7 +184,11 @@ STATIC_INLINE void raw_flags_to_reg(int r)
flags_carry_inverted = false;
}
STR_wXi(r, R_REGSTRUCT, idx);
raw_flags_evicted(r);
live.state[FLAGTMP].status = INMEM;
live.state[FLAGTMP].realreg = -1;
/* We just "evicted" FLAGTMP. */
live.nat[r].nholds = 0;
}
STATIC_INLINE void raw_reg_to_flags(int r)

6
src/jit/codegen_armA64.h
View file

@ -143,6 +143,8 @@
#define STRH_wXi(Wt,Xn,i) _W((0b0111100100 << 22) | ((((i)/2) &0xfff) << 10) | ((Xn) << 5) | (Wt))
#define STRH_wXx(Wt,Xn,Xm) _W((0b01111000001 << 21) | ((Xm) << 16) | (0b011 << 13) | (0 << 12) | (0b10 << 10) | ((Xn) << 5) | (Wt))
#define STUR_wXi(Wt,Xn,i) _W((0b10111000000 << 21) | ((i & 0x1ff) << 12) | ((Xn) << 5) | (Wt))
#define STURH_wXi(Wt,Xn,i) _W((0b01111000000 << 21) | ((i & 0x1ff) << 12) | ((Xn) << 5) | (Wt))
/*----------------------------------------
* move immediate/register
@ -275,12 +277,16 @@
/* AND */
#define AND_www(Wd,Wn,Wm) _W((0b00001010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
#define AND_xxx(Xd,Xn,Xm) _W((0b10001010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
#define AND_xx1f(Xd,Xn) _W((0b100100100 << 23) | immEncode(1,0b000000,0b000100) | ((Xn) << 5) | (Xd))
#define AND_ww3f(Wd,Wn) _W((0b000100100 << 23) | immEncode(0,0b000000,0b000101) | ((Wn) << 5) | (Wd))
#define AND_ww1f(Wd,Wn) _W((0b000100100 << 23) | immEncode(0,0b000000,0b000100) | ((Wn) << 5) | (Wd))
#define ANDS_www(Wd,Wn,Wm) _W((0b01101010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
#define ANDS_xxx(Xd,Xn,Xm) _W((0b11101010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
#define ANDS_xx7fff(Xd,Xn) _W((0b111100100 << 23) | immEncode(1,0b000000,0b001110) | ((Xn) << 5) | (Xd))
#define ANDS_xx1f(Xd,Xn) _W((0b111100100 << 23) | immEncode(1,0b000000,0b000100) | ((Xn) << 5) | (Xd))
#define ANDS_ww7f(Wd,Wn) _W((0b011100100 << 23) | immEncode(0,0b000000,0b000110) | ((Wn) << 5) | (Wd))
#define ANDS_ww3f(Wd,Wn) _W((0b011100100 << 23) | immEncode(0,0b000000,0b000101) | ((Wn) << 5) | (Wd))
#define ANDS_ww1f(Wd,Wn) _W((0b011100100 << 23) | immEncode(0,0b000000,0b000100) | ((Wn) << 5) | (Wd))
/* EOR */
#define EOR_www(Wd,Wn,Wm) _W((0b01001010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))

606
src/jit/compemu.cpp
View file

@ -28751,6 +28751,312 @@ uae_u32 REGPARAM2 op_e7f9_0_comp_ff(uae_u32 opcode)
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* BFINS.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_efc0_0_comp_ff(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 dstreg = opcode & 7;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dst=dstreg;
if ((extra & 0x0820) == 0x0000) {
jff_BFINS_ii(dst, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0800) {
jff_BFINS_di(dst, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jff_BFINS_id(dst, srcreg, offs, width);
} else {
jff_BFINS_dd(dst, srcreg, offs, width);
}
live_flags();
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(An) */
uae_u32 REGPARAM2 op_efd0_0_comp_ff(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 dstreg = opcode & 7;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta=scratchie++;
mov_l_rr(dsta,dstreg+8);
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jff_BFINS_ii(dst, srcreg, offs, width);
} else {
jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jff_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jff_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
live_flags();
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_efe8_0_comp_ff(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 dstreg = opcode & 7;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta=scratchie++;
lea_l_brr(dsta,8+dstreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jff_BFINS_ii(dst, srcreg, offs, width);
} else {
jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jff_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jff_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
live_flags();
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_eff0_0_comp_ff(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 dstreg = opcode & 7;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta=scratchie++;
calc_disp_ea_020(dstreg+8,comp_get_iword((m68k_pc_offset+=2)-2),dsta);
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jff_BFINS_ii(dst, srcreg, offs, width);
} else {
jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jff_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jff_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
live_flags();
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_eff8_0_comp_ff(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta = scratchie++;
mov_l_ri(dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jff_BFINS_ii(dst, srcreg, offs, width);
} else {
jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jff_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jff_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
live_flags();
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_eff9_0_comp_ff(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta = scratchie++;
mov_l_ri(dsta,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jff_BFINS_ii(dst, srcreg, offs, width);
} else {
jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jff_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jff_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
live_flags();
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* FPP.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_f200_0_comp_ff(uae_u32 opcode)
{
@ -56065,6 +56371,306 @@ uae_u32 REGPARAM2 op_e7f9_0_comp_nf(uae_u32 opcode)
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
}
/* BFINS.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_efc0_0_comp_nf(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 dstreg = opcode & 7;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dst=dstreg;
if ((extra & 0x0820) == 0x0000) {
jnf_BFINS_ii(dst, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0800) {
jnf_BFINS_di(dst, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jnf_BFINS_id(dst, srcreg, offs, width);
} else {
jnf_BFINS_dd(dst, srcreg, offs, width);
}
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(An) */
uae_u32 REGPARAM2 op_efd0_0_comp_nf(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 dstreg = opcode & 7;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta=scratchie++;
mov_l_rr(dsta,dstreg+8);
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jnf_BFINS_ii(dst, srcreg, offs, width);
} else {
jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_efe8_0_comp_nf(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 dstreg = opcode & 7;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta=scratchie++;
lea_l_brr(dsta,8+dstreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jnf_BFINS_ii(dst, srcreg, offs, width);
} else {
jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_eff0_0_comp_nf(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 dstreg = opcode & 7;
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta=scratchie++;
calc_disp_ea_020(dstreg+8,comp_get_iword((m68k_pc_offset+=2)-2),dsta);
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jnf_BFINS_ii(dst, srcreg, offs, width);
} else {
jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_eff8_0_comp_nf(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta = scratchie++;
mov_l_ri(dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jnf_BFINS_ii(dst, srcreg, offs, width);
} else {
jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* BFINS.L #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_eff9_0_comp_nf(uae_u32 opcode)
{
#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
FAIL(1);
return 0;
#else
uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
m68k_pc_offset+=2;
uae_u8 scratchie=S1;
dont_care_flags();
uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
int srcreg = (extra >> 12) & 7;
int offs, width;
if ((extra & 0x0800) == 0x0000)
offs = (extra >> 6) & 0x1f;
else
offs = (extra >> 6) & 0x07;
if ((extra & 0x0020) == 0x0000)
width = ((extra - 1) & 0x1f) + 1;
else
width = (extra & 0x07);
int dsta = scratchie++;
mov_l_ri(dsta,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
if ((extra & 0x0800) == 0x0800) {
arm_ADD_ldiv8(dsta,offs);
}
int dst=scratchie++;
readlong(dsta,dst);
int dsta2=scratchie++;
lea_l_brr(dsta2, dsta, 4);
int dst2=scratchie++;
readlong(dsta2,dst2);
if ((extra & 0x0820) == 0x0000) {
if(32 - offs - width >= 0) {
jnf_BFINS_ii(dst, srcreg, offs, width);
} else {
jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
}
} else if ((extra & 0x0820) == 0x0800) {
jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
} else if ((extra & 0x0820) == 0x0020) {
jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
} else {
jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
}
writelong(dsta2,dst2);
writelong(dsta,dst);
if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
return 0;
#endif
}
/* FPP.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_f200_0_comp_nf(uae_u32 opcode)
{

16
src/jit/compemu_midfunc_arm.cpp.in
View file

@ -484,6 +484,22 @@ MIDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
}
MENDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
MIDFUNC(2,arm_ADD_ldiv8,(RW4 d, RR4 s))
{
if (isconst(s)) {
COMPCALL(arm_ADD_l_ri)(d,(live.state[s].val & ~0x1f) >> 3);
return;
}
s = readreg(s);
d = rmw(d);
ASR_rri(REG_WORK1, s, 5);
ADD_rrrLSLi(d, d, REG_WORK1, 2);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,arm_ADD_ldiv8,(RW4 d, RR4 s))
MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IM32 i))
{
if (!i)

1
src/jit/compemu_midfunc_arm.h
View file

@ -33,6 +33,7 @@
// Arm optimized midfunc
DECLARE_MIDFUNC(arm_ADD_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(arm_ADD_ldiv8(RW4 d, RR4 s));
DECLARE_MIDFUNC(arm_ADD_l_ri(RW4 d, IM32 i));
DECLARE_MIDFUNC(arm_ADD_l_ri8(RW4 d, IM8 i));
DECLARE_MIDFUNC(arm_SUB_l_ri8(RW4 d, IM8 i));

1071
src/jit/compemu_midfunc_arm2.cpp.in
View file

File diff suppressed because it is too large Load diff

51
src/jit/compemu_midfunc_arm2.h
View file

@ -52,6 +52,8 @@ DECLARE_MIDFUNC(jff_ADD_l(RW4 d, RR4 s));
// ADDA
DECLARE_MIDFUNC(jnf_ADDA_w(RW4 d, RR2 s));
DECLARE_MIDFUNC(jnf_ADDA_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ADDA_w_imm(RW4 d, IM16 v));
DECLARE_MIDFUNC(jnf_ADDA_l_imm(RW4 d, IM32 v));
// ADDX
DECLARE_MIDFUNC(jnf_ADDX_b(RW1 d, RR1 s));
@ -67,11 +69,13 @@ DECLARE_MIDFUNC(jff_ANDSR(IM32 s, IM8 x));
// AND
DECLARE_MIDFUNC(jnf_AND_b_imm(RW1 d, IM8 v));
DECLARE_MIDFUNC(jnf_AND_w_imm(RW2 d, IM16 v));
DECLARE_MIDFUNC(jnf_AND_l_imm(RW4 d, IM32 v));
DECLARE_MIDFUNC(jnf_AND_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_AND_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_AND_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_AND_b_imm(RW1 d, IM8 v));
DECLARE_MIDFUNC(jff_AND_w_imm(RW2 d, IM16 v));
DECLARE_MIDFUNC(jff_AND_l_imm(RW4 d, IM32 v));
DECLARE_MIDFUNC(jff_AND_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_AND_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_AND_l(RW4 d, RR4 s));
@ -126,6 +130,24 @@ DECLARE_MIDFUNC(jff_BCLR_l_imm(RW4 d, IM8 s));
DECLARE_MIDFUNC(jff_BCLR_b(RW1 d, RR4 s));
DECLARE_MIDFUNC(jff_BCLR_l(RW4 d, RR4 s));
// BFINS
DECLARE_MIDFUNC(jnf_BFINS_ii(RW4 d, RR4 s, IM8 offs, IM8 width));
DECLARE_MIDFUNC(jff_BFINS_ii(RW4 d, RR4 s, IM8 offs, IM8 width));
DECLARE_MIDFUNC(jnf_BFINS2_ii(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width));
DECLARE_MIDFUNC(jff_BFINS2_ii(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width));
DECLARE_MIDFUNC(jnf_BFINS_di(RW4 d, RR4 s, RR4 offs, IM8 width));
DECLARE_MIDFUNC(jff_BFINS_di(RW4 d, RR4 s, RR4 offs, IM8 width));
DECLARE_MIDFUNC(jnf_BFINS2_di(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width));
DECLARE_MIDFUNC(jff_BFINS2_di(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width));
DECLARE_MIDFUNC(jnf_BFINS_id(RW4 d, RR4 s, IM8 offs, RR4 width));
DECLARE_MIDFUNC(jff_BFINS_id(RW4 d, RR4 s, IM8 offs, RR4 width));
DECLARE_MIDFUNC(jnf_BFINS2_id(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width));
DECLARE_MIDFUNC(jff_BFINS2_id(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width));
DECLARE_MIDFUNC(jnf_BFINS_dd(RW4 d, RR4 s, RR4 offs, RR4 width));
DECLARE_MIDFUNC(jff_BFINS_dd(RW4 d, RR4 s, RR4 offs, RR4 width));
DECLARE_MIDFUNC(jnf_BFINS2_dd(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width));
DECLARE_MIDFUNC(jff_BFINS2_dd(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width));
// BSET
DECLARE_MIDFUNC(jnf_BSET_b_imm(RW1 d, IM8 s));
DECLARE_MIDFUNC(jnf_BSET_l_imm(RW4 d, IM8 s));
@ -151,11 +173,16 @@ DECLARE_MIDFUNC (jff_CLR_w(W2 d));
DECLARE_MIDFUNC (jff_CLR_l(W4 d));
// CMP
DECLARE_MIDFUNC(jff_CMP_b_imm(RR1 d, IM8 v));
DECLARE_MIDFUNC(jff_CMP_w_imm(RR2 d, IM16 v));
DECLARE_MIDFUNC(jff_CMP_l_imm(RR4 d, IM32 v));
DECLARE_MIDFUNC(jff_CMP_b(RR1 d, RR1 s));
DECLARE_MIDFUNC(jff_CMP_w(RR2 d, RR2 s));
DECLARE_MIDFUNC(jff_CMP_l(RR4 d, RR4 s));
// CMPA
DECLARE_MIDFUNC(jff_CMPA_w_imm(RR2 d, IM16 v));
DECLARE_MIDFUNC(jff_CMPA_l_imm(RR4 d, IM32 v));
DECLARE_MIDFUNC(jff_CMPA_w(RR2 d, RR2 s));
DECLARE_MIDFUNC(jff_CMPA_l(RR4 d, RR4 s));
@ -179,11 +206,13 @@ DECLARE_MIDFUNC(jff_DIVLS32(RW4 d, RR4 s1, W4 rem));
// EOR
DECLARE_MIDFUNC(jnf_EOR_b_imm(RW1 d, IM8 v));
DECLARE_MIDFUNC(jnf_EOR_w_imm(RW2 d, IM16 v));
DECLARE_MIDFUNC(jnf_EOR_l_imm(RW4 d, IM32 v));
DECLARE_MIDFUNC(jnf_EOR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_EOR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_EOR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_EOR_b_imm(RW1 d, IM8 v));
DECLARE_MIDFUNC(jff_EOR_w_imm(RW2 d, IM16 v));
DECLARE_MIDFUNC(jff_EOR_l_imm(RW4 d, IM32 v));
DECLARE_MIDFUNC(jff_EOR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_EOR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_EOR_l(RW4 d, RR4 s));
@ -260,6 +289,7 @@ DECLARE_MIDFUNC(jnf_MVMLE_l(RR4 d, RR4 s, IM8 offset));
DECLARE_MIDFUNC(jnf_MOVE16(RR4 d, RR4 s));
// MOVEA
DECLARE_MIDFUNC(jnf_MOVEA_w_imm(W4 d, IM16 v));
DECLARE_MIDFUNC(jnf_MOVEA_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jnf_MOVEA_l(W4 d, RR4 s));
@ -306,11 +336,13 @@ DECLARE_MIDFUNC(jff_NOT_l(RW4 d));
// OR
DECLARE_MIDFUNC(jnf_OR_b_imm(RW1 d, IM8 v));
DECLARE_MIDFUNC(jnf_OR_w_imm(RW2 d, IM16 v));
DECLARE_MIDFUNC(jnf_OR_l_imm(RW4 d, IM32 v));
DECLARE_MIDFUNC(jnf_OR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_OR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_OR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_OR_b_imm(RW1 d, IM8 v));
DECLARE_MIDFUNC(jff_OR_w_imm(RW2 d, IM16 v));
DECLARE_MIDFUNC(jff_OR_l_imm(RW4 d, IM32 v));
DECLARE_MIDFUNC(jff_OR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_OR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_OR_l(RW4 d, RR4 s));
@ -319,9 +351,15 @@ DECLARE_MIDFUNC(jff_OR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_ORSR(IM32 s, IM8 x));
// ROL
DECLARE_MIDFUNC(jnf_ROL_b_imm(RW1 d, IM8 i));
DECLARE_MIDFUNC(jnf_ROL_w_imm(RW2 d, IM16 i));
DECLARE_MIDFUNC(jnf_ROL_l_imm(RW4 d, IM32 i));
DECLARE_MIDFUNC(jnf_ROL_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_l(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_ROL_b_imm(RW1 d, IM8 i));
DECLARE_MIDFUNC(jff_ROL_w_imm(RW2 d, IM16 i));
DECLARE_MIDFUNC(jff_ROL_l_imm(RW4 d, IM32 i));
DECLARE_MIDFUNC(jff_ROL_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ROL_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ROL_l(RW4 d, RR4 i));
@ -343,9 +381,15 @@ DECLARE_MIDFUNC(jff_ROXL_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_l(RW4 d, RR4 i));
// ROR
DECLARE_MIDFUNC(jnf_ROR_b_imm(RW1 d, IM8 i));
DECLARE_MIDFUNC(jnf_ROR_w_imm(RW2 d, IM16 i));
DECLARE_MIDFUNC(jnf_ROR_l_imm(RW4 d, IM32 i));
DECLARE_MIDFUNC(jnf_ROR_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROR_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROR_l(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_ROR_b_imm(RW1 d, IM8 i));
DECLARE_MIDFUNC(jff_ROR_w_imm(RW2 d, IM16 i));
DECLARE_MIDFUNC(jff_ROR_l_imm(RW4 d, IM32 i));
DECLARE_MIDFUNC(jff_ROR_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ROR_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ROR_l(RW4 d, RR4 i));
@ -364,11 +408,13 @@ DECLARE_MIDFUNC(jnf_SCC(W1 d, IM8 cc));
// SUB
DECLARE_MIDFUNC(jnf_SUB_b_imm(RW1 d, IM8 v));
DECLARE_MIDFUNC(jnf_SUB_w_imm(RW2 d, IM16 v));
DECLARE_MIDFUNC(jnf_SUB_l_imm(RW4 d, IM32 v));
DECLARE_MIDFUNC(jnf_SUB_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jnf_SUB_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jnf_SUB_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_SUB_b_imm(RW1 d, IM8 v));
DECLARE_MIDFUNC(jff_SUB_w_imm(RW2 d, IM16 v));
DECLARE_MIDFUNC(jff_SUB_l_imm(RW4 d, IM32 v));
DECLARE_MIDFUNC(jff_SUB_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(jff_SUB_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(jff_SUB_l(RW4 d, RR4 s));
@ -376,6 +422,8 @@ DECLARE_MIDFUNC(jff_SUB_l(RW4 d, RR4 s));
// SUBA
DECLARE_MIDFUNC(jnf_SUBA_w(RW4 d, RR2 s));
DECLARE_MIDFUNC(jnf_SUBA_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jnf_SUBA_w_imm(RW4 d, IM16 v));
DECLARE_MIDFUNC(jnf_SUBA_l_imm(RW4 d, IM32 v));
// SUBX
DECLARE_MIDFUNC(jnf_SUBX_b(RW1 d, RR1 s));
@ -390,6 +438,9 @@ DECLARE_MIDFUNC (jnf_SWAP(RW4 d));
DECLARE_MIDFUNC (jff_SWAP(RW4 d));
// TST
DECLARE_MIDFUNC (jff_TST_b_imm(IM8 v));
DECLARE_MIDFUNC (jff_TST_w_imm(IM16 v));
DECLARE_MIDFUNC (jff_TST_l_imm(IM32 v));
DECLARE_MIDFUNC (jff_TST_b(RR1 s));
DECLARE_MIDFUNC (jff_TST_w(RR2 s));
DECLARE_MIDFUNC (jff_TST_l(RR4 s));

16
src/jit/compemu_midfunc_armA64.cpp.in
View file

@ -491,6 +491,22 @@ MIDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
}
MENDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
MIDFUNC(2,arm_ADD_ldiv8,(RW4 d, RR4 s))
{
if (isconst(s)) {
COMPCALL(arm_ADD_l_ri)(d,(live.state[s].val & ~0x1f) >> 3);
return;
}
s = readreg(s);
d = rmw(d);
ASR_wwi(REG_WORK1, s, 5);
ADD_wwwLSLi(d, d, REG_WORK1, 2);
unlock2(d);
unlock2(s);
}
MENDFUNC(2,arm_ADD_ldiv8,(RW4 d, RR4 s))
MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IM32 i))
{
if (!i)

1105
src/jit/compemu_midfunc_armA64_2.cpp.in
View file

File diff suppressed because it is too large Load diff

16
src/jit/compemu_support.cpp
View file

@ -49,6 +49,12 @@
#endif
//#define PROFILE_UNTRANSLATED_INSNS 1
#if defined(CPU_AARCH64)
#define PRINT_PTR "%016llx"
#else
#define PRINT_PTR "%08x"
#endif
#define jit_log(format, ...) \
write_log("JIT: " format "\n", ##__VA_ARGS__);
@ -1271,8 +1277,8 @@ static void init_comp(void)
if (i < 16) { /* First 16 registers map to 68k registers */
live.state[i].mem = &regs.regs[i];
set_status(i, INMEM);
} else {
live.state[i].mem = &regs.scratchregs[i - 16];
} else if(i >= S1) {
live.state[i].mem = &regs.scratchregs[i - S1];
}
}
live.state[PC_P].mem = (uae_u32*)&(regs.pc_p);
@ -1327,7 +1333,7 @@ static void init_comp(void)
}
/* Only do this if you really mean it! The next call should be to init!*/
void flush(int save_regs)
static void flush(int save_regs)
{
int i;
@ -2302,7 +2308,7 @@ void compile_block(cpu_history* pc_hist, int blocklen, int totcycles)
needed_flags = (liveflags[i + 1] & prop[opcode].set_flags);
special_mem = pc_hist[i].specmem;
#ifdef JIT_DEBUG
write_log(" location=0x%016llx, opcode=0x%04x, target=0x%016llx, need_flags=%d\n", pc_hist[i].location, opcode, get_target(), needed_flags);
write_log(" location=0x" PRINT_PTR ", opcode=0x%04x, target=0x" PRINT_PTR ", need_flags=%d\n", pc_hist[i].location, opcode, get_target(), needed_flags);
#endif
if (!needed_flags) {
cputbl = cpufunctbl;
@ -2368,7 +2374,7 @@ void compile_block(cpu_history* pc_hist, int blocklen, int totcycles)
bigstate tmp;
blockinfo* tbi;
#ifdef JIT_DEBUG
write_log(" branch detected: t1=0x%016llx, t2=0x%016llx, cc=%d\n", t1, t2, cc);
write_log(" branch detected: t1=0x%016llx, t2=0x" PRINT_PTR ", cc=%d\n", t1, t2, cc);
#endif
if (taken_pc_p < next_pc_p) {

24
src/jit/compstbl.cpp
View file

@ -1788,12 +1788,12 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
{ NULL, 0x00000000, 61168 }, /* BFSET */
{ NULL, 0x00000000, 61176 }, /* BFSET */
{ NULL, 0x00000000, 61177 }, /* BFSET */
{ NULL, 0x00000000, 61376 }, /* BFINS */
{ NULL, 0x00000000, 61392 }, /* BFINS */
{ NULL, 0x00000000, 61416 }, /* BFINS */
{ NULL, 0x00000000, 61424 }, /* BFINS */
{ NULL, 0x00000000, 61432 }, /* BFINS */
{ NULL, 0x00000000, 61433 }, /* BFINS */
{ op_efc0_0_comp_ff, 0x00000002, 61376 }, /* BFINS */
{ op_efd0_0_comp_ff, 0x00000002, 61392 }, /* BFINS */
{ op_efe8_0_comp_ff, 0x00000002, 61416 }, /* BFINS */
{ op_eff0_0_comp_ff, 0x00000002, 61424 }, /* BFINS */
{ op_eff8_0_comp_ff, 0x00000002, 61432 }, /* BFINS */
{ op_eff9_0_comp_ff, 0x00000002, 61433 }, /* BFINS */
{ NULL, 0x00000001, 61440 }, /* MMUOP030 */
{ NULL, 0x00000001, 61448 }, /* MMUOP030 */
{ NULL, 0x00000001, 61456 }, /* MMUOP030 */
@ -3660,12 +3660,12 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
{ NULL, 0x00000000, 61168 }, /* BFSET */
{ NULL, 0x00000000, 61176 }, /* BFSET */
{ NULL, 0x00000000, 61177 }, /* BFSET */
{ NULL, 0x00000000, 61376 }, /* BFINS */
{ NULL, 0x00000000, 61392 }, /* BFINS */
{ NULL, 0x00000000, 61416 }, /* BFINS */
{ NULL, 0x00000000, 61424 }, /* BFINS */
{ NULL, 0x00000000, 61432 }, /* BFINS */
{ NULL, 0x00000000, 61433 }, /* BFINS */
{ op_efc0_0_comp_nf, 0x00000002, 61376 }, /* BFINS */
{ op_efd0_0_comp_nf, 0x00000002, 61392 }, /* BFINS */
{ op_efe8_0_comp_nf, 0x00000002, 61416 }, /* BFINS */
{ op_eff0_0_comp_nf, 0x00000002, 61424 }, /* BFINS */
{ op_eff8_0_comp_nf, 0x00000002, 61432 }, /* BFINS */
{ op_eff9_0_comp_nf, 0x00000002, 61433 }, /* BFINS */
{ NULL, 0x00000001, 61440 }, /* MMUOP030 */
{ NULL, 0x00000001, 61448 }, /* MMUOP030 */
{ NULL, 0x00000001, 61456 }, /* MMUOP030 */

12
src/jit/comptbl.h
View file

@ -1493,6 +1493,12 @@ extern compop_func op_e7e8_0_comp_ff;
extern compop_func op_e7f0_0_comp_ff;
extern compop_func op_e7f8_0_comp_ff;
extern compop_func op_e7f9_0_comp_ff;
extern compop_func op_efc0_0_comp_ff;
extern compop_func op_efd0_0_comp_ff;
extern compop_func op_efe8_0_comp_ff;
extern compop_func op_eff0_0_comp_ff;
extern compop_func op_eff8_0_comp_ff;
extern compop_func op_eff9_0_comp_ff;
extern compop_func op_f200_0_comp_ff;
extern compop_func op_f208_0_comp_ff;
extern compop_func op_f210_0_comp_ff;
@ -3013,6 +3019,12 @@ extern compop_func op_e7e8_0_comp_nf;
extern compop_func op_e7f0_0_comp_nf;
extern compop_func op_e7f8_0_comp_nf;
extern compop_func op_e7f9_0_comp_nf;
extern compop_func op_efc0_0_comp_nf;
extern compop_func op_efd0_0_comp_nf;
extern compop_func op_efe8_0_comp_nf;
extern compop_func op_eff0_0_comp_nf;
extern compop_func op_eff8_0_comp_nf;
extern compop_func op_eff9_0_comp_nf;
extern compop_func op_f200_0_comp_nf;
extern compop_func op_f208_0_comp_nf;
extern compop_func op_f210_0_comp_nf;