Fixed JIT FPU bugs (Starstruck demo corruption, etc.)
This commit is contained in:
Dimitris Panokostas
parent
88316d7916
commit
b9dc57af87
14 changed files with 1735 additions and 121 deletions
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@ -1852,28 +1852,44 @@ MENDFUNC(2,jff_DBCC,(RR2 d, IMM cc))
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* C Always cleared.
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*
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*/
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// ToDo: How to handle exceptions (division by zero). Performance improvement isn't big, so this is on hold.
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MIDFUNC(3,jnf_DIVU,(W4 d, RR4 s1, RR4 s2))
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{
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s1 = readreg(s1, 4);
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s2 = readreg(s2, 4);
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d = writereg(d, 4);
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VMOV32_sr(0, s1); // move to s0
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VMOV32_sr(1, s2); // move to s1
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VCVTIto64_ds(2, 0); // convert s0 to d2 (int to float)
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VCVTIto64_ds(3, 1); // convert s1 to d3 (int to float)
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VDIV64_ddd(4, 2, 3); // d4 = d2 / d3
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VCVT64toI_sd(0, 4); // convert d4 to s0 (float to int)
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VMOV32_rs(REG_WORK1, 0); // move from s0
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UNSIGNED16_REG_2_REG(REG_WORK3, s2);
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TST_rr(REG_WORK3, REG_WORK3);
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BNE_i(6); // src is not 0
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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STR_rR(REG_WORK1, REG_WORK2);
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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MOV_ri(REG_WORK1, ARM_Z_FLAG | ARM_V_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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B_i(11); // end_of_op
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// src is not 0
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VMOVi_from_ARM_dr(SCRATCH_F64_1, s1, 0);
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VMOVi_from_ARM_dr(SCRATCH_F64_2, REG_WORK3, 0);
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VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
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VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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LSRS_rri(REG_WORK2, REG_WORK1, 16); // if result of this is not 0, DIVU overflows -> no result
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BNE_i(2);
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// Here we have to calc reminder
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MUL_rrr(REG_WORK2, REG_WORK1, s2);
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MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
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SUB_rrr(REG_WORK2, s1, REG_WORK2);
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PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
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// end_of_op
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unlock2(d);
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unlock2(s1);
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@ -1887,13 +1903,29 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
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s2 = readreg(s2, 4);
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d = writereg(d, 4);
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VMOV32_sr(0, s1); // move to s0
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VMOV32_sr(1, s2); // move to s1
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VCVTIto64_ds(2, 0); // convert s0 to d2 (int to float)
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VCVTIto64_ds(3, 1); // convert s1 to d3 (int to float)
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VDIV64_ddd(4, 2, 3); // d4 = d2 / d3
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VCVT64toI_sd(0, 4); // convert d4 to s0 (float to int)
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VMOV32_rs(REG_WORK1, 0); // move from s0
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UNSIGNED16_REG_2_REG(REG_WORK3, s2);
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TST_rr(REG_WORK3, REG_WORK3);
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BNE_i(6); // src is not 0
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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STR_rR(REG_WORK1, REG_WORK2);
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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MOV_ri(REG_WORK1, ARM_Z_FLAG | ARM_V_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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B_i(18); // end_of_op
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// src is not 0
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VMOVi_from_ARM_dr(SCRATCH_F64_1, s1, 0);
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VMOVi_from_ARM_dr(SCRATCH_F64_2, REG_WORK3, 0);
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VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
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VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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LSRS_rri(REG_WORK2, REG_WORK1, 16); // if result of this is not 0, DIVU overflows
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BEQ_i(2);
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@ -1908,9 +1940,10 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
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BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
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MSR_CPSRf_r(REG_WORK2);
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MUL_rrr(REG_WORK2, REG_WORK1, s2);
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MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
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SUB_rrr(REG_WORK2, s1, REG_WORK2);
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PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
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// end_of_op
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unlock2(d);
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unlock2(s1);
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@ -1918,6 +1951,138 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
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}
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MENDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
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/*
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* DIVS
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*
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* X Not affected.
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* N Set if the most significant bit of the result is set or overflow. Cleared otherwise.
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* Z Set if the result is zero. Cleared otherwise.
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* V Set if overflow. Cleared otherwise.
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* C Always cleared.
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*
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*/
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MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
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{
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s1 = readreg(s1, 4);
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s2 = readreg(s2, 4);
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d = writereg(d, 4);
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SIGNED16_REG_2_REG(REG_WORK3, s2);
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TST_rr(REG_WORK3, REG_WORK3);
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BNE_i(6); // src is not 0
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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STR_rR(REG_WORK1, REG_WORK2);
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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MOV_ri(REG_WORK1, ARM_Z_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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B_i(18); // end_of_op
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// src is not 0
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VMOVi_from_ARM_dr(SCRATCH_F64_1, s1, 0);
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VMOVi_from_ARM_dr(SCRATCH_F64_2, REG_WORK3, 0);
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VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
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VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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// check for overflow
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MVN_ri(REG_WORK2, 0);
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LSL_rri(REG_WORK2, REG_WORK2, 15); // REG_WORK2 is now 0xffff8000
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ANDS_rrr(REG_WORK3, REG_WORK1, REG_WORK2);
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BEQ_i(1); // positive result, no overflow
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CMP_rr(REG_WORK3, REG_WORK2);
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BNE_i(5); // overflow -> end_of_op
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// Here we have to calc reminder
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SIGNED16_REG_2_REG(REG_WORK3, s2);
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MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
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SUB_rrr(REG_WORK2, s1, REG_WORK2); // REG_WORK2 contains remainder
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EORS_rrr(REG_WORK3, REG_WORK2, s1); // If sign of remainder and first operand differs, change sign of remainder
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CC_RSB_rri(NATIVE_CC_MI, REG_WORK2, REG_WORK2, 0);
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PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
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// end_of_op
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unlock2(d);
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unlock2(s1);
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unlock2(s2);
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}
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MENDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
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MIDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
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{
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s1 = readreg(s1, 4);
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s2 = readreg(s2, 4);
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d = writereg(d, 4);
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SIGNED16_REG_2_REG(REG_WORK3, s2);
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TST_rr(REG_WORK3, REG_WORK3);
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BNE_i(6); // src is not 0
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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STR_rR(REG_WORK1, REG_WORK2);
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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MOV_ri(REG_WORK1, ARM_Z_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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B_i(25); // end_of_op
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// src is not 0
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VMOVi_from_ARM_dr(SCRATCH_F64_1, s1, 0);
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VMOVi_from_ARM_dr(SCRATCH_F64_2, REG_WORK3, 0);
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VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
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VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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// check for overflow
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MVN_ri(REG_WORK2, 0);
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LSL_rri(REG_WORK2, REG_WORK2, 15); // REG_WORK2 is now 0xffff8000
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ANDS_rrr(REG_WORK3, REG_WORK1, REG_WORK2);
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BEQ_i(4); // positive result, no overflow
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CMP_rr(REG_WORK3, REG_WORK2);
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BEQ_i(2); // no overflow
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// Here we handle overflow
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MOV_ri(REG_WORK1, ARM_V_FLAG | ARM_N_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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B_i(9);
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// calc flags
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LSLS_rri(REG_WORK2, REG_WORK1, 16); // N and Z ok
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MRS_CPSR(REG_WORK2);
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BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
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MSR_CPSRf_r(REG_WORK2);
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// calc remainder
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SIGNED16_REG_2_REG(REG_WORK3, s2);
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MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
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SUB_rrr(REG_WORK2, s1, REG_WORK2); // REG_WORK2 contains remainder
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EORS_rrr(REG_WORK3, REG_WORK2, s1); // If sign of remainder and first operand differs, change sign of remainder
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CC_RSB_rri(NATIVE_CC_MI, REG_WORK2, REG_WORK2, 0);
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PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
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// end_of_op
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unlock2(d);
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unlock2(s1);
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unlock2(s2);
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}
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MENDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
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/*
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* EOR
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* Operand Syntax: Dn, <ea>
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@ -5114,7 +5279,7 @@ MIDFUNC(2,jnf_MEM_WRITE_OFF_b,(RR4 adr, RR4 b))
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LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
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adr = readreg(adr, 4);
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b = readreg(b, 4);
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b = readreg(b, 1);
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STRB_rRR(b, adr, REG_WORK2);
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@ -5129,7 +5294,7 @@ MIDFUNC(2,jnf_MEM_WRITE_OFF_w,(RR4 adr, RR4 w))
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LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
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adr = readreg(adr, 4);
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w = readreg(w, 4);
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w = readreg(w, 2);
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REV16_rr(REG_WORK1, w);
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STRH_rRR(REG_WORK1, adr, REG_WORK2);
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@ -5162,7 +5327,7 @@ MIDFUNC(2,jnf_MEM_READ_OFF_b,(W4 d, RR4 adr))
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LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
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adr = readreg(adr, 4);
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d = writereg(d, 4);
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d = writereg(d, 1);
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LDRB_rRR(d, adr, REG_WORK2);
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@ -5177,7 +5342,7 @@ MIDFUNC(2,jnf_MEM_READ_OFF_w,(W4 d, RR4 adr))
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LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
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adr = readreg(adr, 4);
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d = writereg(d, 4);
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d = writereg(d, 2);
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LDRH_rRR(REG_WORK1, adr, REG_WORK2);
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REV16_rr(d, REG_WORK1);
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@ -5210,7 +5375,7 @@ MIDFUNC(2,jnf_MEM_WRITE24_OFF_b,(RR4 adr, RR4 b))
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LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
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adr = readreg(adr, 4);
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b = readreg(b, 4);
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b = readreg(b, 1);
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BIC_rri(REG_WORK1, adr, 0xff000000);
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STRB_rRR(b, REG_WORK1, REG_WORK2);
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@ -5226,7 +5391,7 @@ MIDFUNC(2,jnf_MEM_WRITE24_OFF_w,(RR4 adr, RR4 w))
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LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
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adr = readreg(adr, 4);
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w = readreg(w, 4);
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w = readreg(w, 2);
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BIC_rri(REG_WORK1, adr, 0xff000000);
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REV16_rr(REG_WORK3, w);
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@ -5261,7 +5426,7 @@ MIDFUNC(2,jnf_MEM_READ24_OFF_b,(W4 d, RR4 adr))
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LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
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adr = readreg(adr, 4);
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d = writereg(d, 4);
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d = writereg(d, 1);
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BIC_rri(REG_WORK1, adr, 0xff000000);
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LDRB_rRR(d, REG_WORK1, REG_WORK2);
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@ -5277,7 +5442,7 @@ MIDFUNC(2,jnf_MEM_READ24_OFF_w,(W4 d, RR4 adr))
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LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
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adr = readreg(adr, 4);
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d = writereg(d, 4);
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d = writereg(d, 2);
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BIC_rri(REG_WORK1, adr, 0xff000000);
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LDRH_rRR(REG_WORK1, REG_WORK1, REG_WORK2);
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