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JIT: performance enhancements, implemented ROXR (merged from TomB)

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This commit is contained in:
Dimitris Panokostas 2018-04-02 17:25:57 +02:00
parent b477850782
commit e499bbeff3
12 changed files with 4998 additions and 4877 deletions
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43
src/jit/codegen_arm.cpp
View file

@ -82,11 +82,11 @@ extern void __clear_cache (char*, char*);
//#define REG_DATAPTR R10_INDEX
#define REG_PC_PRE R0_INDEX /* The register we use for preloading regs.pc_p */
#define REG_PC_TMP R1_INDEX /* Another register that is not the above */
#define R_MEMSTART 10
#define R_REGSTRUCT 11
uae_s8 always_used[]={2,3,R_REGSTRUCT,12,-1}; // r2, r3 and r12 are work register in emitted code
uae_s8 always_used[]={2,3,R_MEMSTART,R_REGSTRUCT,12,-1}; // r2, r3 and r12 are work register in emitted code
uae_u8 call_saved[]={0,0,0,0, 1,1,1,1, 1,1,1,1, 0,1,1,1};
@ -666,7 +666,7 @@ STATIC_INLINE void compemu_raw_branch(IMM d)
}
// Optimize access to struct regstruct with r11
// Optimize access to struct regstruct with r11 and memory with r10
LOWFUNC(NONE,NONE,1,compemu_raw_init_r_regstruct,(IMM s))
{
@ -677,6 +677,8 @@ LOWFUNC(NONE,NONE,1,compemu_raw_init_r_regstruct,(IMM s))
uae_s32 offs = data_long_offs(s);
LDR_rRI(R_REGSTRUCT, RPC_INDEX, offs);
#endif
uae_s32 offsmem = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(R_MEMSTART, R_REGSTRUCT, offsmem);
}
LENDFUNC(NONE,NONE,1,compemu_raw_init_r_regstruct,(IMM s))
@ -1096,24 +1098,22 @@ LENDFUNC(NONE,NONE,3,raw_fpowx_rr,(uae_u32 x, FW d, FR s))
LOWFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
VMOVi_to_ARM_rd(REG_WORK1, s, 1); // get high part of double
VCMP64_d0(s);
VMRS_CPSR();
#ifdef ARMV6T2
BEQ_i(20); // iszero
BEQ_i(19); // iszero
#else
BEQ_i(21);
BEQ_i(20);
#endif
UBFX_rrii(REG_WORK2, REG_WORK1, 20, 11); // get exponent
MOVW_ri16(REG_WORK3, 2047);
CMP_rr(REG_WORK2, REG_WORK3);
#ifdef ARMV6T2
BEQ_i(13); // isnan
BEQ_i(12); // isnan
#else
BEQ_i(14);
BEQ_i(13);
#endif
MOVW_ri16(REG_WORK3, 15360); // diff of bias between double and long double
@ -1121,8 +1121,7 @@ LOWFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
AND_rri(REG_WORK1, REG_WORK1, 0x80000000); // extract sign
ORR_rrrLSLi(REG_WORK2, REG_WORK1, REG_WORK2, 16); // merge sign and exponent
LDR_rRI(REG_WORK3, R_REGSTRUCT, offs);
ADD_rrr(REG_WORK3, adr, REG_WORK3);
ADD_rrr(REG_WORK3, adr, R_MEMSTART);
REV_rr(REG_WORK2, REG_WORK2);
STRH_rR(REG_WORK2, REG_WORK3); // write exponent
@ -1133,11 +1132,11 @@ LOWFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
ORR_rri(REG_WORK1, REG_WORK1, 0x80); // insert explicit 1
#ifdef ARMV6T2
STRD_rRI(REG_WORK1, REG_WORK3, 4);
B_i(9); // end_of_op
B_i(8); // end_of_op
#else
STR_rRI(REG_WORK1, REG_WORK3, 4);
STR_rRI(REG_WORK2, REG_WORK3, 8);
B_i(10);
B_i(9);
#endif
// isnan
@ -1149,8 +1148,7 @@ LOWFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
CC_AND_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, 0x80000000); // extract sign
CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
LDR_rRI(REG_WORK3, R_REGSTRUCT, offs);
ADD_rrr(REG_WORK3, adr, REG_WORK3);
ADD_rrr(REG_WORK3, adr, R_MEMSTART);
REV_rr(REG_WORK1, REG_WORK1);
#ifdef ARMV6T2
@ -1168,10 +1166,7 @@ LENDFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
LOWFUNC(NONE,READ,2,raw_fp_to_exten_rm,(FW d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK3, R_REGSTRUCT, offs);
ADD_rrr(REG_WORK3, adr, REG_WORK3);
ADD_rrr(REG_WORK3, adr, R_MEMSTART);
#ifdef ARMV6T2
LDRD_rRI(REG_WORK1, REG_WORK3, 4);
@ -1218,10 +1213,7 @@ LENDFUNC(NONE,READ,2,raw_fp_to_exten_rm,(FW d, RR4 adr))
LOWFUNC(NONE,WRITE,2,raw_fp_from_double_mr,(RR4 adr, FR s))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK3, R_REGSTRUCT, offs);
ADD_rrr(REG_WORK3, adr, REG_WORK3);
ADD_rrr(REG_WORK3, adr, R_MEMSTART);
VREV64_8_dd(SCRATCH_F64_1, s);
VSTR64_dRi(SCRATCH_F64_1, REG_WORK3, 0);
@ -1230,10 +1222,7 @@ LENDFUNC(NONE,WRITE,2,raw_fp_from_double_mr,(RR4 adr, FR s))
LOWFUNC(NONE,READ,2,raw_fp_to_double_rm,(FW d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK3, R_REGSTRUCT, offs);
ADD_rrr(REG_WORK3, adr, REG_WORK3);
ADD_rrr(REG_WORK3, adr, R_MEMSTART);
VLDR64_dRi(d, REG_WORK3, 0);
VREV64_8_dd(d, d);

8978
src/jit/compemu.cpp
View file

File diff suppressed because it is too large Load diff

24
src/jit/compemu.h
View file

@ -123,7 +123,7 @@ typedef union {
#if defined(CPU_arm)
//#define DEBUG_DATA_BUFFER
#define ALIGN_NOT_NEEDED
#define N_REGS 11 /* really 16, but 13 to 15 are SP, LR, PC; 12 is scratch reg and 11 holds regs-struct */
#define N_REGS 10 /* really 16, but 13 to 15 are SP, LR, PC; 12 is scratch reg, 10 holds memstart and 11 holds regs-struct */
#else
#define N_REGS 8 /* really only 7, but they are numbered 0,1,2,3,5,6,7 */
#endif
@ -298,17 +298,17 @@ extern int failure;
/* Convenience functions exposed to gencomp */
extern uae_u32 m68k_pc_offset;
extern void readbyte(int address, int dest, int tmp);
extern void readword(int address, int dest, int tmp);
extern void readlong(int address, int dest, int tmp);
extern void writebyte(int address, int source, int tmp);
extern void writeword(int address, int source, int tmp);
extern void writelong(int address, int source, int tmp);
extern void writeword_clobber(int address, int source, int tmp);
extern void writelong_clobber(int address, int source, int tmp);
extern void get_n_addr(int address, int dest, int tmp);
extern void get_n_addr_jmp(int address, int dest, int tmp);
extern void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp);
extern void readbyte(int address, int dest);
extern void readword(int address, int dest);
extern void readlong(int address, int dest);
extern void writebyte(int address, int source);
extern void writeword(int address, int source);
extern void writelong(int address, int source);
extern void writeword_clobber(int address, int source);
extern void writelong_clobber(int address, int source);
extern void get_n_addr(int address, int dest);
extern void get_n_addr_jmp(int address, int dest);
extern void calc_disp_ea_020(int base, uae_u32 dp, int target);
#define SYNC_PC_OFFSET 124
extern void sync_m68k_pc(void);
extern uae_u32 get_const(int r);

20
src/jit/compemu_fpp.cpp
View file

@ -77,7 +77,7 @@ STATIC_INLINE int comp_fp_get (uae_u32 opcode, uae_u16 extra, int treg)
case 6: /* (d8,An,Xn) or (bd,An,Xn) or ([bd,An,Xn],od) or ([bd,An],Xn,od) */
{
uae_u32 dp = comp_get_iword ((m68k_pc_offset += 2) - 2);
calc_disp_ea_020 (reg + 8, dp, S1, S2);
calc_disp_ea_020 (reg + 8, dp, S1);
break;
}
case 7:
@ -173,25 +173,25 @@ STATIC_INLINE int comp_fp_get (uae_u32 opcode, uae_u16 extra, int treg)
switch (size) {
case 0: /* Long */
readlong (S1, S2, S3);
readlong (S1, S2);
fmov_l_rr (treg, S2);
return 2;
case 1: /* Single */
readlong (S1, S2, S3);
readlong (S1, S2);
fmov_s_rr (treg, S2);
return 1;
case 2: /* Long Double */
fp_to_exten_rm (treg, S1);
return 0;
case 4: /* Word */
readword (S1, S2, S3);
readword (S1, S2);
fmov_w_rr (treg, S2);
return 1;
case 5: /* Double */
fp_to_double_rm (treg, S1);
return 2;
case 6: /* Byte */
readbyte (S1, S2, S3);
readbyte (S1, S2);
fmov_b_rr (treg, S2);
return 1;
default:
@ -251,7 +251,7 @@ STATIC_INLINE int comp_fp_put (uae_u32 opcode, uae_u16 extra)
case 6: /* (d8,An,Xn) or (bd,An,Xn) or ([bd,An,Xn],od) or ([bd,An],Xn,od) */
{
uae_u32 dp = comp_get_iword ((m68k_pc_offset += 2) - 2);
calc_disp_ea_020 (reg + 8, dp, S1, S2);
calc_disp_ea_020 (reg + 8, dp, S1);
break;
}
case 7:
@ -276,25 +276,25 @@ STATIC_INLINE int comp_fp_put (uae_u32 opcode, uae_u16 extra)
switch (size) {
case 0: /* Long */
fmov_to_l_rr(S2, sreg);
writelong_clobber (S1, S2, S3);
writelong_clobber (S1, S2);
return 0;
case 1: /* Single */
fmov_to_s_rr(S2, sreg);
writelong_clobber (S1, S2, S3);
writelong_clobber (S1, S2);
return 0;
case 2:/* Long Double */
fp_from_exten_mr (S1, sreg);
return 0;
case 4: /* Word */
fmov_to_w_rr(S2, sreg);
writeword_clobber (S1, S2, S3);
writeword_clobber (S1, S2);
return 0;
case 5: /* Double */
fp_from_double_mr(S1, sreg);
return 0;
case 6: /* Byte */
fmov_to_b_rr(S2, sreg);
writebyte (S1, S2, S3);
writebyte (S1, S2);
return 0;
default:
return -1;

97
src/jit/compemu_midfunc_arm.cpp
View file

@ -200,23 +200,55 @@ MIDFUNC(2,mov_l_mi,(IMM d, IMM s))
}
MENDFUNC(2,mov_l_mi,(IMM d, IMM s))
MIDFUNC(2,shll_l_ri,(RW4 r, IMM i))
MIDFUNC(4,disp_ea20_target_add,(RW4 target, RR4 reg, IMM shift, IMM extend))
{
// Only used in calc_disp_ea_020() -> flags not relevant and never modified
if (!i)
return;
if (isconst(r)) {
live.state[r].val <<= i;
if(isconst(target) && isconst(reg)) {
if(extend)
set_const(target, live.state[target].val + (((uae_s32)(uae_s16)live.state[reg].val) << (shift & 0x1f)));
else
set_const(target, live.state[target].val + (live.state[reg].val << (shift & 0x1f)));
return;
}
r = rmw(r);
reg = readreg(reg);
target = rmw(target);
LSL_rri(r,r, i & 0x1f);
unlock2(r);
if(extend) {
SIGNED16_REG_2_REG(REG_WORK1, reg);
ADD_rrrLSLi(target, target, REG_WORK1, shift & 0x1f);
} else {
ADD_rrrLSLi(target, target, reg, shift & 0x1f);
}
MENDFUNC(2,shll_l_ri,(RW4 r, IMM i))
unlock2(target);
unlock2(reg);
}
MENDFUNC(4,disp_ea20_target_add,(RW4 target, RR4 reg, IMM shift, IMM extend))
MIDFUNC(4,disp_ea20_target_mov,(W4 target, RR4 reg, IMM shift, IMM extend))
{
if(isconst(reg)) {
if(extend)
set_const(target, ((uae_s32)(uae_s16)live.state[reg].val) << (shift & 0x1f));
else
set_const(target, live.state[reg].val << (shift & 0x1f));
return;
}
reg = readreg(reg);
target = writereg(target);
if(extend) {
SIGNED16_REG_2_REG(REG_WORK1, reg);
LSL_rri(target, REG_WORK1, shift & 0x1f);
} else {
LSL_rri(target, reg, shift & 0x1f);
}
unlock2(target);
unlock2(reg);
}
MENDFUNC(4,disp_ea20_target_mov,(W4 target, RR4 reg, IMM shift, IMM extend))
MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
{
@ -478,49 +510,6 @@ MIDFUNC(2,sub_w_ri,(RW2 d, IMM i))
}
MENDFUNC(2,sub_w_ri,(RW2 d, IMM i))
MIDFUNC(3,call_r_02,(RR4 r, RR4 in1, RR4 in2))
{
clobber_flags();
in1 = readreg_specific(in1, REG_PAR1);
in2 = readreg_specific(in2, REG_PAR2);
r = readreg(r);
prepare_for_call_1();
unlock2(r);
unlock2(in1);
unlock2(in2);
prepare_for_call_2();
compemu_raw_call_r(r);
}
MENDFUNC(3,call_r_02,(RR4 r, RR4 in1, RR4 in2))
MIDFUNC(3,call_r_11,(W4 out1, RR4 r, RR4 in1))
{
clobber_flags();
if (out1 != in1 && out1 != r) {
COMPCALL(forget_about)(out1);
}
in1 = readreg_specific(in1, REG_PAR1);
r = readreg(r);
prepare_for_call_1();
unlock2(in1);
unlock2(r);
prepare_for_call_2();
compemu_raw_call_r(r);
live.nat[REG_RESULT].holds[0] = out1;
live.nat[REG_RESULT].nholds = 1;
live.nat[REG_RESULT].touched = touchcnt++;
live.state[out1].realreg = REG_RESULT;
live.state[out1].realind = 0;
live.state[out1].val = 0;
live.state[out1].validsize = 4;
set_status(out1, DIRTY);
}
MENDFUNC(3,call_r_11,(W4 out1, RR4 r, RR4 in1))
/* forget_about() takes a mid-layer register */
MIDFUNC(1,forget_about,(W4 r))

6
src/jit/compemu_midfunc_arm.h
View file

@ -38,8 +38,10 @@ DECLARE_MIDFUNC(arm_ADD_l_ri8(RW4 d, IMM i));
DECLARE_MIDFUNC(arm_SUB_l_ri8(RW4 d, IMM i));
// Emulated midfunc
DECLARE_MIDFUNC(disp_ea20_target_add(RW4 target, RR4 reg, IMM shift, IMM extend));
DECLARE_MIDFUNC(disp_ea20_target_mov(W4 target, RR4 reg, IMM shift, IMM extend));
DECLARE_MIDFUNC(mov_l_mi(IMM d, IMM s));
DECLARE_MIDFUNC(shll_l_ri(RW4 r, IMM i));
DECLARE_MIDFUNC(pop_l(W4 d));
DECLARE_MIDFUNC(push_l(RR4 s));
DECLARE_MIDFUNC(sign_extend_16_rr(W4 d, RR2 s));
@ -54,8 +56,6 @@ DECLARE_MIDFUNC(mov_l_ri(W4 d, IMM s));
DECLARE_MIDFUNC(mov_b_ri(W1 d, IMM s));
DECLARE_MIDFUNC(sub_l_ri(RW4 d, IMM i));
DECLARE_MIDFUNC(sub_w_ri(RW2 d, IMM i));
DECLARE_MIDFUNC(call_r_02(RR4 r, RR4 in1, RR4 in2));
DECLARE_MIDFUNC(call_r_11(W4 out1, RR4 r, RR4 in1));
DECLARE_MIDFUNC(live_flags(void));
DECLARE_MIDFUNC(dont_care_flags(void));
DECLARE_MIDFUNC(make_flags_live(void));

421
src/jit/compemu_midfunc_arm2.cpp
View file

@ -4064,11 +4064,8 @@ MIDFUNC(2,jnf_MOVE16,(RR4 d, RR4 s))
BIC_rri(s, s, 0x0000000F);
BIC_rri(d, d, 0x0000000F);
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK1, R_REGSTRUCT, offs);
ADD_rrr(s, s, REG_WORK1);
ADD_rrr(d, d, REG_WORK1);
ADD_rrr(s, s, R_MEMSTART);
ADD_rrr(d, d, R_MEMSTART);
#ifdef ARMV6T2
LDRD_rR(REG_WORK1, s);
@ -5591,10 +5588,11 @@ MIDFUNC(2,jff_ROXL_b,(RW1 d, RR4 i))
CMP_ri(REG_WORK1, 8);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
TST_rr(REG_WORK1, REG_WORK1);
BNE_i(2); // need to rotate
BNE_i(3); // need to rotate
MSR_CPSRf_i(0);
MOVS_rrLSLi(REG_WORK1, d, 24);
AND_rri(REG_WORK1, d, 0xff); // make sure to clear carry
MOVS_rrLSLi(REG_WORK1, REG_WORK1, 24);
#ifdef ARMV6T2
B_i(13); // end of op
#else
@ -5656,7 +5654,8 @@ MIDFUNC(2,jff_ROXL_w,(RW2 d, RR4 i))
BNE_i(3); // need to rotate
MSR_CPSRf_i(0);
MOVS_rrLSLi(REG_WORK1, d, 16);
BIC_rri(REG_WORK1, d, 0x00ff0000); // make sure to clear carry
MOVS_rrLSLi(REG_WORK1, REG_WORK1, 16);
#ifdef ARMV6T2
B_i(13); // end of op
#else
@ -6037,6 +6036,282 @@ MIDFUNC(1,jff_RORW,(RW2 d))
}
MENDFUNC(1,jff_RORW,(RW2 d))
/*
* ROXR
* Operand Syntax: Dx, Dy
* #<data>, Dy
*
* Operand Size: 8,16,32
*
* X Set according to the last bit rotated out of the operand. Unchanged when the rotate count is zero.
* N Set if the most significant bit of the result is set. Cleared otherwise.
* Z Set if the result is zero. Cleared otherwise.
* V Always cleared.
* C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
*
*/
MIDFUNC(2,jnf_ROXR_b,(RW1 d, RR4 i))
{
int x = readreg(FLAGX);
INIT_REGS_b(d, i);
clobber_flags();
AND_rri(REG_WORK1, i, 63);
CMP_ri(REG_WORK1, 35);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
CMP_ri(REG_WORK1, 17);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
CMP_ri(REG_WORK1, 8);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
TST_rr(REG_WORK1, REG_WORK1);
#ifdef ARMV6T2
BEQ_i(4); // end of op
#else
BEQ_i(6); // end of op
#endif
// need to rotate
AND_rri(REG_WORK2, d, 0xff); // val = val & 0xff
ORR_rrrLSLi(REG_WORK2, REG_WORK2, REG_WORK2, 9); // val = val | (val << 9)
ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 8); // val = val | (x << 8)
MOV_rrLSRr(REG_WORK2, REG_WORK2, REG_WORK1); // val = val >> cnt
#ifdef ARMV6T2
BFI_rrii(d, REG_WORK2, 0, 7);
#else
AND_rri(REG_WORK2, REG_WORK2, 0xff);
BIC_rri(d, d, 0xff);
ORR_rrr(d, d, REG_WORK2);
#endif
// end of op
unlock2(x);
EXIT_REGS(d, i);
}
MENDFUNC(2,jnf_ROXR_b,(RW1 d, RR4 i))
MIDFUNC(2,jnf_ROXR_w,(RW2 d, RR4 i))
{
int x = readreg(FLAGX);
INIT_REGS_w(d, i);
clobber_flags();
AND_rri(REG_WORK1, i, 63);
CMP_ri(REG_WORK1, 33);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
CMP_ri(REG_WORK1, 16);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
TST_rr(REG_WORK1, REG_WORK1);
BEQ_i(5); // end of op
// need to rotate
BIC_rri(REG_WORK2, d, 0xff000000);
BIC_rri(REG_WORK2, REG_WORK2, 0x00ff0000); // val = val & 0xffff
ORR_rrrLSLi(REG_WORK2, REG_WORK2, REG_WORK2, 17); // val = val | (val << 17)
ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 16); // val = val | (x << 16)
MOV_rrLSRr(REG_WORK2, REG_WORK2, REG_WORK1); // val = val >> cnt
PKHTB_rrr(d, d, REG_WORK2);
// end of op
unlock2(x);
EXIT_REGS(d, i);
}
MENDFUNC(2,jnf_ROXR_w,(RW2 d, RR4 i))
MIDFUNC(2,jnf_ROXR_l,(RW4 d, RR4 i))
{
int x = readreg(FLAGX);
INIT_REGS_l(d, i);
clobber_flags();
AND_rri(REG_WORK1, i, 63);
CMP_ri(REG_WORK1, 32);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
TST_rr(REG_WORK1, REG_WORK1);
BEQ_i(6); // end of op
// need to rotate
CMP_ri(REG_WORK1, 32);
CC_MOV_rrLSRr(NATIVE_CC_NE, REG_WORK2, d, REG_WORK1);
CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
RSB_rri(REG_WORK3, REG_WORK1, 32);
ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
ADD_rri(REG_WORK3, REG_WORK1, 1);
ORR_rrrLSLr(d, REG_WORK2, d, REG_WORK3);
// end of op
unlock2(x);
EXIT_REGS(d, i);
}
MENDFUNC(2,jnf_ROXR_l,(RW4 d, RR4 i))
MIDFUNC(2,jff_ROXR_b,(RW1 d, RR4 i))
{
INIT_REGS_b(d, i);
int x = rmw(FLAGX);
AND_rri(REG_WORK1, i, 63);
CMP_ri(REG_WORK1, 35);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
CMP_ri(REG_WORK1, 17);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
CMP_ri(REG_WORK1, 8);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
TST_rr(REG_WORK1, REG_WORK1);
BNE_i(3); // need to rotate
MSR_CPSRf_i(0);
BIC_rri(REG_WORK1, d, 0x0000ff00); // make sure to clear carry
MOVS_rrLSLi(REG_WORK1, REG_WORK1, 24);
#ifdef ARMV6T2
B_i(9); // end of op
#else
B_i(12); // end of op
#endif
// need to rotate
AND_rri(REG_WORK2, d, 0xff); // val = val & 0xff
ORR_rrrLSLi(REG_WORK2, REG_WORK2, REG_WORK2, 9); // val = val | (val << 9)
ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 8); // val = val | (x << 8)
MSR_CPSRf_i(0);
MOVS_rrLSRr(REG_WORK2, REG_WORK2, REG_WORK1); // val = val >> cnt
// Duplicate carry
MOV_ri(x, 1);
CC_MOV_ri(NATIVE_CC_CC, x, 0);
// Calc N and Z
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, x, 8, 8); // Make sure to set carry (last bit shifted out)
#else
BIC_rri(REG_WORK2, REG_WORK2, 0x100);
ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 8);
#endif
LSLS_rri(REG_WORK1, REG_WORK2, 24);
#ifdef ARMV6T2
BFI_rrii(d, REG_WORK2, 0, 7);
#else
AND_rri(REG_WORK2, REG_WORK2, 0xff);
BIC_rri(d, d, 0xff);
ORR_rrr(d, d, REG_WORK2);
#endif
// end of op
unlock2(x);
EXIT_REGS(d, i);
}
MENDFUNC(2,jff_ROXR_b,(RW1 d, RR4 i))
MIDFUNC(2,jff_ROXR_w,(RW2 d, RR4 i))
{
INIT_REGS_w(d, i);
int x = rmw(FLAGX);
AND_rri(REG_WORK1, i, 63);
CMP_ri(REG_WORK1, 33);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
CMP_ri(REG_WORK1, 16);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
TST_rr(REG_WORK1, REG_WORK1);
BNE_i(3); // need to rotate
MSR_CPSRf_i(0);
BIC_rri(REG_WORK1, d, 0x00ff0000); // make sure to clear carry
MOVS_rrLSLi(REG_WORK1, REG_WORK1, 16);
#ifdef ARMV6T2
B_i(10); // end of op
#else
B_i(11); // end of op
#endif
// need to rotate
BIC_rri(REG_WORK2, d, 0xff000000);
BIC_rri(REG_WORK2, REG_WORK2, 0x00ff0000); // val = val & 0xffff
ORR_rrrLSLi(REG_WORK2, REG_WORK2, REG_WORK2, 17); // val = val | (val << 17)
ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 16); // val = val | (x << 16)
MSR_CPSRf_i(0);
MOVS_rrLSRr(REG_WORK2, REG_WORK2, REG_WORK1); // val = val >> cnt
// Duplicate carry
MOV_ri(x, 1);
CC_MOV_ri(NATIVE_CC_CC, x, 0);
// Calc N and Z
#ifdef ARMV6T2
BFI_rrii(REG_WORK2, x, 16, 16); // Make sure to set carry (last bit shifted out)
#else
BIC_rri(REG_WORK2, REG_WORK2, 0x10000);
ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 16);
#endif
LSLS_rri(REG_WORK1, REG_WORK2, 16);
PKHTB_rrr(d, d, REG_WORK2);
// end of op
unlock2(x);
EXIT_REGS(d, i);
}
MENDFUNC(2,jff_ROXR_w,(RW2 d, RR4 i))
MIDFUNC(2,jff_ROXR_l,(RW4 d, RR4 i))
{
INIT_REGS_l(d, i);
int x = rmw(FLAGX);
AND_rri(REG_WORK1, i, 63);
CMP_ri(REG_WORK1, 32);
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
TST_rr(REG_WORK1, REG_WORK1);
BNE_i(2); // need to rotate
MSR_CPSRf_i(0);
TST_rr(d, d);
B_i(13); // end of op
// need to rotate
CMP_ri(REG_WORK1, 32);
BNE_i(3); // rotate 1-31
// rotate 32
MSR_CPSRf_i(0);
LSLS_rri(d, d, 1);
ORRS_rrr(d, d, x);
B_i(5); // duplicate carry
// rotate 1-31
MSR_CPSRf_i(0);
MOVS_rrLSRr(REG_WORK2, d, REG_WORK1);
RSB_rri(REG_WORK3, REG_WORK1, 32);
ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
ADD_rri(REG_WORK3, REG_WORK1, 1);
ORR_rrrLSLr(d, REG_WORK2, d, REG_WORK3);
// Duplicate carry
MOV_ri(x, 1);
CC_MOV_ri(NATIVE_CC_CC, x, 0);
// end of op
unlock2(x);
EXIT_REGS(d, i);
}
MENDFUNC(2,jff_ROXR_l,(RW4 d, RR4 i))
/*
* SCC
*
@ -6654,13 +6929,10 @@ MENDFUNC(1,jff_TST_l,(RR4 s))
*/
MIDFUNC(2,jnf_MEM_WRITE_OFF_b,(RR4 adr, RR4 b))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
b = readreg(b);
STRB_rRR(b, adr, REG_WORK2);
STRB_rRR(b, adr, R_MEMSTART);
unlock2(b);
unlock2(adr);
@ -6669,14 +6941,11 @@ MENDFUNC(2,jnf_MEM_WRITE_OFF_b,(RR4 adr, RR4 b))
MIDFUNC(2,jnf_MEM_WRITE_OFF_w,(RR4 adr, RR4 w))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
w = readreg(w);
REV16_rr(REG_WORK1, w);
STRH_rRR(REG_WORK1, adr, REG_WORK2);
STRH_rRR(REG_WORK1, adr, R_MEMSTART);
unlock2(w);
unlock2(adr);
@ -6685,14 +6954,11 @@ MENDFUNC(2,jnf_MEM_WRITE_OFF_w,(RR4 adr, RR4 w))
MIDFUNC(2,jnf_MEM_WRITE_OFF_l,(RR4 adr, RR4 l))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
l = readreg(l);
REV_rr(REG_WORK1, l);
STR_rRR(REG_WORK1, adr, REG_WORK2);
STR_rRR(REG_WORK1, adr, R_MEMSTART);
unlock2(l);
unlock2(adr);
@ -6702,13 +6968,10 @@ MENDFUNC(2,jnf_MEM_WRITE_OFF_l,(RR4 adr, RR4 l))
MIDFUNC(2,jnf_MEM_READ_OFF_b,(W4 d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
d = writereg(d);
LDRB_rRR(d, adr, REG_WORK2);
LDRB_rRR(d, adr, R_MEMSTART);
unlock2(d);
unlock2(adr);
@ -6717,13 +6980,10 @@ MENDFUNC(2,jnf_MEM_READ_OFF_b,(W4 d, RR4 adr))
MIDFUNC(2,jnf_MEM_READ_OFF_w,(W4 d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
d = writereg(d);
LDRH_rRR(REG_WORK1, adr, REG_WORK2);
LDRH_rRR(REG_WORK1, adr, R_MEMSTART);
REV16_rr(d, REG_WORK1);
unlock2(d);
@ -6733,13 +6993,10 @@ MENDFUNC(2,jnf_MEM_READ_OFF_w,(W4 d, RR4 adr))
MIDFUNC(2,jnf_MEM_READ_OFF_l,(W4 d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
d = writereg(d);
LDR_rRR(REG_WORK1, adr, REG_WORK2);
LDR_rRR(REG_WORK1, adr, R_MEMSTART);
REV_rr(d, REG_WORK1);
unlock2(d);
@ -6750,14 +7007,11 @@ MENDFUNC(2,jnf_MEM_READ_OFF_l,(W4 d, RR4 adr))
MIDFUNC(2,jnf_MEM_WRITE24_OFF_b,(RR4 adr, RR4 b))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
b = readreg(b);
BIC_rri(REG_WORK1, adr, 0xff000000);
STRB_rRR(b, REG_WORK1, REG_WORK2);
STRB_rRR(b, REG_WORK1, R_MEMSTART);
unlock2(b);
unlock2(adr);
@ -6766,15 +7020,12 @@ MENDFUNC(2,jnf_MEM_WRITE24_OFF_b,(RR4 adr, RR4 b))
MIDFUNC(2,jnf_MEM_WRITE24_OFF_w,(RR4 adr, RR4 w))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
w = readreg(w);
BIC_rri(REG_WORK1, adr, 0xff000000);
REV16_rr(REG_WORK3, w);
STRH_rRR(REG_WORK3, REG_WORK1, REG_WORK2);
STRH_rRR(REG_WORK3, REG_WORK1, R_MEMSTART);
unlock2(w);
unlock2(adr);
@ -6783,15 +7034,12 @@ MENDFUNC(2,jnf_MEM_WRITE24_OFF_w,(RR4 adr, RR4 w))
MIDFUNC(2,jnf_MEM_WRITE24_OFF_l,(RR4 adr, RR4 l))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
l = readreg(l);
BIC_rri(REG_WORK1, adr, 0xff000000);
REV_rr(REG_WORK3, l);
STR_rRR(REG_WORK3, REG_WORK1, REG_WORK2);
STR_rRR(REG_WORK3, REG_WORK1, R_MEMSTART);
unlock2(l);
unlock2(adr);
@ -6801,14 +7049,11 @@ MENDFUNC(2,jnf_MEM_WRITE24_OFF_l,(RR4 adr, RR4 l))
MIDFUNC(2,jnf_MEM_READ24_OFF_b,(W4 d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
d = writereg(d);
BIC_rri(REG_WORK1, adr, 0xff000000);
LDRB_rRR(d, REG_WORK1, REG_WORK2);
LDRB_rRR(d, REG_WORK1, R_MEMSTART);
unlock2(d);
unlock2(adr);
@ -6817,14 +7062,11 @@ MENDFUNC(2,jnf_MEM_READ24_OFF_b,(W4 d, RR4 adr))
MIDFUNC(2,jnf_MEM_READ24_OFF_w,(W4 d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
d = writereg(d);
BIC_rri(REG_WORK1, adr, 0xff000000);
LDRH_rRR(REG_WORK1, REG_WORK1, REG_WORK2);
LDRH_rRR(REG_WORK1, REG_WORK1, R_MEMSTART);
REV16_rr(d, REG_WORK1);
unlock2(d);
@ -6834,14 +7076,11 @@ MENDFUNC(2,jnf_MEM_READ24_OFF_w,(W4 d, RR4 adr))
MIDFUNC(2,jnf_MEM_READ24_OFF_l,(W4 d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
d = writereg(d);
BIC_rri(REG_WORK1, adr, 0xff000000);
LDR_rRR(d, REG_WORK1, REG_WORK2);
LDR_rRR(d, REG_WORK1, R_MEMSTART);
REV_rr(d, d);
unlock2(d);
@ -6852,13 +7091,10 @@ MENDFUNC(2,jnf_MEM_READ24_OFF_l,(W4 d, RR4 adr))
MIDFUNC(2,jnf_MEM_GETADR_OFF,(W4 d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
d = writereg(d);
ADD_rrr(d, adr, REG_WORK2);
ADD_rrr(d, adr, R_MEMSTART);
unlock2(d);
unlock2(adr);
@ -6867,14 +7103,11 @@ MENDFUNC(2,jnf_MEM_GETADR_OFF,(W4 d, RR4 adr))
MIDFUNC(2,jnf_MEM_GETADR24_OFF,(W4 d, RR4 adr))
{
uae_s32 offs = (uae_u32)&NATMEM_OFFSETX - (uae_u32) &regs;
LDR_rRI(REG_WORK2, R_REGSTRUCT, offs);
adr = readreg(adr);
d = writereg(d);
BIC_rri(REG_WORK1, adr, 0xff000000);
ADD_rrr(d, REG_WORK1, REG_WORK2);
ADD_rrr(d, REG_WORK1, R_MEMSTART);
unlock2(d);
unlock2(adr);
@ -6882,10 +7115,17 @@ MIDFUNC(2,jnf_MEM_GETADR24_OFF,(W4 d, RR4 adr))
MENDFUNC(2,jnf_MEM_GETADR24_OFF,(W4 d, RR4 adr))
MIDFUNC(2,jnf_MEM_GETBANKFUNC,(W4 d, RR4 adr, IMM offset))
MIDFUNC(3,jnf_MEM_READMEMBANK,(W4 dest, RR4 adr, IMM offset))
{
adr = readreg(adr);
d = writereg(d);
clobber_flags();
if (dest != adr) {
COMPCALL(forget_about)(dest);
}
adr = readreg_specific(adr, REG_PAR1);
prepare_for_call_1();
unlock2(adr);
prepare_for_call_2();
#ifdef ARMV6T2
MOVW_ri16(REG_WORK2, (uae_u32)mem_banks);
@ -6895,10 +7135,47 @@ MIDFUNC(2,jnf_MEM_GETBANKFUNC,(W4 d, RR4 adr, IMM offset))
LDR_rRI(REG_WORK2, RPC_INDEX, offs);
#endif
LSR_rri(REG_WORK1, adr, 16);
LDR_rRR_LSLi(d, REG_WORK2, REG_WORK1, 2);
LDR_rRI(d, d, offset);
LDR_rRR_LSLi(REG_WORK3, REG_WORK2, REG_WORK1, 2);
LDR_rRI(REG_WORK3, REG_WORK3, offset);
unlock2(d);
unlock2(adr);
compemu_raw_call_r(REG_WORK3);
live.nat[REG_RESULT].holds[0] = dest;
live.nat[REG_RESULT].nholds = 1;
live.nat[REG_RESULT].touched = touchcnt++;
live.state[dest].realreg = REG_RESULT;
live.state[dest].realind = 0;
live.state[dest].val = 0;
live.state[dest].validsize = 4;
set_status(dest, DIRTY);
}
MENDFUNC(2,jnf_MEM_GETBANKFUNC,(W4 d, RR4 adr, IMM offset))
MENDFUNC(3,jnf_MEM_READMEMBANK,(W4 dest, RR4 adr, IMM offset))
MIDFUNC(3,jnf_MEM_WRITEMEMBANK,(RR4 adr, RR4 source, IMM offset))
{
clobber_flags();
adr = readreg_specific(adr, REG_PAR1);
source = readreg_specific(source, REG_PAR2);
prepare_for_call_1();
unlock2(adr);
unlock2(source);
prepare_for_call_2();
#ifdef ARMV6T2
MOVW_ri16(REG_WORK2, (uae_u32)mem_banks);
MOVT_ri16(REG_WORK2, (uae_u32)mem_banks >> 16);
#else
uae_s32 offs = data_long_offs((uae_u32)mem_banks);
LDR_rRI(REG_WORK2, RPC_INDEX, offs);
#endif
LSR_rri(REG_WORK1, adr, 16);
LDR_rRR_LSLi(REG_WORK3, REG_WORK2, REG_WORK1, 2);
LDR_rRI(REG_WORK3, REG_WORK3, offset);
compemu_raw_call_r(REG_WORK3);
}
MENDFUNC(3,jnf_MEM_WRITEMEMBANK,(RR4 adr, RR4 source, IMM offset))

12
src/jit/compemu_midfunc_arm2.h
View file

@ -357,6 +357,14 @@ DECLARE_MIDFUNC(jff_ROR_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ROR_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ROR_l(RW4 d, RR4 i));
// ROXR
DECLARE_MIDFUNC(jnf_ROXR_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROXR_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jnf_ROXR_l(RW4 d, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_b(RW1 d, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_w(RW2 d, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_l(RW4 d, RR4 i));
// Scc
DECLARE_MIDFUNC(jnf_SCC(W1 d, IMM cc));
@ -412,4 +420,6 @@ DECLARE_MIDFUNC(jnf_MEM_READ24_OFF_l(W4 d, RR4 adr));
DECLARE_MIDFUNC(jnf_MEM_GETADR_OFF(W4 d, RR4 adr));
DECLARE_MIDFUNC(jnf_MEM_GETADR24_OFF(W4 d, RR4 adr));
DECLARE_MIDFUNC(jnf_MEM_GETBANKFUNC(W4 d, RR4 adr, IMM offset));
DECLARE_MIDFUNC(jnf_MEM_READMEMBANK(W4 dest, RR4 adr, IMM offset));
DECLARE_MIDFUNC(jnf_MEM_WRITEMEMBANK(RR4 adr, RR4 source, IMM offset));

110
src/jit/compemu_support.cpp
View file

@ -1544,7 +1544,7 @@ void freescratch(void)
int i;
for (i=0; i<N_REGS; i++)
#if defined(CPU_arm)
if (live.nat[i].locked && i != 2 && i != 3 && i != 11 && i != 12) {
if (live.nat[i].locked && i != 2 && i != 3 && i != 10 && i != 11 && i != 12) {
#else
if (live.nat[i].locked && i!=4 && i!= 12) {
#endif
@ -1663,74 +1663,52 @@ static void writemem_real(int address, int source, int size)
}
}
STATIC_INLINE void writemem_special(int address, int source, int offset, int tmp)
STATIC_INLINE void writemem_special(int address, int source, int offset)
{
jnf_MEM_GETBANKFUNC(tmp, address, offset);
/* Now tmp holds the address of the b/w/lput function */
call_r_02(tmp, address, source);
forget_about(tmp);
jnf_MEM_WRITEMEMBANK(address, source, offset);
}
void writebyte(int address, int source, int tmp)
void writebyte(int address, int source)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 20, tmp);
writemem_special(address, source, 20);
else
writemem_real(address, source, 1);
}
void writeword(int address, int source, int tmp)
void writeword(int address, int source)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 16, tmp);
writemem_special(address, source, 16);
else
writemem_real(address, source, 2);
}
void writelong(int address, int source, int tmp)
void writelong(int address, int source)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 12, tmp);
writemem_special(address, source, 12);
else
writemem_real(address, source, 4);
}
// Now the same for clobber variant
STATIC_INLINE void writemem_real_clobber(int address, int source, int size)
void writeword_clobber(int address, int source)
{
if(currprefs.address_space_24)
{
switch(size) {
case 1: jnf_MEM_WRITE24_OFF_b(address, source); break;
case 2: jnf_MEM_WRITE24_OFF_w(address, source); break;
case 4: jnf_MEM_WRITE24_OFF_l(address, source); break;
}
}
if (special_mem & S_WRITE)
writemem_special(address, source, 16);
else
{
switch(size) {
case 1: jnf_MEM_WRITE_OFF_b(address, source); break;
case 2: jnf_MEM_WRITE_OFF_w(address, source); break;
case 4: jnf_MEM_WRITE_OFF_l(address, source); break;
}
}
writemem_real(address, source, 2);
forget_about(source);
}
void writeword_clobber(int address, int source, int tmp)
void writelong_clobber(int address, int source)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 16, tmp);
writemem_special(address, source, 12);
else
writemem_real_clobber(address, source, 2);
}
void writelong_clobber(int address, int source, int tmp)
{
if (special_mem & S_WRITE)
writemem_special(address, source, 12, tmp);
else
writemem_real_clobber(address, source, 4);
writemem_real(address, source, 4);
forget_about(source);
}
@ -1758,42 +1736,39 @@ static void readmem_real(int address, int dest, int size)
}
}
STATIC_INLINE void readmem_special(int address, int dest, int offset, int tmp)
STATIC_INLINE void readmem_special(int address, int dest, int offset)
{
jnf_MEM_GETBANKFUNC(tmp, address, offset);
/* Now tmp holds the address of the b/w/lget function */
call_r_11(dest, tmp, address);
forget_about(tmp);
jnf_MEM_READMEMBANK(dest, address, offset);
}
void readbyte(int address, int dest, int tmp)
void readbyte(int address, int dest)
{
if (special_mem & S_READ)
readmem_special(address, dest, 8, tmp);
readmem_special(address, dest, 8);
else
readmem_real(address, dest, 1);
}
void readword(int address, int dest, int tmp)
void readword(int address, int dest)
{
if (special_mem & S_READ)
readmem_special(address, dest, 4, tmp);
readmem_special(address, dest, 4);
else
readmem_real(address, dest, 2);
}
void readlong(int address, int dest, int tmp)
void readlong(int address, int dest)
{
if (special_mem & S_READ)
readmem_special(address, dest, 0, tmp);
readmem_special(address, dest, 0);
else
readmem_real(address, dest, 4);
}
/* This one might appear a bit odd... */
STATIC_INLINE void get_n_addr_old(int address, int dest, int tmp)
STATIC_INLINE void get_n_addr_old(int address, int dest)
{
readmem_special(address, dest, 24, tmp);
readmem_special(address, dest, 24);
}
STATIC_INLINE void get_n_addr_real(int address, int dest)
@ -1804,27 +1779,27 @@ STATIC_INLINE void get_n_addr_real(int address, int dest)
jnf_MEM_GETADR_OFF(dest, address);
}
void get_n_addr(int address, int dest, int tmp)
void get_n_addr(int address, int dest)
{
if (special_mem)
get_n_addr_old(address,dest,tmp);
get_n_addr_old(address, dest);
else
get_n_addr_real(address,dest);
}
void get_n_addr_jmp(int address, int dest, int tmp)
void get_n_addr_jmp(int address, int dest)
{
/* For this, we need to get the same address as the rest of UAE
would --- otherwise we end up translating everything twice */
if (special_mem)
get_n_addr_old(address,dest,tmp);
get_n_addr_old(address, dest);
else
get_n_addr_real(address,dest);
}
/* base is a register, but dp is an actual value.
target is a register, as is tmp */
void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
target is a register */
void calc_disp_ea_020(int base, uae_u32 dp, int target)
{
int reg = (dp >> 12) & 15;
int regd_shift=(dp >> 9) & 3;
@ -1843,11 +1818,7 @@ void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
if ((dp & 0x4) == 0) { /* add regd *before* the get_long */
if (!ignorereg) {
if ((dp & 0x800) == 0)
sign_extend_16_rr(target, reg);
else
mov_l_rr(target, reg);
shll_l_ri(target, regd_shift);
disp_ea20_target_mov(target, reg, regd_shift, ((dp & 0x800) == 0));
}
else
mov_l_ri(target, 0);
@ -1856,7 +1827,7 @@ void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
if (!ignorebase)
arm_ADD_l(target, base);
arm_ADD_l_ri(target, addbase);
if (dp&0x03) readlong(target, target, tmp);
if (dp&0x03) readlong(target, target);
} else { /* do the getlong first, then add regd */
if (!ignorebase) {
mov_l_rr(target, base);
@ -1864,16 +1835,10 @@ void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
}
else
mov_l_ri(target, addbase);
if (dp&0x03) readlong(target, target, tmp);
if (dp&0x03) readlong(target, target);
if (!ignorereg) {
if ((dp & 0x800) == 0)
sign_extend_16_rr(tmp, reg);
else
mov_l_rr(tmp, reg);
shll_l_ri(tmp, regd_shift);
/* tmp is now regd */
arm_ADD_l(target, tmp);
disp_ea20_target_add(target, reg, regd_shift, ((dp & 0x800) == 0));
}
}
arm_ADD_l_ri(target, outer);
@ -1887,7 +1852,6 @@ void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
lea_l_brr_indexed(target, base, reg, 1 << regd_shift, (uae_s8)dp);
}
}
forget_about(tmp);
}
void set_cache_state(int enabled)

24
src/jit/compstbl.cpp
View file

@ -1636,27 +1636,27 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
{ op_d1fc_0_comp_ff, 0x00000002, 53756 }, /* ADDA */
{ op_e000_0_comp_ff, 0x00000000, 57344 }, /* ASR */
{ op_e008_0_comp_ff, 0x00000000, 57352 }, /* LSR */
{ NULL, 0x00000008, 57360 }, /* ROXR */
{ op_e010_0_comp_ff, 0x00000008, 57360 }, /* ROXR */
{ op_e018_0_comp_ff, 0x00000000, 57368 }, /* ROR */
{ op_e020_0_comp_ff, 0x00000000, 57376 }, /* ASR */
{ op_e028_0_comp_ff, 0x00000000, 57384 }, /* LSR */
{ NULL, 0x00000008, 57392 }, /* ROXR */
{ op_e030_0_comp_ff, 0x00000008, 57392 }, /* ROXR */
{ op_e038_0_comp_ff, 0x00000000, 57400 }, /* ROR */
{ op_e040_0_comp_ff, 0x00000000, 57408 }, /* ASR */
{ op_e048_0_comp_ff, 0x00000000, 57416 }, /* LSR */
{ NULL, 0x00000008, 57424 }, /* ROXR */
{ op_e050_0_comp_ff, 0x00000008, 57424 }, /* ROXR */
{ op_e058_0_comp_ff, 0x00000000, 57432 }, /* ROR */
{ op_e060_0_comp_ff, 0x00000000, 57440 }, /* ASR */
{ op_e068_0_comp_ff, 0x00000000, 57448 }, /* LSR */
{ NULL, 0x00000008, 57456 }, /* ROXR */
{ op_e070_0_comp_ff, 0x00000008, 57456 }, /* ROXR */
{ op_e078_0_comp_ff, 0x00000000, 57464 }, /* ROR */
{ op_e080_0_comp_ff, 0x00000000, 57472 }, /* ASR */
{ op_e088_0_comp_ff, 0x00000000, 57480 }, /* LSR */
{ NULL, 0x00000008, 57488 }, /* ROXR */
{ op_e090_0_comp_ff, 0x00000008, 57488 }, /* ROXR */
{ op_e098_0_comp_ff, 0x00000000, 57496 }, /* ROR */
{ op_e0a0_0_comp_ff, 0x00000000, 57504 }, /* ASR */
{ op_e0a8_0_comp_ff, 0x00000000, 57512 }, /* LSR */
{ NULL, 0x00000008, 57520 }, /* ROXR */
{ op_e0b0_0_comp_ff, 0x00000008, 57520 }, /* ROXR */
{ op_e0b8_0_comp_ff, 0x00000000, 57528 }, /* ROR */
{ op_e0d0_0_comp_ff, 0x00000000, 57552 }, /* ASRW */
{ op_e0d8_0_comp_ff, 0x00000000, 57560 }, /* ASRW */
@ -3508,27 +3508,27 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
{ op_d1fc_0_comp_nf, 0x00000002, 53756 }, /* ADDA */
{ op_e000_0_comp_nf, 0x00000000, 57344 }, /* ASR */
{ op_e008_0_comp_nf, 0x00000000, 57352 }, /* LSR */
{ NULL, 0x00000008, 57360 }, /* ROXR */
{ op_e010_0_comp_nf, 0x00000008, 57360 }, /* ROXR */
{ op_e018_0_comp_nf, 0x00000000, 57368 }, /* ROR */
{ op_e020_0_comp_nf, 0x00000000, 57376 }, /* ASR */
{ op_e028_0_comp_nf, 0x00000000, 57384 }, /* LSR */
{ NULL, 0x00000008, 57392 }, /* ROXR */
{ op_e030_0_comp_nf, 0x00000008, 57392 }, /* ROXR */
{ op_e038_0_comp_nf, 0x00000000, 57400 }, /* ROR */
{ op_e040_0_comp_nf, 0x00000000, 57408 }, /* ASR */
{ op_e048_0_comp_nf, 0x00000000, 57416 }, /* LSR */
{ NULL, 0x00000008, 57424 }, /* ROXR */
{ op_e050_0_comp_nf, 0x00000008, 57424 }, /* ROXR */
{ op_e058_0_comp_nf, 0x00000000, 57432 }, /* ROR */
{ op_e060_0_comp_nf, 0x00000000, 57440 }, /* ASR */
{ op_e068_0_comp_nf, 0x00000000, 57448 }, /* LSR */
{ NULL, 0x00000008, 57456 }, /* ROXR */
{ op_e070_0_comp_nf, 0x00000008, 57456 }, /* ROXR */
{ op_e078_0_comp_nf, 0x00000000, 57464 }, /* ROR */
{ op_e080_0_comp_nf, 0x00000000, 57472 }, /* ASR */
{ op_e088_0_comp_nf, 0x00000000, 57480 }, /* LSR */
{ NULL, 0x00000008, 57488 }, /* ROXR */
{ op_e090_0_comp_nf, 0x00000008, 57488 }, /* ROXR */
{ op_e098_0_comp_nf, 0x00000000, 57496 }, /* ROR */
{ op_e0a0_0_comp_nf, 0x00000000, 57504 }, /* ASR */
{ op_e0a8_0_comp_nf, 0x00000000, 57512 }, /* LSR */
{ NULL, 0x00000008, 57520 }, /* ROXR */
{ op_e0b0_0_comp_nf, 0x00000008, 57520 }, /* ROXR */
{ op_e0b8_0_comp_nf, 0x00000000, 57528 }, /* ROR */
{ op_e0d0_0_comp_nf, 0x00000000, 57552 }, /* ASRW */
{ op_e0d8_0_comp_nf, 0x00000000, 57560 }, /* ASRW */

12
src/jit/comptbl.h
View file

@ -1399,21 +1399,27 @@ extern compop_func op_d1fb_0_comp_ff;
extern compop_func op_d1fc_0_comp_ff;
extern compop_func op_e000_0_comp_ff;
extern compop_func op_e008_0_comp_ff;
extern compop_func op_e010_0_comp_ff;
extern compop_func op_e018_0_comp_ff;
extern compop_func op_e020_0_comp_ff;
extern compop_func op_e028_0_comp_ff;
extern compop_func op_e030_0_comp_ff;
extern compop_func op_e038_0_comp_ff;
extern compop_func op_e040_0_comp_ff;
extern compop_func op_e048_0_comp_ff;
extern compop_func op_e050_0_comp_ff;
extern compop_func op_e058_0_comp_ff;
extern compop_func op_e060_0_comp_ff;
extern compop_func op_e068_0_comp_ff;
extern compop_func op_e070_0_comp_ff;
extern compop_func op_e078_0_comp_ff;
extern compop_func op_e080_0_comp_ff;
extern compop_func op_e088_0_comp_ff;
extern compop_func op_e090_0_comp_ff;
extern compop_func op_e098_0_comp_ff;
extern compop_func op_e0a0_0_comp_ff;
extern compop_func op_e0a8_0_comp_ff;
extern compop_func op_e0b0_0_comp_ff;
extern compop_func op_e0b8_0_comp_ff;
extern compop_func op_e0d0_0_comp_ff;
extern compop_func op_e0d8_0_comp_ff;
@ -2907,21 +2913,27 @@ extern compop_func op_d1fb_0_comp_nf;
extern compop_func op_d1fc_0_comp_nf;
extern compop_func op_e000_0_comp_nf;
extern compop_func op_e008_0_comp_nf;
extern compop_func op_e010_0_comp_nf;
extern compop_func op_e018_0_comp_nf;
extern compop_func op_e020_0_comp_nf;
extern compop_func op_e028_0_comp_nf;
extern compop_func op_e030_0_comp_nf;
extern compop_func op_e038_0_comp_nf;
extern compop_func op_e040_0_comp_nf;
extern compop_func op_e048_0_comp_nf;
extern compop_func op_e050_0_comp_nf;
extern compop_func op_e058_0_comp_nf;
extern compop_func op_e060_0_comp_nf;
extern compop_func op_e068_0_comp_nf;
extern compop_func op_e070_0_comp_nf;
extern compop_func op_e078_0_comp_nf;
extern compop_func op_e080_0_comp_nf;
extern compop_func op_e088_0_comp_nf;
extern compop_func op_e090_0_comp_nf;
extern compop_func op_e098_0_comp_nf;
extern compop_func op_e0a0_0_comp_nf;
extern compop_func op_e0a8_0_comp_nf;
extern compop_func op_e0b0_0_comp_nf;
extern compop_func op_e0b8_0_comp_nf;
extern compop_func op_e0d0_0_comp_nf;
extern compop_func op_e0d8_0_comp_nf;

124
src/jit/gencomp_arm.cpp
View file

@ -108,7 +108,7 @@
//#define DISABLE_I_ROL
//#define DISABLE_I_ROR
//#define DISABLE_I_ROXL
#define DISABLE_I_ROXR
//#define DISABLE_I_ROXR
//#define DISABLE_I_ASRW
//#define DISABLE_I_ASLW
//#define DISABLE_I_LSRW
@ -275,32 +275,32 @@ static inline void gen_update_next_handler(void)
static void gen_writebyte(const char* address, const char* source)
{
comprintf("\twritebyte(%s,%s,scratchie);\n", address, source);
comprintf("\twritebyte(%s,%s);\n", address, source);
}
static void gen_writeword(const char* address, const char* source)
{
comprintf("\twriteword(%s,%s,scratchie);\n", address, source);
comprintf("\twriteword(%s,%s);\n", address, source);
}
static void gen_writelong(const char* address, const char* source)
{
comprintf("\twritelong(%s,%s,scratchie);\n", address, source);
comprintf("\twritelong(%s,%s);\n", address, source);
}
static void gen_readbyte(const char* address, const char* dest)
{
comprintf("\treadbyte(%s,%s,scratchie);\n", address, dest);
comprintf("\treadbyte(%s,%s);\n", address, dest);
}
static void gen_readword(const char* address, const char* dest)
{
comprintf("\treadword(%s,%s,scratchie);\n", address, dest);
comprintf("\treadword(%s,%s);\n", address, dest);
}
static void gen_readlong(const char* address, const char* dest)
{
comprintf("\treadlong(%s,%s,scratchie);\n", address, dest);
comprintf("\treadlong(%s,%s);\n", address, dest);
}
@ -443,7 +443,7 @@ static void genamode(amodes mode, const char *reg, wordsizes size, const char *n
break;
case Ad8r:
comprintf("\tint %sa=scratchie++;\n", name);
comprintf("\tcalc_disp_ea_020(%s+8,%s,%sa,scratchie);\n", reg, gen_nextiword(), name);
comprintf("\tcalc_disp_ea_020(%s+8,%s,%sa);\n", reg, gen_nextiword(), name);
break;
case PC16:
@ -460,7 +460,7 @@ static void genamode(amodes mode, const char *reg, wordsizes size, const char *n
start_brace();
comprintf("\tmov_l_ri(pctmp,address);\n");
comprintf("\tcalc_disp_ea_020(pctmp,%s,%sa,scratchie);\n", gen_nextiword(), name);
comprintf("\tcalc_disp_ea_020(pctmp,%s,%sa);\n", gen_nextiword(), name);
break;
case absw:
comprintf("\tint %sa = scratchie++;\n", name);
@ -659,7 +659,7 @@ static void genamode_new(amodes mode, const char *reg, wordsizes size, const cha
break;
case Ad8r:
comprintf("\tint %sa=scratchie++;\n", name);
comprintf("\tcalc_disp_ea_020(%s+8,%s,%sa,scratchie);\n", reg, gen_nextiword(), name);
comprintf("\tcalc_disp_ea_020(%s+8,%s,%sa);\n", reg, gen_nextiword(), name);
break;
case PC16:
@ -675,7 +675,7 @@ static void genamode_new(amodes mode, const char *reg, wordsizes size, const cha
comprintf("\tuae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
comprintf("\tmov_l_ri(pctmp,address);\n");
comprintf("\tcalc_disp_ea_020(pctmp,%s,%sa,scratchie);\n", gen_nextiword(), name);
comprintf("\tcalc_disp_ea_020(pctmp,%s,%sa);\n", gen_nextiword(), name);
break;
case absw:
comprintf("\tint %sa = scratchie++;\n", name);
@ -1006,7 +1006,7 @@ static void genmovemel(uae_u16 opcode)
comprintf("\tif (!special_mem) {\n");
/* Fast but unsafe... */
comprintf("\tget_n_addr(srca,native,scratchie);\n");
comprintf("\tget_n_addr(srca,native);\n");
comprintf("\tfor (i=0;i<16;i++) {\n"
"\t\tif ((mask>>i)&1) {\n");
@ -1037,11 +1037,11 @@ static void genmovemel(uae_u16 opcode)
"\t\t\tif ((mask>>i)&1) {\n");
switch(table68k[opcode].size) {
case sz_long:
comprintf("\t\t\t\treadlong(tmp,i,scratchie);\n"
comprintf("\t\t\t\treadlong(tmp,i);\n"
"\t\t\t\tarm_ADD_l_ri8(tmp,4);\n");
break;
case sz_word:
comprintf("\t\t\t\treadword(tmp,i,scratchie);\n"
comprintf("\t\t\t\treadword(tmp,i);\n"
"\t\t\t\tarm_ADD_l_ri8(tmp,2);\n");
break;
default: abort();
@ -1071,7 +1071,7 @@ static void genmovemle(uae_u16 opcode)
act of cleverness means that movmle must pay attention to special_mem,
or Genetic Species is a rather boring-looking game ;-) */
comprintf("\tif (!special_mem) {\n");
comprintf("\tget_n_addr(srca,native,scratchie);\n");
comprintf("\tget_n_addr(srca,native);\n");
if (table68k[opcode].dmode != Apdi) {
comprintf("\tfor (i=0;i<16;i++) {\n"
@ -1120,11 +1120,11 @@ static void genmovemle(uae_u16 opcode)
"\t\tif ((mask>>i)&1) {\n");
switch(table68k[opcode].size) {
case sz_long:
comprintf("\t\t\twritelong(tmp,i,scratchie);\n"
comprintf("\t\t\twritelong(tmp,i);\n"
"\t\t\tarm_ADD_l_ri8(tmp,4);\n");
break;
case sz_word:
comprintf("\t\t\twriteword(tmp,i,scratchie);\n"
comprintf("\t\t\twriteword(tmp,i);\n"
"\t\t\tarm_ADD_l_ri8(tmp,2);\n");
break;
default: abort();
@ -1136,11 +1136,11 @@ static void genmovemle(uae_u16 opcode)
switch(table68k[opcode].size) {
case sz_long:
comprintf("\t\t\tarm_SUB_l_ri8(srca,4);\n"
"\t\t\twritelong(srca,15-i,scratchie);\n");
"\t\t\twritelong(srca,15-i);\n");
break;
case sz_word:
comprintf("\t\t\tarm_SUB_l_ri8(srca,2);\n"
"\t\t\twriteword(srca,15-i,scratchie);\n");
"\t\t\twriteword(srca,15-i);\n");
break;
default: abort();
}
@ -1245,14 +1245,6 @@ static void gen_andsr(uae_u32 opcode, struct instr *curi, char* ssize) {
static void gen_asl(uae_u32 opcode, struct instr *curi, char* ssize) {
(void) opcode;
mayfail;
if (curi->smode == Dreg) {
comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
" FAIL(1);\n"
" " RETURN "\n"
"} \n");
start_brace();
}
comprintf("\t dont_care_flags();\n");
genamode_new(curi->smode, "srcreg", curi->size, "", 1, 0);
@ -1297,15 +1289,6 @@ static void gen_aslw(uae_u32 opcode, struct instr *curi, char* ssize) {
static void gen_asr(uae_u32 opcode, struct instr *curi, char* ssize) {
(void)opcode;
mayfail;
if (curi->smode == Dreg) {
comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
" FAIL(1);\n"
" " RETURN "\n"
"} \n");
start_brace();
}
comprintf("\t dont_care_flags();\n");
genamode_new(curi->smode, "srcreg", curi->size, "", 1, 0);
@ -1664,14 +1647,6 @@ static void gen_ext(uae_u32 opcode, struct instr *curi, char* ssize) {
static void gen_lsl(uae_u32 opcode, struct instr *curi, char* ssize) {
(void) opcode;
mayfail;
if (curi->smode == Dreg) {
comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
" FAIL(1);\n"
" " RETURN "\n"
"} \n");
start_brace();
}
comprintf("\tdont_care_flags();\n");
genamode_new(curi->smode, "srcreg", curi->size, "", 1, 0);
@ -1715,14 +1690,6 @@ static void gen_lslw(uae_u32 opcode, struct instr *curi, char* ssize) {
static void gen_lsr(uae_u32 opcode, struct instr *curi, char* ssize) {
(void) opcode;
mayfail;
if (curi->smode == Dreg) {
comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
" FAIL(1);\n"
" " RETURN "\n"
"} \n");
start_brace();
}
comprintf("\t dont_care_flags();\n");
genamode_new(curi->smode, "srcreg", curi->size, "", 1, 0);
@ -1970,14 +1937,6 @@ static void gen_orsr(uae_u32 opcode, struct instr *curi, char* ssize) {
static void gen_rol(uae_u32 opcode, struct instr *curi, char* ssize) {
(void) opcode;
mayfail;
if (curi->smode == Dreg) {
comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
" FAIL(1);\n"
" " RETURN "\n"
"} \n");
start_brace();
}
comprintf("\t dont_care_flags();\n");
genamode_new(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
genamode_new(curi->dmode, "dstreg", curi->size, "data", 1, 0);
@ -2009,14 +1968,6 @@ static void gen_rolw(uae_u32 opcode, struct instr *curi, char* ssize) {
static void gen_ror(uae_u32 opcode, struct instr *curi, char* ssize) {
(void) opcode;
mayfail;
if (curi->smode == Dreg) {
comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
" FAIL(1);\n"
" " RETURN "\n"
"} \n");
start_brace();
}
comprintf("\t dont_care_flags();\n");
genamode_new(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
genamode_new(curi->dmode, "dstreg", curi->size, "data", 1, 0);
@ -2048,14 +1999,6 @@ static void gen_rorw(uae_u32 opcode, struct instr *curi, char* ssize) {
static void gen_roxl(uae_u32 opcode, struct instr *curi, char* ssize) {
(void) opcode;
mayfail;
if (curi->smode == Dreg) {
comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
" FAIL(1);\n"
" " RETURN "\n"
"} \n");
start_brace();
}
isaddx;
comprintf("\t dont_care_flags();\n");
genamode_new(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
@ -2091,15 +2034,6 @@ static void gen_roxlw(uae_u32 opcode, struct instr *curi, char* ssize) {
static void gen_roxr(uae_u32 opcode, struct instr *curi, char* ssize) {
(void) opcode;
(void) ssize;
mayfail;
if (curi->smode == Dreg) {
comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
" FAIL(1);\n"
" " RETURN "\n"
"} \n");
start_brace();
}
isaddx;
comprintf("\t dont_care_flags();\n");
genamode_new(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
@ -2597,9 +2531,9 @@ static int gen_opcode(unsigned long int opcode)
comprintf("\tarm_ADD_l_ri8(offs,4);\n");
start_brace();
comprintf("\tint newad=scratchie++;\n"
"\treadlong(15,newad,scratchie);\n"
"\treadlong(15,newad);\n"
"\tmov_l_mr((uintptr)&regs.pc,newad);\n"
"\tget_n_addr_jmp(newad,PC_P,scratchie);\n"
"\tget_n_addr_jmp(newad,PC_P);\n"
"\tmov_l_mr((uintptr)&regs.pc_oldp,PC_P);\n"
"\tm68k_pc_offset=0;\n"
"\tarm_ADD_l(15,offs);\n");
@ -2614,7 +2548,7 @@ static int gen_opcode(unsigned long int opcode)
genamode_new(curi->smode, "srcreg", sz_long, "src", 1, 0);
genamode_new(curi->dmode, "dstreg", curi->size, "offs", 1, 0);
comprintf("\tsub_l_ri(15,4);\n"
"\twritelong_clobber(15,src,scratchie);\n"
"\twritelong_clobber(15,src);\n"
"\tmov_l_rr(src,15);\n");
comprintf("\tarm_ADD_l(15,offs);\n");
genastore("src", curi->smode, "srcreg", sz_long, "src");
@ -2626,7 +2560,7 @@ static int gen_opcode(unsigned long int opcode)
#endif
genamode_new(curi->smode, "srcreg", curi->size, "src", 1, 0);
comprintf("\tmov_l_rr(15,src);\n"
"\treadlong(15,src,scratchie);\n"
"\treadlong(15,src);\n"
"\tarm_ADD_l_ri8(15,4);\n");
genastore("src", curi->smode, "srcreg", curi->size, "src");
break;
@ -2636,9 +2570,9 @@ static int gen_opcode(unsigned long int opcode)
failure;
#endif
comprintf("\tint newad=scratchie++;\n"
"\treadlong(15,newad,scratchie);\n"
"\treadlong(15,newad);\n"
"\tmov_l_mr((uintptr)&regs.pc,newad);\n"
"\tget_n_addr_jmp(newad,PC_P,scratchie);\n"
"\tget_n_addr_jmp(newad,PC_P);\n"
"\tmov_l_mr((uintptr)&regs.pc_oldp,PC_P);\n"
"\tm68k_pc_offset=0;\n"
"\tarm_ADD_l_ri8(15,4);\n");
@ -2668,9 +2602,9 @@ static int gen_opcode(unsigned long int opcode)
comprintf("\tint ret=scratchie++;\n"
"\tmov_l_ri(ret,retadd);\n"
"\tsub_l_ri(15,4);\n"
"\twritelong_clobber(15,ret,scratchie);\n");
"\twritelong_clobber(15,ret);\n");
comprintf("\tmov_l_mr((uintptr)&regs.pc,srca);\n"
"\tget_n_addr_jmp(srca,PC_P,scratchie);\n"
"\tget_n_addr_jmp(srca,PC_P);\n"
"\tmov_l_mr((uintptr)&regs.pc_oldp,PC_P);\n"
"\tm68k_pc_offset=0;\n");
gen_update_next_handler();
@ -2683,7 +2617,7 @@ static int gen_opcode(unsigned long int opcode)
isjump;
genamode_new(curi->smode, "srcreg", curi->size, "src", 0, 0);
comprintf("\tmov_l_mr((uintptr)&regs.pc,srca);\n"
"\tget_n_addr_jmp(srca,PC_P,scratchie);\n"
"\tget_n_addr_jmp(srca,PC_P);\n"
"\tmov_l_mr((uintptr)&regs.pc_oldp,PC_P);\n"
"\tm68k_pc_offset=0;\n");
gen_update_next_handler();
@ -2702,7 +2636,7 @@ static int gen_opcode(unsigned long int opcode)
comprintf("\tint ret=scratchie++;\n"
"\tmov_l_ri(ret,retadd);\n"
"\tsub_l_ri(15,4);\n"
"\twritelong_clobber(15,ret,scratchie);\n");
"\twritelong_clobber(15,ret);\n");
comprintf("\tarm_ADD_l_ri(src,m68k_pc_offset_thisinst+2);\n");
comprintf("\tm68k_pc_offset=0;\n");
comprintf("\tarm_ADD_l(PC_P,src);\n");