Partial fixes regarding #240: Compilation fails on RPI1/Zero targets with new JIT FPU code
This commit is contained in:
Dimitris Panokostas
parent
4b5f2aeca9
commit
fdaaf45997
4 changed files with 88 additions and 40 deletions
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@ -945,44 +945,49 @@ STATIC_INLINE void compemu_raw_jcc_l_oponly(int cc)
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STATIC_INLINE void compemu_raw_handle_except(IMM cycles)
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{
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uae_u32* branchadd;
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uae_u32* branchadd;
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clobber_flags();
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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LDR_rR(REG_WORK1, REG_WORK2);
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clobber_flags();
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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#else
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auto offset = data_long_offs((uae_u32)(&jit_exception));
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LDR_rRI(REG_WORK2, RPC_INDEX, offset);
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#endif
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LDR_rR(REG_WORK1, REG_WORK2);
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TST_rr(REG_WORK1, REG_WORK1);
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BNE_i(1); // exception, skip LDR and target
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LDR_rRI(RPC_INDEX, RPC_INDEX, -4); // jump to next opcode
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branchadd = (uae_u32*)get_target();
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skip_long(); // emit of target (next opcode handler) will be done later
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// countdown -= scaled_cycles(totcycles);
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uae_s32 offs = (uae_u32)&countdown - (uae_u32)®s;
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// countdown -= scaled_cycles(totcycles);
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uae_s32 offs = (uae_u32)&countdown - (uae_u32)®s;
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LDR_rRI(REG_WORK1, R_REGSTRUCT, offs);
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if(CHECK32(cycles)) {
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SUBS_rri(REG_WORK1, REG_WORK1, cycles);
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} else {
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if (CHECK32(cycles)) {
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SUBS_rri(REG_WORK1, REG_WORK1, cycles);
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}
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else {
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK2, cycles);
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if(cycles >> 16)
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MOVT_ri16(REG_WORK2, cycles >> 16);
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MOVW_ri16(REG_WORK2, cycles);
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if (cycles >> 16)
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MOVT_ri16(REG_WORK2, cycles >> 16);
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#else
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int offs2 = data_long_offs(cycles);
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LDR_rRI(REG_WORK2, RPC_INDEX, offs2);
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int offs2 = data_long_offs(cycles);
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LDR_rRI(REG_WORK2, RPC_INDEX, offs2);
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#endif
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SUBS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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}
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SUBS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
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}
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STR_rRI(REG_WORK1, R_REGSTRUCT, offs);
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LDR_rRI(RPC_INDEX, RPC_INDEX, -4); // <popall_execute_exception>
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LDR_rRI(RPC_INDEX, RPC_INDEX, -4); // <popall_execute_exception>
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emit_long((uintptr)popall_execute_exception);
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// Write target of next instruction
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write_jmp_target(branchadd, (cpuop_func*)get_target());
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}
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STATIC_INLINE void compemu_raw_jl(uae_u32 t)
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@ -1140,8 +1145,6 @@ LENDFUNC(NONE,NONE,2,compemu_raw_endblock_pc_isconst,(IMM cycles, IMM v))
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* FPU stuff *
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*************************************************************************/
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#ifdef USE_JIT_FPU
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LOWFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s))
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{
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VMOV64_dd(d, s);
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@ -1153,8 +1156,13 @@ LOWFUNC(NONE,WRITE,2,compemu_raw_fmov_mr_drop,(MEMW mem, FR s))
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if(mem >= (uae_u32) ®s && mem < (uae_u32) ®s + 1020 && ((mem - (uae_u32) ®s) & 0x3) == 0) {
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VSTR64_dRi(s, R_REGSTRUCT, (mem - (uae_u32) ®s));
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} else {
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK1, mem);
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MOVT_ri16(REG_WORK1, mem >> 16);
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#else
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auto offs = data_long_offs(mem);
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LDR_rRI(REG_WORK1, RPC_INDEX, offs);
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#endif
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VSTR64_dRi(s, REG_WORK1, 0);
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}
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}
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@ -1166,8 +1174,13 @@ LOWFUNC(NONE,READ,2,compemu_raw_fmov_rm,(FW d, MEMR mem))
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if(mem >= (uae_u32) ®s && mem < (uae_u32) ®s + 1020 && ((mem - (uae_u32) ®s) & 0x3) == 0) {
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VLDR64_dRi(d, R_REGSTRUCT, (mem - (uae_u32) ®s));
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} else {
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK1, mem);
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MOVT_ri16(REG_WORK1, mem >> 16);
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#else
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auto offs = data_long_offs(mem);
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LDR_rRI(REG_WORK1, RPC_INDEX, offs);
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#endif
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VLDR64_dRi(d, REG_WORK1, 0);
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}
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}
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@ -1266,16 +1279,26 @@ LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_10,(FW r))
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LOWFUNC(NONE,READ,2,raw_fmov_d_rm,(FW r, MEMR m))
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{
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK1, m);
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MOVT_ri16(REG_WORK1, m >> 16);
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#else
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auto offs = data_long_offs(m);
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LDR_rRI(REG_WORK1, RPC_INDEX, offs);
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#endif
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VLDR64_dRi(r, REG_WORK1, 0);
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}
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LENDFUNC(NONE,READ,2,raw_fmov_d_rm,(FW r, MEMR m))
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LOWFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
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{
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MOVW_ri16(REG_WORK1, m);
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MOVT_ri16(REG_WORK1, m >> 16);
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK1, m);
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MOVT_ri16(REG_WORK1, m >> 16);
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#else
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auto offs = data_long_offs(m);
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LDR_rRI(REG_WORK1, RPC_INDEX, offs);
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#endif
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VLDR32_sRi(SCRATCH_F32_1, REG_WORK1, 0);
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VCVT32to64_ds(r, SCRATCH_F32_1);
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}
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@ -1407,10 +1430,13 @@ LENDFUNC(NONE,NONE,2,raw_fmovs_rr,(FW d, FR s))
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LOWFUNC(NONE,NONE,3,raw_ffunc_rr,(double (*func)(double), FW d, FR s))
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{
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VMOV64_dd(0, s);
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK1, (uae_u32)func);
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MOVT_ri16(REG_WORK1, ((uae_u32)func) >> 16);
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#else
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auto offs = data_long_offs(uae_u32(func));
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LDR_rRI(REG_WORK1, RPC_INDEX, offs);
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#endif
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PUSH(RLR_INDEX);
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BLX_r(REG_WORK1);
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POP(RLR_INDEX);
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@ -1431,8 +1457,13 @@ LOWFUNC(NONE,NONE,3,raw_fpowx_rr,(uae_u32 x, FW d, FR s))
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VMOV64_dd(1, s);
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MOVW_ri16(REG_WORK1, (uae_u32)func);
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MOVT_ri16(REG_WORK1, ((uae_u32)func) >> 16);
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK1, (uae_u32)func);
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MOVT_ri16(REG_WORK1, ((uae_u32)func) >> 16);
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#else
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auto offs = data_long_offs(uae_u32(func));
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LDR_rRI(REG_WORK1, RPC_INDEX, offs);
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#endif
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PUSH(RLR_INDEX);
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BLX_r(REG_WORK1);
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@ -1670,4 +1701,3 @@ LOWFUNC(NONE,NONE,1,raw_roundingmode,(IMM mode))
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}
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LENDFUNC(NONE,NONE,1,raw_roundingmode,(IMM mode))
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#endif // USE_JIT_FPU
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@ -491,8 +491,6 @@ STATIC_INLINE void emit_jmp_target(uae_u32 a) {
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* FPU stuff *
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*************************************************************************/
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#ifdef USE_JIT_FPU
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MIDFUNC(1,f_forget_about,(FW r))
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{
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if (f_isinreg(r))
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@ -955,4 +953,4 @@ MIDFUNC(1,roundingmode,(IMM mode))
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MENDFUNC(1,roundingmode,(IMM mode))
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#endif // USE_JIT_FPU
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@ -1864,8 +1864,13 @@ MENDFUNC(2,jff_DBCC,(RR2 d, IMM cc))
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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#else
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auto offs = data_long_offs((uae_u32)(&jit_exception));
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LDR_rRI(REG_WORK2, RPC_INDEX, offs);
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#endif
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STR_rR(REG_WORK1, REG_WORK2);
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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@ -1909,8 +1914,13 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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#else
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auto offs = data_long_offs((uae_u32)(&jit_exception));
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LDR_rRI(REG_WORK2, RPC_INDEX, offs);
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#endif
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STR_rR(REG_WORK1, REG_WORK2);
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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@ -1973,8 +1983,13 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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#else
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auto offs = data_long_offs((uae_u32)(&jit_exception));
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LDR_rRI(REG_WORK2, RPC_INDEX, offs);
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#endif
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STR_rR(REG_WORK1, REG_WORK2);
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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@ -2028,8 +2043,13 @@ MIDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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#ifdef ARMV6T2
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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#else
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auto offs = data_long_offs((uae_u32)(&jit_exception));
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LDR_rRI(REG_WORK2, RPC_INDEX, offs);
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#endif
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STR_rR(REG_WORK1, REG_WORK2);
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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@ -1347,7 +1347,7 @@ static int rmw(int r, int wsize, int rsize)
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/********************************************************************
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* FPU register status handling. EMIT TIME! *
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********************************************************************/
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#ifdef USE_JIT_FPU
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STATIC_INLINE void f_tomem_drop(int r)
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{
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if (live.fate[r].status == DIRTY) {
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@ -1480,7 +1480,7 @@ static void fflags_into_flags_internal(void)
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f_unlock(r);
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live_flags();
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}
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#endif
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#if defined(CPU_arm)
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#include "compemu_midfunc_arm.cpp"
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